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add verilog files for project one through five

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This commit is contained in:
Konarak
2024-10-17 14:36:58 -04:00
parent b16bfcfd43
commit 792efa70cd
37 changed files with 871 additions and 275 deletions
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11
01_Boolean_Logic/And.v
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@@ -6,11 +6,14 @@
`default_nettype none
module And(
input a,
input b,
output out
input a,
input b,
output out
);
// Put your code here:
// Put your code here:
wire nand1;
Nand NAND1(a, b, nand1);
Nand NAND2(nand1, nand1, out);
endmodule

25
01_Boolean_Logic/And16.v
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@@ -5,11 +5,26 @@
`default_nettype none
module And16(
input [15:0] a,
input [15:0] b,
output [15:0] out
input [15:0] a,
input [15:0] b,
output [15:0] out
);
// Put your code here:
// Put your code here:
And AND0(a[0], b[0], out[0]);
And AND1(a[1], b[1], out[1]);
And AND2(a[2], b[2], out[2]);
And AND3(a[3], b[3], out[3]);
And AND4(a[4], b[4], out[4]);
And AND5(a[5], b[5], out[5]);
And AND6(a[6], b[6], out[6]);
And AND7(a[7], b[7], out[7]);
And AND8(a[8], b[8], out[8]);
And AND9(a[9], b[9], out[9]);
And AND10(a[10], b[10], out[10]);
And AND11(a[11], b[11], out[11]);
And AND12(a[12], b[12], out[12]);
And AND13(a[13], b[13], out[13]);
And AND14(a[14], b[14], out[14]);
And AND15(a[15], b[15], out[15]);
endmodule

8
01_Boolean_Logic/Buffer.v
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@@ -5,10 +5,10 @@
`default_nettype none
module Buffer(
input in,
output out
input in,
output out
);
// Put your code here:
// Put your code here:
assign out = in;
endmodule

8
01_Boolean_Logic/Buffer16.v
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@@ -5,10 +5,10 @@
`default_nettype none
module Buffer16(
input [15:0] in,
output [15:0] out
input [15:0] in,
output [15:0] out
);
// Put your code here:
// Put your code here:
assign out[15:0] = in[15:0];
endmodule

12
01_Boolean_Logic/DMux.v
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@@ -6,12 +6,16 @@
`default_nettype none
module DMux(
input in,
input sel,
input in,
input sel,
output a,
output b
output b
);
// Put your code here:
// Put your code here:
wire nsel;
Not NOT1(sel, nsel);
And AND1(in, sel, b);
And AND2(in, nsel, a);
endmodule

20
01_Boolean_Logic/DMux4Way.v
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@@ -8,14 +8,20 @@
`default_nettype none
module DMux4Way(
input in,
input [1:0] sel,
input in,
input [1:0] sel,
output a,
output b,
output c,
output d
output b,
output c,
output d
);
// Put your code here:
// Put your code here:
wire outx;
wire outy;
DMux DMUXA(in, sel[1], outx, outy);
DMux DMUXB(outx, sel[0], a, b);
DMux DMUXC(outy, sel[0], c, d);
endmodule

34
01_Boolean_Logic/DMux8Way.v
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@@ -8,18 +8,32 @@
`default_nettype none
module DMux8Way(
input in,
input [2:0] sel,
input in,
input [2:0] sel,
output a,
output b,
output c,
output d,
output e,
output f,
output g,
output h
output b,
output c,
output d,
output e,
output f,
output g,
output h
);
// Put your code here:
// Put your code here:
wire outi;
wire outj;
wire outw;
wire outx;
wire outy;
wire outz;
DMux DMUXA(in, sel[2], outi, outj);
DMux DMUXB(outi, sel[1], outw, outx);
DMux DMUXC(outj, sel[1], outy, outz);
DMux DMUXD(outw, sel[0], a, b);
DMux DMUXE(outx, sel[0], c, d);
DMux DMUXF(outy, sel[0], e, f);
DMux DMUXG(outz, sel[0], g, h);
endmodule

19
01_Boolean_Logic/Mux.v
View File

@@ -1,4 +1,4 @@
/**
/**
* Multiplexor:
* out = a if sel == 0
* b otherwise
@@ -6,12 +6,19 @@
`default_nettype none
module Mux(
input a,
input b,
input sel,
output out
input a,
input b,
input sel,
output out
);
// Put your code here:
// Put your code here:
wire nsel;
wire outx;
wire outy;
Not NOT1(sel, nsel);
And AND1(b, sel, outx);
And AND2(a, nsel, outy);
Or OR(outx, outy, out);
endmodule

31
01_Boolean_Logic/Mux16.v
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@@ -1,17 +1,32 @@
/**
* 16-bit multiplexor:
* for i = 0..15 out[i] = a[i] if sel == 0
* 16-bit multiplexor:
* for i = 0..15 out[i] = a[i] if sel == 0
* b[i] if sel == 1
*/
`default_nettype none
module Mux16(
input [15:0] a,
input [15:0] b,
input sel,
output [15:0] out
input [15:0] a,
input [15:0] b,
input sel,
output [15:0] out
);
// Put your code here:
// Put your code here:
Mux MUX0(a[0], b[0], sel, out[0]);
Mux MUX1(a[1], b[1], sel, out[1]);
Mux MUX2(a[2], b[2], sel, out[2]);
Mux MUX3(a[3], b[3], sel, out[3]);
Mux MUX4(a[4], b[4], sel, out[4]);
Mux MUX5(a[5], b[5], sel, out[5]);
Mux MUX6(a[6], b[6], sel, out[6]);
Mux MUX7(a[7], b[7], sel, out[7]);
Mux MUX8(a[8], b[8], sel, out[8]);
Mux MUX9(a[9], b[9], sel, out[9]);
Mux MUX10(a[10], b[10], sel, out[10]);
Mux MUX11(a[11], b[11], sel, out[11]);
Mux MUX12(a[12], b[12], sel, out[12]);
Mux MUX13(a[13], b[13], sel, out[13]);
Mux MUX14(a[14], b[14], sel, out[14]);
Mux MUX15(a[15], b[15], sel, out[15]);
endmodule

25
01_Boolean_Logic/Mux4Way16.v
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@@ -1,19 +1,24 @@
/**
* 16-bit multiplexor:
* for i = 0..15 out[i] = a[i] if sel == 0
* 16-bit multiplexor:
* for i = 0..15 out[i] = a[i] if sel == 0
* b[i] if sel == 1
*/
`default_nettype none
module Mux4Way16(
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input [1:0] sel,
output [15:0] out
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input [1:0] sel,
output [15:0] out
);
// Put your code here:
// Put your code here:
wire [15:0] outab;
wire [15:0] outcd;
Mux16 MUX16A(a[15:0], b[15:0], sel[0], outab[15:0]);
Mux16 MUX16B(c[15:0], d[15:0], sel[0], outcd[15:0]);
Mux16 MUX16(outab[15:0], outcd[15:0], sel[1], out[15:0]);
endmodule

41
01_Boolean_Logic/Mux8Way16.v
View File

@@ -1,23 +1,38 @@
/**
* 16-bit multiplexor:
* for i = 0..15 out[i] = a[i] if sel == 0
* 16-bit multiplexor:
* for i = 0..15 out[i] = a[i] if sel == 0
* b[i] if sel == 1
*/
`default_nettype none
module Mux8Way16(
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input [15:0] e,
input [15:0] f,
input [15:0] g,
input [15:0] h,
input [2:0] sel,
output [15:0] out
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input [15:0] e,
input [15:0] f,
input [15:0] g,
input [15:0] h,
input [2:0] sel,
output [15:0] out
);
// Put your code here:
// Put your code here:
wire [15:0] outab;
wire [15:0] outcd;
wire [15:0] outef;
wire [15:0] outgh;
wire [15:0] outabcd;
wire [15:0] outefgh;
Mux16 MUX16A(a[15:0], b[15:0], sel[0], outab[15:0]);
Mux16 MUX16B(c[15:0], d[15:0], sel[0], outcd[15:0]);
Mux16 MUX16C(e[15:0], f[15:0], sel[0], outef[15:0]);
Mux16 MUX16D(g[15:0], h[15:0], sel[0], outgh[15:0]);
Mux16 MUX16E(outab[15:0], outcd[15:0], sel[1], outabcd[15:0]);
Mux16 MUX16F(outef[15:0], outgh[15:0], sel[1], outefgh[15:0]);
Mux16 MUX16(outabcd[15:0], outefgh[15:0], sel[2], out[15:0]);
endmodule

14
01_Boolean_Logic/Nand.v
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@@ -1,18 +1,18 @@
/**
* Nand gate:
* Nand gate:
* out = 0 if (a == 1 and b == 1)
* 1 otherwise
*/
`default_nettype none
module Nand(
input a,
input b,
output out
input a,
input b,
output out
);
// No need to implement this chip
// This chip is implemented using verilog primitives
nand(out,a,b);
// No need to implement this chip
// This chip is implemented using verilog primitives
nand(out,a,b);
endmodule

8
01_Boolean_Logic/Not.v
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@@ -5,10 +5,10 @@
`default_nettype none
module Not(
input in,
output out
input in,
output out
);
// Put your code here:
// Put your code here:
Nand NOT1(in, in, out);
endmodule

23
01_Boolean_Logic/Not16.v
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@@ -5,10 +5,25 @@
`default_nettype none
module Not16(
input [15:0] in,
output [15:0] out
input [15:0] in,
output [15:0] out
);
// Put your code here:
// Put your code here:
Not NOT0(in[0], out[0]);
Not NOT1(in[1], out[1]);
Not NOT2(in[2], out[2]);
Not NOT3(in[3], out[3]);
Not NOT4(in[4], out[4]);
Not NOT5(in[5], out[5]);
Not NOT6(in[6], out[6]);
Not NOT7(in[7], out[7]);
Not NOT8(in[8], out[8]);
Not NOT9(in[9], out[9]);
Not NOT10(in[10], out[10]);
Not NOT11(in[11], out[11]);
Not NOT12(in[12], out[12]);
Not NOT13(in[13], out[13]);
Not NOT14(in[14], out[14]);
Not NOT15(in[15], out[15]);
endmodule

13
01_Boolean_Logic/Or.v
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@@ -6,11 +6,16 @@
`default_nettype none
module Or(
input a,
input b,
output out
input a,
input b,
output out
);
// Put your code here:
// Put your code here:
wire nanda;
wire nandb;
Nand NAND1(a, a, nanda);
Nand NAND2(b, b, nandb);
Nand NAND3(nanda, nandb, out);
endmodule

27
01_Boolean_Logic/Or16.v
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@@ -1,15 +1,30 @@
/**
* 16-bit bitwise And:
* for i = 0..15: out[i] = (a[i] and b[i])
* for i = 0: out[i] = (a[i] and b[i])
*/
`default_nettype none
module Or16(
input [15:0] a,
input [15:0] b,
output [15:0] out
input [15:0] a,
input [15:0] b,
output [15:0] out
);
// Put your code here:
// Put your code here:
Or OR0(a[0], b[0], out[0]);
Or OR1(a[1], b[1], out[1]);
Or OR2(a[2], b[2], out[2]);
Or OR3(a[3], b[3], out[3]);
Or OR4(a[4], b[4], out[4]);
Or OR5(a[5], b[5], out[5]);
Or OR6(a[6], b[6], out[6]);
Or OR7(a[7], b[7], out[7]);
Or OR8(a[8], b[8], out[8]);
Or OR9(a[9], b[9], out[9]);
Or OR10(a[10], b[10], out[10]);
Or OR11(a[11], b[11], out[11]);
Or OR12(a[12], b[12], out[12]);
Or OR13(a[13], b[13], out[13]);
Or OR14(a[14], b[14], out[14]);
Or OR15(a[15], b[15], out[15]);
endmodule

20
01_Boolean_Logic/Or8Way.v
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@@ -5,10 +5,24 @@
`default_nettype none
module Or8Way(
input [7:0] in,
output out
input [7:0] in,
output out
);
// Put your code here:
// Put your code here:
wire outA;
wire outB;
wire outC;
wire outD;
wire outE;
wire outF;
Or OR0(in[0], in[1], outA);
Or OR2(in[2], outA, outB);
Or OR3(in[3], outB, outC);
Or OR4(in[4], outC, outD);
Or OR5(in[5], outD, outE);
Or OR6(in[6], outE, outF);
Or OR7(in[7], outF, out);
endmodule

18
01_Boolean_Logic/Xor.v
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@@ -5,11 +5,21 @@
`default_nettype none
module Xor(
input a,
input b,
output out
input a,
input b,
output out
);
// Put your code here:
// Put your code here:
wire nota;
wire notb;
Not NOT1(a, nota);
Not NOT2(b, notb);
wire w1;
wire w2;
And AND1(a, notb, w1);
And AND2(nota, b, w2);
Or OR(w1, w2, out);
endmodule