diff --git a/01_Boolean_Logic/And.v b/01_Boolean_Logic/And.v
index 0bc4814..bce60f3 100644
--- a/01_Boolean_Logic/And.v
+++ b/01_Boolean_Logic/And.v
@@ -6,11 +6,14 @@
 
 `default_nettype none
 module And(
-	input a,
-	input b,
-	output out
+    input a,
+    input b,
+    output out
 );
 
-	// Put your code here:
+    // Put your code here:
+    wire nand1;
 
+    Nand NAND1(a, b, nand1);
+    Nand NAND2(nand1, nand1, out);
 endmodule
diff --git a/01_Boolean_Logic/And16.v b/01_Boolean_Logic/And16.v
index e0e7ffd..7b48734 100644
--- a/01_Boolean_Logic/And16.v
+++ b/01_Boolean_Logic/And16.v
@@ -5,11 +5,26 @@
 
 `default_nettype none
 module And16(
-	input [15:0] a,
-	input [15:0] b,
-	output [15:0] out
+    input [15:0] a,
+    input [15:0] b,
+    output [15:0] out
 );
 
-	// Put your code here:
-
+    // Put your code here:
+    And AND0(a[0], b[0], out[0]);
+    And AND1(a[1], b[1], out[1]);
+    And AND2(a[2], b[2], out[2]);
+    And AND3(a[3], b[3], out[3]);
+    And AND4(a[4], b[4], out[4]);
+    And AND5(a[5], b[5], out[5]);
+    And AND6(a[6], b[6], out[6]);
+    And AND7(a[7], b[7], out[7]);
+    And AND8(a[8], b[8], out[8]);
+    And AND9(a[9], b[9], out[9]);
+    And AND10(a[10], b[10], out[10]);
+    And AND11(a[11], b[11], out[11]);
+    And AND12(a[12], b[12], out[12]);
+    And AND13(a[13], b[13], out[13]);
+    And AND14(a[14], b[14], out[14]);
+    And AND15(a[15], b[15], out[15]);
 endmodule
diff --git a/01_Boolean_Logic/Buffer.v b/01_Boolean_Logic/Buffer.v
index 4b4a7e9..b8b8810 100644
--- a/01_Boolean_Logic/Buffer.v
+++ b/01_Boolean_Logic/Buffer.v
@@ -5,10 +5,10 @@
 
 `default_nettype none
 module Buffer(
-	input in,
-	output out
+    input in,
+    output out
 );
 
-	// Put your code here:
-
+    // Put your code here:
+    assign out = in;
 endmodule
diff --git a/01_Boolean_Logic/Buffer16.v b/01_Boolean_Logic/Buffer16.v
index 911a9fd..1d60209 100644
--- a/01_Boolean_Logic/Buffer16.v
+++ b/01_Boolean_Logic/Buffer16.v
@@ -5,10 +5,10 @@
 
 `default_nettype none
 module Buffer16(
-	input [15:0] in,
-	output [15:0] out
+    input [15:0] in,
+    output [15:0] out
 );
 
-	// Put your code here:
-
+    // Put your code here:
+    assign out[15:0] = in[15:0];
 endmodule
diff --git a/01_Boolean_Logic/DMux.v b/01_Boolean_Logic/DMux.v
index 01b68b5..65c9c32 100644
--- a/01_Boolean_Logic/DMux.v
+++ b/01_Boolean_Logic/DMux.v
@@ -6,12 +6,16 @@
 
 `default_nettype none
 module DMux(
-	input in,
-	input sel,
+    input in,
+    input sel,
     output a,
-	output b
+    output b
 );
 
-	// Put your code here:
+    // Put your code here:
+    wire nsel;
 
+    Not NOT1(sel, nsel);
+    And AND1(in, sel, b);
+    And AND2(in, nsel, a);
 endmodule
diff --git a/01_Boolean_Logic/DMux4Way.v b/01_Boolean_Logic/DMux4Way.v
index 495c851..e5a6501 100644
--- a/01_Boolean_Logic/DMux4Way.v
+++ b/01_Boolean_Logic/DMux4Way.v
@@ -8,14 +8,20 @@
 
 `default_nettype none
 module DMux4Way(
-	input in,
-	input [1:0] sel,
+    input in,
+    input [1:0] sel,
     output a,
-	output b,
-	output c,
-	output d
+    output b,
+    output c,
+    output d
 );
-	
-	// Put your code here:	
+
+    // Put your code here:
+    wire outx;
+    wire outy;
+
+    DMux DMUXA(in, sel[1], outx, outy);
+    DMux DMUXB(outx, sel[0], a, b);
+    DMux DMUXC(outy, sel[0], c, d);
 
 endmodule
diff --git a/01_Boolean_Logic/DMux8Way.v b/01_Boolean_Logic/DMux8Way.v
index 3626055..d3360bd 100644
--- a/01_Boolean_Logic/DMux8Way.v
+++ b/01_Boolean_Logic/DMux8Way.v
@@ -8,18 +8,32 @@
 
 `default_nettype none
 module DMux8Way(
-	input in,
-	input [2:0] sel,
+    input in,
+    input [2:0] sel,
     output a,
-	output b,
-	output c,
-	output d,
-	output e,
-	output f,
-	output g,
-	output h
+    output b,
+    output c,
+    output d,
+    output e,
+    output f,
+    output g,
+    output h
 );
 
-	// Put your code here:
+    // Put your code here:
+    wire outi;
+    wire outj;
+    wire outw;
+    wire outx;
+    wire outy;
+    wire outz;
+
+    DMux DMUXA(in,   sel[2], outi, outj);
+    DMux DMUXB(outi, sel[1], outw, outx);
+    DMux DMUXC(outj, sel[1], outy, outz);
+    DMux DMUXD(outw, sel[0], a, b);
+    DMux DMUXE(outx, sel[0], c, d);
+    DMux DMUXF(outy, sel[0], e, f);
+    DMux DMUXG(outz, sel[0], g, h);
 
 endmodule
diff --git a/01_Boolean_Logic/Mux.v b/01_Boolean_Logic/Mux.v
index 0b799e4..58bed22 100644
--- a/01_Boolean_Logic/Mux.v
+++ b/01_Boolean_Logic/Mux.v
@@ -1,4 +1,4 @@
-/** 
+/**
  * Multiplexor:
  * out = a if sel == 0
  *       b otherwise
@@ -6,12 +6,19 @@
 
 `default_nettype none
 module Mux(
-	input a,
-	input b,
-	input sel,
-	output out
+    input a,
+    input b,
+    input sel,
+    output out
 );
 
-	// Put your code here:
+    // Put your code here:
+    wire nsel;
+    wire outx;
+    wire outy;
 
+    Not NOT1(sel, nsel);
+    And AND1(b, sel, outx);
+    And AND2(a, nsel, outy);
+    Or OR(outx, outy, out);
 endmodule
diff --git a/01_Boolean_Logic/Mux16.v b/01_Boolean_Logic/Mux16.v
index 2589a4e..ad11fba 100644
--- a/01_Boolean_Logic/Mux16.v
+++ b/01_Boolean_Logic/Mux16.v
@@ -1,17 +1,32 @@
 /**
- * 16-bit multiplexor: 
- * for i = 0..15 out[i] = a[i] if sel == 0 
+ * 16-bit multiplexor:
+ * for i = 0..15 out[i] = a[i] if sel == 0
  *                        b[i] if sel == 1
  */
 
 `default_nettype none
 module Mux16(
-	input [15:0] a,
-	input [15:0] b,
-   	input sel,
-	output [15:0] out
+    input [15:0] a,
+    input [15:0] b,
+       input sel,
+    output [15:0] out
 );
 
-	// Put your code here:
-
+    // Put your code here:
+    Mux MUX0(a[0], b[0], sel, out[0]);
+    Mux MUX1(a[1], b[1], sel, out[1]);
+    Mux MUX2(a[2], b[2], sel, out[2]);
+    Mux MUX3(a[3], b[3], sel, out[3]);
+    Mux MUX4(a[4], b[4], sel, out[4]);
+    Mux MUX5(a[5], b[5], sel, out[5]);
+    Mux MUX6(a[6], b[6], sel, out[6]);
+    Mux MUX7(a[7], b[7], sel, out[7]);
+    Mux MUX8(a[8], b[8], sel, out[8]);
+    Mux MUX9(a[9], b[9], sel, out[9]);
+    Mux MUX10(a[10], b[10], sel, out[10]);
+    Mux MUX11(a[11], b[11], sel, out[11]);
+    Mux MUX12(a[12], b[12], sel, out[12]);
+    Mux MUX13(a[13], b[13], sel, out[13]);
+    Mux MUX14(a[14], b[14], sel, out[14]);
+    Mux MUX15(a[15], b[15], sel, out[15]);
 endmodule
diff --git a/01_Boolean_Logic/Mux4Way16.v b/01_Boolean_Logic/Mux4Way16.v
index f5a1b3a..6156ace 100644
--- a/01_Boolean_Logic/Mux4Way16.v
+++ b/01_Boolean_Logic/Mux4Way16.v
@@ -1,19 +1,24 @@
 /**
- * 16-bit multiplexor: 
- * for i = 0..15 out[i] = a[i] if sel == 0 
+ * 16-bit multiplexor:
+ * for i = 0..15 out[i] = a[i] if sel == 0
  *                        b[i] if sel == 1
  */
 
 `default_nettype none
 module Mux4Way16(
-	input [15:0] a,
-	input [15:0] b,
-	input [15:0] c,
-	input [15:0] d,
-   	input [1:0] sel,
-	output [15:0] out
+    input [15:0] a,
+    input [15:0] b,
+    input [15:0] c,
+    input [15:0] d,
+       input [1:0] sel,
+    output [15:0] out
 );
-	
-	// Put your code here:
 
+    // Put your code here:
+    wire  [15:0] outab;
+    wire  [15:0] outcd;
+
+    Mux16 MUX16A(a[15:0], b[15:0], sel[0], outab[15:0]);
+    Mux16 MUX16B(c[15:0], d[15:0], sel[0], outcd[15:0]);
+    Mux16 MUX16(outab[15:0], outcd[15:0], sel[1], out[15:0]);
 endmodule
diff --git a/01_Boolean_Logic/Mux8Way16.v b/01_Boolean_Logic/Mux8Way16.v
index b2d2eb0..2f64ff3 100644
--- a/01_Boolean_Logic/Mux8Way16.v
+++ b/01_Boolean_Logic/Mux8Way16.v
@@ -1,23 +1,38 @@
 /**
- * 16-bit multiplexor: 
- * for i = 0..15 out[i] = a[i] if sel == 0 
+ * 16-bit multiplexor:
+ * for i = 0..15 out[i] = a[i] if sel == 0
  *                        b[i] if sel == 1
  */
 
 `default_nettype none
 module Mux8Way16(
-	input [15:0] a,
-	input [15:0] b,
-	input [15:0] c,
-	input [15:0] d,
-	input [15:0] e,
-	input [15:0] f,
-	input [15:0] g,
-	input [15:0] h,
-   	input [2:0] sel,
-	output [15:0] out
+    input [15:0] a,
+    input [15:0] b,
+    input [15:0] c,
+    input [15:0] d,
+    input [15:0] e,
+    input [15:0] f,
+    input [15:0] g,
+    input [15:0] h,
+       input [2:0] sel,
+    output [15:0] out
 );
 
-	// Put your code here:
+    // Put your code here:
+    wire  [15:0] outab;
+    wire  [15:0] outcd;
+    wire  [15:0] outef;
+    wire  [15:0] outgh;
+    wire  [15:0] outabcd;
+    wire  [15:0] outefgh;
+
+
+    Mux16 MUX16A(a[15:0], b[15:0], sel[0], outab[15:0]);
+    Mux16 MUX16B(c[15:0], d[15:0], sel[0], outcd[15:0]);
+    Mux16 MUX16C(e[15:0], f[15:0], sel[0], outef[15:0]);
+    Mux16 MUX16D(g[15:0], h[15:0], sel[0], outgh[15:0]);
+    Mux16 MUX16E(outab[15:0], outcd[15:0], sel[1], outabcd[15:0]);
+    Mux16 MUX16F(outef[15:0], outgh[15:0], sel[1], outefgh[15:0]);
+    Mux16 MUX16(outabcd[15:0], outefgh[15:0], sel[2], out[15:0]);
 
 endmodule
diff --git a/01_Boolean_Logic/Nand.v b/01_Boolean_Logic/Nand.v
index 3e22553..9c76bc2 100644
--- a/01_Boolean_Logic/Nand.v
+++ b/01_Boolean_Logic/Nand.v
@@ -1,18 +1,18 @@
 /**
- * Nand gate: 
+ * Nand gate:
  * out = 0 if (a == 1 and b == 1)
  *       1 otherwise
  */
 
 `default_nettype none
 module Nand(
-	input a,
-	input b,
-	output out
+    input a,
+    input b,
+    output out
 );
 
-	// No need to implement this chip
-	// This chip is implemented using verilog primitives
-	nand(out,a,b);
+    // No need to implement this chip
+    // This chip is implemented using verilog primitives
+    nand(out,a,b);
 
 endmodule
diff --git a/01_Boolean_Logic/Not.v b/01_Boolean_Logic/Not.v
index 56117e0..741ae70 100644
--- a/01_Boolean_Logic/Not.v
+++ b/01_Boolean_Logic/Not.v
@@ -5,10 +5,10 @@
 
 `default_nettype none
 module Not(
-	input in,
-	output out
+    input in,
+    output out
 );
 
-	// Put your code here:
-
+    // Put your code here:
+    Nand NOT1(in, in, out);
 endmodule
diff --git a/01_Boolean_Logic/Not16.v b/01_Boolean_Logic/Not16.v
index fd7e664..384bb37 100644
--- a/01_Boolean_Logic/Not16.v
+++ b/01_Boolean_Logic/Not16.v
@@ -5,10 +5,25 @@
 
 `default_nettype none
 module Not16(
-	input [15:0] in,
-	output [15:0] out
+    input [15:0] in,
+    output [15:0] out
 );
 
-	// Put your code here:
-
+    // Put your code here:
+    Not NOT0(in[0], out[0]);
+    Not NOT1(in[1], out[1]);
+    Not NOT2(in[2], out[2]);
+    Not NOT3(in[3], out[3]);
+    Not NOT4(in[4], out[4]);
+    Not NOT5(in[5], out[5]);
+    Not NOT6(in[6], out[6]);
+    Not NOT7(in[7], out[7]);
+    Not NOT8(in[8], out[8]);
+    Not NOT9(in[9], out[9]);
+    Not NOT10(in[10], out[10]);
+    Not NOT11(in[11], out[11]);
+    Not NOT12(in[12], out[12]);
+    Not NOT13(in[13], out[13]);
+    Not NOT14(in[14], out[14]);
+    Not NOT15(in[15], out[15]);
 endmodule
diff --git a/01_Boolean_Logic/Or.v b/01_Boolean_Logic/Or.v
index 577dbb2..3d6b11e 100644
--- a/01_Boolean_Logic/Or.v
+++ b/01_Boolean_Logic/Or.v
@@ -6,11 +6,16 @@
 
 `default_nettype none
 module Or(
-	input a,
-	input b,
-	output out
+    input a,
+    input b,
+    output out
 );
 
-	// Put your code here:
+    // Put your code here:
+    wire nanda;
+    wire nandb;
 
+    Nand NAND1(a, a, nanda);
+    Nand NAND2(b, b, nandb);
+    Nand NAND3(nanda, nandb, out);
 endmodule
diff --git a/01_Boolean_Logic/Or16.v b/01_Boolean_Logic/Or16.v
index 946e864..dff2a1d 100644
--- a/01_Boolean_Logic/Or16.v
+++ b/01_Boolean_Logic/Or16.v
@@ -1,15 +1,30 @@
 /**
  * 16-bit bitwise And:
- * for i = 0..15: out[i] = (a[i] and b[i])
+ * for i = 0: out[i] = (a[i] and b[i])
  */
 
 `default_nettype none
 module Or16(
-	input [15:0] a,
-	input [15:0] b,
-	output [15:0] out
+    input [15:0] a,
+    input [15:0] b,
+    output [15:0] out
 );
 
-	// Put your code here:
-
+    // Put your code here:
+    Or OR0(a[0], b[0], out[0]);
+    Or OR1(a[1], b[1], out[1]);
+    Or OR2(a[2], b[2], out[2]);
+    Or OR3(a[3], b[3], out[3]);
+    Or OR4(a[4], b[4], out[4]);
+    Or OR5(a[5], b[5], out[5]);
+    Or OR6(a[6], b[6], out[6]);
+    Or OR7(a[7], b[7], out[7]);
+    Or OR8(a[8], b[8], out[8]);
+    Or OR9(a[9], b[9], out[9]);
+    Or OR10(a[10], b[10], out[10]);
+    Or OR11(a[11], b[11], out[11]);
+    Or OR12(a[12], b[12], out[12]);
+    Or OR13(a[13], b[13], out[13]);
+    Or OR14(a[14], b[14], out[14]);
+    Or OR15(a[15], b[15], out[15]);
 endmodule
diff --git a/01_Boolean_Logic/Or8Way.v b/01_Boolean_Logic/Or8Way.v
index 2ad682b..d693005 100644
--- a/01_Boolean_Logic/Or8Way.v
+++ b/01_Boolean_Logic/Or8Way.v
@@ -5,10 +5,24 @@
 
 `default_nettype none
 module Or8Way(
-	input [7:0] in,
-	output out
+    input [7:0] in,
+    output out
 );
 
-	// Put your code here:
+    // Put your code here:
+    wire outA;
+    wire outB;
+    wire outC;
+    wire outD;
+    wire outE;
+    wire outF;
+
+    Or OR0(in[0], in[1], outA);
+    Or OR2(in[2], outA, outB);
+    Or OR3(in[3], outB, outC);
+    Or OR4(in[4], outC, outD);
+    Or OR5(in[5], outD, outE);
+    Or OR6(in[6], outE, outF);
+    Or OR7(in[7], outF, out);
 
 endmodule
diff --git a/01_Boolean_Logic/Xor.v b/01_Boolean_Logic/Xor.v
index 3c4789f..c8f324d 100644
--- a/01_Boolean_Logic/Xor.v
+++ b/01_Boolean_Logic/Xor.v
@@ -5,11 +5,21 @@
 
 `default_nettype none
 module Xor(
-	input a,
-	input b,
-	output out
+    input a,
+    input b,
+    output out
 );
 
-	// Put your code here:
+    // Put your code here:
+    wire nota;
+    wire notb;
+    Not NOT1(a, nota);
+    Not NOT2(b, notb);
 
+    wire w1;
+    wire w2;
+    And AND1(a, notb, w1);
+    And AND2(nota, b, w2);
+
+    Or OR(w1, w2, out);
 endmodule
diff --git a/02_Boolean_Arithmetic/ALU.v b/02_Boolean_Arithmetic/ALU.v
index 844ae44..9428bbc 100644
--- a/02_Boolean_Arithmetic/ALU.v
+++ b/02_Boolean_Arithmetic/ALU.v
@@ -2,7 +2,7 @@
  * The ALU (Arithmetic Logic Unit).
  * Computes one of the following functions:
  * x+y, x-y, y-x, 0, 1, -1, x, y, -x, -y, !x, !y,
- * x+1, y+1, x-1, y-1, x&y, x|y on two 16-bit inputs, 
+ * x+1, y+1, x-1, y-1, x&y, x|y on two 16-bit inputs,
  * according to 6 input bits denoted zx,nx,zy,ny,f,no.
  * In addition, the ALU computes two 1-bit outputs:
  * if the ALU output == 0, zr is set to 1; otherwise zr is set to 0;
@@ -23,19 +23,78 @@
 
 `default_nettype none
 module ALU(
-	input [15:0] x,		// input x (16 bit)
-	input [15:0] y,		// input y (16 bit)
-    input zx, 				// zero the x input?
-    input nx, 				// negate the x input?
-    input zy, 				// zero the y input?
-    input ny, 				// negate the y input?
-    input f,  				// compute out = x + y (if 1) or x & y (if 0)
-    input no, 				// negate the out output?
-    output [15:0] out, 			// 16-bit output
-    output zr, 				// 1 if (out == 0), 0 otherwise
-    output ng 				// 1 if (out < 0),  0 otherwise
+    input [15:0] x,     // input x (16 bit)
+    input [15:0] y,     // input y (16 bit)
+    input zx,               // zero the x input?
+    input nx,               // negate the x input?
+    input zy,               // zero the y input?
+    input ny,               // negate the y input?
+    input f,                // compute out = x + y (if 1) or x & y (if 0)
+    input no,               // negate the out output?
+    output [15:0] out,      // 16-bit output
+    output zr,              // 1 if (out == 0), 0 otherwise
+    output ng               // 1 if (out < 0),  0 otherwise
 );
 
-	// Put your code here:
+    // Put your code here:
+    wire [15:0] xa;
+    wire [15:0] xb;
+    wire [15:0] xc;
+    wire [15:0] ya;
+    wire [15:0] yb;
+    wire [15:0] yc;
+    wire [15:0] xandy;
+    wire [15:0] xplusy;
+    wire [15:0] xf;
+    wire [15:0] xn;
+    wire [7:0] zri;
+    wire [7:0] zrj;
+    wire ngr;
+    wire zrm;
+    wire zrn;
+    wire zro;
+    wire tt;
+    wire ff;
+
+    // Mux16(a=x, b=false, sel=zx, out=xa);
+    // Not16(in=xa, out=xb);
+    // Mux16(a=xa, b=xb, sel=nx, out=xc);
+    Mux16 MUXX1(x, 16'b0, zx, xa);
+    Not16 NOTX1(xa, xb);
+    Mux16 MUXX2(xa, xb, nx, xc);
+
+    // Mux16(a=y, b=false, sel=zy, out=ya);
+    // Not16(in=ya, out=yb);
+    // Mux16(a=ya, b=yb, sel=ny, out=yc);
+    Mux16 MUXY1(y, 16'b0, zy, ya);
+    Not16 NOTY1(ya, yb);
+    Mux16 MUXY2(ya, yb, ny, yc);
+
+    // And16(a=xc, b=yc, out=xandy);
+    // Add16(a=xc, b=yc, out=xplusy);
+    // Mux16(a=xandy, b=xplusy, sel=f, out=xf);
+    And16 ANDZ1(xc, yc, xandy);
+    Add16 ADDZ1(xc, yc, xplusy);
+    Mux16 MUXZ1(xandy, xplusy, f, xf);
+
+    // Not16(in=xf, out=xn);
+    // Mux16(a=xf, b=xn, sel=no, out=out, out[15]=ngr, out[0..7]=zri, out[8..15]=zrj);
+    Not16 NOTF1(xf, xn);
+    Mux16 MUXF1(xf, xn, no, out);
+
+    assign ngr = out[15];
+    assign zri[7:0] = out[7:0];
+    assign zrj[7:0] = out[15:8];
+
+    // Or8Way(in=zri, out=zrm);
+    // Or8Way(in=zrj, out=zrn);
+    Or8Way OR8F1(zri, zrm);
+    Or8Way OR8F2(zrj, zrn);
+    Or ORF1(zrm, zrn, zro);
+    Not NOTF2(zro, zr);
+    Mux MUXF2(1'b0, 1'b1, ngr,  ng);
+    // Or(a=zrm, b=zrn, out=zro);
+    // Not(in=zro, out=zr);
+    // Mux(a=false, b=true, sel=ngr, out=ng);
 
 endmodule
diff --git a/02_Boolean_Arithmetic/Add16.v b/02_Boolean_Arithmetic/Add16.v
index afa4243..2826497 100644
--- a/02_Boolean_Arithmetic/Add16.v
+++ b/02_Boolean_Arithmetic/Add16.v
@@ -6,11 +6,43 @@
 
 `default_nettype none
 module Add16(
-	input [15:0] a,
-	input [15:0] b,
-	output [15:0] out
+    input [15:0] a,
+    input [15:0] b,
+    output [15:0] out
 );
 
-	// Put your code here:
+    // Put your code here:
+    wire carry0;
+    wire carry1;
+    wire carry2;
+    wire carry3;
+    wire carry4;
+    wire carry5;
+    wire carry6;
+    wire carry7;
+    wire carry8;
+    wire carry9;
+    wire carry10;
+    wire carry11;
+    wire carry12;
+    wire carry13;
+    wire carry14;
+    wire carry15;
 
+    HalfAdder HA0(a[0], b[0], out[0], carry0);
+    FullAdder FA0(a[1], b[1], carry0, out[1], carry1);
+    FullAdder FA1(a[2], b[2], carry1, out[2], carry2);
+    FullAdder FA2(a[3], b[3], carry2, out[3], carry3);
+    FullAdder FA3(a[4], b[4], carry3, out[4], carry4);
+    FullAdder FA4(a[5], b[5], carry4, out[5], carry5);
+    FullAdder FA5(a[6], b[6], carry5, out[6], carry6);
+    FullAdder FA6(a[7], b[7], carry6, out[7], carry7);
+    FullAdder FA7(a[8], b[8], carry7, out[8], carry8);
+    FullAdder FA8(a[9], b[9], carry8, out[9], carry9);
+    FullAdder FA9(a[10], b[10], carry9, out[10], carry10);
+    FullAdder FA10(a[11], b[11], carry10, out[11], carry11);
+    FullAdder FA11(a[12], b[12], carry11, out[12], carry12);
+    FullAdder FA12(a[13], b[13], carry12, out[13], carry13);
+    FullAdder FA13(a[14], b[14], carry13, out[14], carry14);
+    FullAdder FA14(a[15], b[15], carry14, out[15], carry15);
 endmodule
diff --git a/02_Boolean_Arithmetic/FullAdder.v b/02_Boolean_Arithmetic/FullAdder.v
index 3c91dff..a9fa1bb 100644
--- a/02_Boolean_Arithmetic/FullAdder.v
+++ b/02_Boolean_Arithmetic/FullAdder.v
@@ -4,13 +4,19 @@
 
 `default_nettype none
 module FullAdder(
-	input a,		//1-bit input
-	input b,		//1-bit input
-	input c,		//1-bit input
-	output sum,		//Right bit of a + b + c
-	output carry	//Left bit of a + b + c
+    input a,        //1-bit input
+    input b,        //1-bit input
+    input c,        //1-bit input
+    output sum,     //Right bit of a + b + c
+    output carry    //Left bit of a + b + c
 );
 
-	// Put your code here:
+    // Put your code here:
+    wire sumi;
+    wire carryi;
+    wire carryj;
 
+    HalfAdder HA1(a, b, sumi, carryi);
+    HalfAdder HA2(c, sumi, sum, carryj);
+    Or OR(carryi, carryj, carry);
 endmodule
diff --git a/02_Boolean_Arithmetic/HalfAdder.v b/02_Boolean_Arithmetic/HalfAdder.v
index c7e3d47..79fc54e 100644
--- a/02_Boolean_Arithmetic/HalfAdder.v
+++ b/02_Boolean_Arithmetic/HalfAdder.v
@@ -4,12 +4,13 @@
 
 `default_nettype none
 module HalfAdder(
-	input a,		//1-bit input
-	input b,		//1-bit inpur
-	output sum,	//Right bit of a + b
-	output carry	//Lef bit of a + b
+    input a,        //1-bit input
+    input b,        //1-bit inpur
+    output sum,     //Right bit of a + b
+    output carry    //Lef bit of a + b
 );
 
-	// Put your code here:
-
+    // Put your code here:
+    Xor XOR(a, b, sum);
+    And AND(a, b, carry);
 endmodule
diff --git a/02_Boolean_Arithmetic/Inc16.v b/02_Boolean_Arithmetic/Inc16.v
index ea944b5..d51221d 100644
--- a/02_Boolean_Arithmetic/Inc16.v
+++ b/02_Boolean_Arithmetic/Inc16.v
@@ -5,10 +5,14 @@
 
 `default_nettype none
 module Inc16(
-	input [15:0] in,
-	output [15:0] out
+    input [15:0] in,
+    output [15:0] out
 );
 
-	// Put your code here:
-
+    // Put your code here:
+    wire [15:0] incr;
+    assign incr[15:0] = 16'b1;
+    Add16 ADD(in, incr, out);
+    // or just:
+    //assign out = in + 1;
 endmodule
diff --git a/03_Sequential_Logic/Bit.v b/03_Sequential_Logic/Bit.v
index 17befc5..ffa0482 100644
--- a/03_Sequential_Logic/Bit.v
+++ b/03_Sequential_Logic/Bit.v
@@ -6,12 +6,16 @@
 
 `default_nettype none
 module Bit(
-	input clk,
-	input in,
-	input load,
-	output out
+    input clk,
+    input in,
+    input load,
+    output out
 );
 
-	// Put your code here:
-
+    // Put your code here:
+    wire muxout;
+    // Mux(a=dffout, b=in, sel=load, out=muxout);
+    // DFF(in=muxout, out=out, out=dffout);
+    Mux MUX(out, in, load, muxout);
+    DFF DFF(clk, muxout, out);
 endmodule
diff --git a/03_Sequential_Logic/BitShift8L.v b/03_Sequential_Logic/BitShift8L.v
index c79d81d..4f2d23f 100644
--- a/03_Sequential_Logic/BitShift8L.v
+++ b/03_Sequential_Logic/BitShift8L.v
@@ -7,14 +7,56 @@
 
 `default_nettype none
 module BitShift8L(
-	input clk,
-	input [7:0] in,
-	input inLSB,
-	input load,
-	input shift,
-	output [7:0] out
+input clk,
+input [7:0] in,
+input inLSB,
+input load,
+input shift,
+output [7:0] out
 );
 
-	// Put your code here:
+    // Put your code here:
+    reg [7:0] reg8;
 
+    always @(posedge clk) begin
+        if (load == 1) begin
+            reg8[7:0] = in[7:0];
+        end
+        else if (shift == 1 ) begin
+            reg8[7:1] = reg8[6:0];
+            reg8[0] = inLSB;
+        end
+    end
+
+    assign out = reg8;
+
+    // wire [7:0] out_l;
+    // wire [7:0] out_s;
+
+    // Mux MUXLA(out[0], in[0], load, out_l[0]);
+    // Mux MUXLB(out[1], in[1], load, out_l[1]);
+    // Mux MUXLC(out[2], in[2], load, out_l[2]);
+    // Mux MUXLD(out[3], in[3], load, out_l[3]);
+    // Mux MUXLE(out[4], in[4], load, out_l[4]);
+    // Mux MUXLF(out[5], in[5], load, out_l[5]);
+    // Mux MUXLG(out[6], in[6], load, out_l[6]);
+    // Mux MUXLH(out[7], in[7], load, out_l[7]);
+
+    // Mux MUXSA(out_l[0], inLSB,  shift, out_s[0]);
+    // Mux MUXSB(out_l[1], out[0], shift, out_s[1]);
+    // Mux MUXSC(out_l[2], out[1], shift, out_s[2]);
+    // Mux MUXSD(out_l[3], out[2], shift, out_s[3]);
+    // Mux MUXSE(out_l[4], out[3], shift, out_s[4]);
+    // Mux MUXSF(out_l[5], out[4], shift, out_s[5]);
+    // Mux MUXSG(out_l[6], out[5], shift, out_s[6]);
+    // Mux MUXSH(out_l[7], out[6], shift, out_s[7]);
+
+    // Bit BITA(clk, out_s[0], 1'b1, out[0]);
+    // Bit BITB(clk, out_s[1], 1'b1, out[1]);
+    // Bit BITC(clk, out_s[2], 1'b1, out[2]);
+    // Bit BITD(clk, out_s[3], 1'b1, out[3]);
+    // Bit BITE(clk, out_s[4], 1'b1, out[4]);
+    // Bit BITF(clk, out_s[5], 1'b1, out[5]);
+    // Bit BITG(clk, out_s[6], 1'b1, out[6]);
+    // Bit BITH(clk, out_s[7], 1'b1, out[7]);
 endmodule
diff --git a/03_Sequential_Logic/BitShift9R.v b/03_Sequential_Logic/BitShift9R.v
index c8bda6b..adeb977 100644
--- a/03_Sequential_Logic/BitShift9R.v
+++ b/03_Sequential_Logic/BitShift9R.v
@@ -7,14 +7,26 @@
 
 `default_nettype none
 module BitShift9R(
-	input clk,
-	input [8:0] in,
-	input inMSB,
-	input load,
-	input shift,
-	output [8:0] out
+    input clk,
+    input [8:0] in,
+    input inMSB,
+    input load,
+    input shift,
+    output [8:0] out
 );
 
-	// Put your code here:
+    // Put your code here:
+    reg [8:0] reg9;
 
+    always @(posedge clk) begin
+        if (load == 1) begin
+            reg9[7:0] = in[7:0];
+        end
+        else if (shift == 1 ) begin
+            reg9[7:0] = reg9[8:1];
+            reg9[8] = inMSB;
+        end
+    end
+
+    assign out = reg9;
 endmodule
diff --git a/03_Sequential_Logic/DFF.v b/03_Sequential_Logic/DFF.v
index d2f6a6b..925b0b6 100644
--- a/03_Sequential_Logic/DFF.v
+++ b/03_Sequential_Logic/DFF.v
@@ -5,16 +5,16 @@
 
 `default_nettype none
 module DFF(
-		input clk,
-		input in,
-		output out
+        input clk,
+        input in,
+        output reg out
 );
 
-	// No need to implement this chip
-	// This chip is implemented in verilog using reg-variables
-	reg out;
-	always @(posedge clk)
-		if (in) out <= 1'b1;
-		else out <= 1'b0;
+    // No need to implement this chip
+    // This chip is implemented in verilog using reg-variables
+    // reg out;
+    always @(posedge clk)
+        if (in) out <= 1'b1;
+        else out <= 1'b0;
 
 endmodule
diff --git a/03_Sequential_Logic/PC.v b/03_Sequential_Logic/PC.v
index 34a7d54..60bf5bd 100644
--- a/03_Sequential_Logic/PC.v
+++ b/03_Sequential_Logic/PC.v
@@ -8,14 +8,24 @@
 
 `default_nettype none
 module PC(
-	input clk,
-	input [15:0] in,
-	input load,
-	input inc,
-	input reset,
-	output [15:0] out
-);	
-	
-	// Put your code here:
+    input clk,
+    input [15:0] in,
+    input load,
+    input inc,
+    input reset,
+    output [15:0] out
+);
 
+    // Put your code here:
+    // wire [15:0] plusone;
+    // wire [15:0] incstep;
+    // wire [15:0] loadstep;
+    // wire [15:0] resetstep;
+    // Inc16 INC16(out, plusone);
+    // Mux16 MUX16A(out, plusone, inc, incstep);
+    // Mux16 MUX16B(incstep, in, load, loadstep);
+    // Mux16 MUX16C(loadstep, 16'b0, reset, resetstep);
+    wire [15:0] select;
+    assign select = reset? 0 : (load? in : (inc? out+1 : out));
+    Register REG(clk, select, 1'b1, out);
 endmodule
diff --git a/03_Sequential_Logic/RAM3840.v b/03_Sequential_Logic/RAM3840.v
index 9eb4f4f..6598e04 100644
--- a/03_Sequential_Logic/RAM3840.v
+++ b/03_Sequential_Logic/RAM3840.v
@@ -6,13 +6,43 @@
 
 `default_nettype none
 module RAM3840(
-	input clk,
-	input [11:0] address,
-	input [15:0] in,
-	input load,
-	output [15:0] out
+    input clk,
+    input [11:0] address,
+    input [15:0] in,
+    input load,
+    output [15:0] out
 );
-	
-	// Put your code here:
+
+    // Put your code here:
+    wire load0;
+    wire load1;
+    wire load2;
+    wire load3;
+    wire load4;
+    wire load5;
+    wire load6;
+    wire load7;
+    wire [15:0] ram0;
+    wire [15:0] ram1;
+    wire [15:0] ram2;
+    wire [15:0] ram3;
+    wire [15:0] ram4;
+    wire [15:0] ram5;
+    wire [15:0] ram6;
+    wire [15:0] ram7;
+
+    DMux8Way DMUX(load, address[11:9],
+        load0, load1, load2, load3, load4, load5, load6, load7);
+    RAM512 RAM0(clk, address[8:0], in, load0, ram0);
+    RAM512 RAM1(clk, address[8:0], in, load1, ram1);
+    RAM512 RAM2(clk, address[8:0], in, load2, ram2);
+    RAM512 RAM3(clk, address[8:0], in, load3, ram3);
+    RAM512 RAM4(clk, address[8:0], in, load4, ram4);
+    RAM512 RAM5(clk, address[8:0], in, load5, ram5);
+    RAM512 RAM6(clk, address[8:0], in, load6, ram6);
+    RAM256 RAM7(clk, address[7:0], in, load7, ram7);
+
+    Mux8Way16 MUX(ram0, ram1, ram2, ram3, ram4, ram5, ram6, ram7,
+        address[11:9], out);
 
 endmodule
diff --git a/03_Sequential_Logic/RAM512.v b/03_Sequential_Logic/RAM512.v
index 6e2eacb..0268091 100644
--- a/03_Sequential_Logic/RAM512.v
+++ b/03_Sequential_Logic/RAM512.v
@@ -6,13 +6,21 @@
 
 `default_nettype none
 module RAM512(
-	input clk,
-	input [8:0] address,
-	input [15:0] in,
-	input load,
-	output [15:0] out
+    input clk,
+    input [8:0] address,
+    input [15:0] in,
+    input load,
+    output [15:0] out
 );
-	
-	// Put your code here:
+
+    // Put your code here:
+    wire load0;
+    wire load1;
+    wire [15:0] ram0;
+    wire [15:0] ram1;
+    DMux DMUX(load, address[8], load0, load1);
+    RAM256 RAM0(clk, address[7:0], in, load0, ram0);
+    RAM256 RAM1(clk, address[7:0], in, load1, ram1);
+    Mux16 MUX(ram0, ram1, address[8], out);
 
 endmodule
diff --git a/03_Sequential_Logic/Register.v b/03_Sequential_Logic/Register.v
index 384dc9b..47308f1 100644
--- a/03_Sequential_Logic/Register.v
+++ b/03_Sequential_Logic/Register.v
@@ -7,12 +7,27 @@
 `default_nettype none
 
 module Register(
-	input clk,
-	input [15:0] in,
-	input load,
-	output [15:0] out
+    input clk,
+    input [15:0] in,
+    input load,
+    output [15:0] out
 );
 
-	// Put your code here:
-
+    // Put your code here:
+    Bit BITA(clk, in[0], load, out[0]);
+    Bit BITB(clk, in[1], load, out[1]);
+    Bit BITC(clk, in[2], load, out[2]);
+    Bit BITD(clk, in[3], load, out[3]);
+    Bit BITE(clk, in[4], load, out[4]);
+    Bit BITF(clk, in[5], load, out[5]);
+    Bit BITG(clk, in[6], load, out[6]);
+    Bit BITH(clk, in[7], load, out[7]);
+    Bit BITI(clk, in[8], load, out[8]);
+    Bit BITJ(clk, in[9], load, out[9]);
+    Bit BITK(clk, in[10], load, out[10]);
+    Bit BITL(clk, in[11], load, out[11]);
+    Bit BITM(clk, in[12], load, out[12]);
+    Bit BITN(clk, in[13], load, out[13]);
+    Bit BITO(clk, in[14], load, out[14]);
+    Bit BITP(clk, in[15], load, out[15]);
 endmodule
diff --git a/04_Machine_Language/leds.asm b/04_Machine_Language/leds.asm
index 8c55125..2766dc2 100644
--- a/04_Machine_Language/leds.asm
+++ b/04_Machine_Language/leds.asm
@@ -3,3 +3,10 @@
 // read the button state and output to led
 
 // Put your code here:
+
+@BUT
+D=M
+@LED
+M=!D
+@0
+0;JMP
diff --git a/04_Machine_Language/mult.asm b/04_Machine_Language/mult.asm
index 0a74dad..a90f454 100644
--- a/04_Machine_Language/mult.asm
+++ b/04_Machine_Language/mult.asm
@@ -31,8 +31,41 @@ M=1
 // Put your code here:
 
 
+@R2
+M=0
+@DEBUG2
+M=0
+@itr
+M=0
 
+// loop declaration
+// D = R1 - itr
+// if 0 jump to @STOP
+// else continue
+    (LOOP)
+@itr
+D=M
+@R0
+D=M-D
+@DEBUG0
+M=D
+@END
+D;JEQ
 
+// R2 = R0 + R2
+// itr = itr + 1
+@R1
+D=M
+@R2
+DM=D+M
+@DEBUG2
+M=D
+@itr
+M=M+1
+
+// back to loop declaration
+@LOOP
+0;JMP
 
 // till here!
 
diff --git a/05_Computer_Architecture/CPU.v b/05_Computer_Architecture/CPU.v
index 23f4bdb..eafbd75 100644
--- a/05_Computer_Architecture/CPU.v
+++ b/05_Computer_Architecture/CPU.v
@@ -1,40 +1,106 @@
 /**
  * The Hack CPU (Central Processing unit), consisting of an ALU,
  * two registers named A and D, and a program counter named PC.
- * The CPU is designed to fetch and execute instructions written in 
+ * The CPU is designed to fetch and execute instructions written in
  * the Hack machine language. In particular, functions as follows:
- * Executes the inputted instruction according to the Hack machine 
+ * Executes the inputted instruction according to the Hack machine
  * language specification. The D and A in the language specification
  * refer to CPU-resident registers, while M refers to the external
- * memory location addressed by A, i.e. to Memory[A]. The inM input 
- * holds the value of this location. If the current instruction needs 
- * to write a value to M, the value is placed in outM, the address 
- * of the target location is placed in the addressM output, and the 
- * writeM control bit is asserted. (When writeM==0, any value may 
- * appear in outM). The outM and writeM outputs are combinational: 
- * they are affected instantaneously by the execution of the current 
- * instruction. The addressM and pc outputs are clocked: although they 
- * are affected by the execution of the current instruction, they commit 
- * to their new values only in the next time step. If reset==1 then the 
- * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather 
- * than to the address resulting from executing the current instruction. 
+ * memory location addressed by A, i.e. to Memory[A]. The inM input
+ * holds the value of this location. If the current instruction needs
+ * to write a value to M, the value is placed in outM, the address
+ * of the target location is placed in the addressM output, and the
+ * writeM control bit is asserted. (When writeM==0, any value may
+ * appear in outM). The outM and writeM outputs are combinational:
+ * they are affected instantaneously by the execution of the current
+ * instruction. The addressM and pc outputs are clocked: although they
+ * are affected by the execution of the current instruction, they commit
+ * to their new values only in the next time step. If reset==1 then the
+ * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather
+ * than to the address resulting from executing the current instruction.
  */
 
 `default_nettype none
 module CPU(
-		input clk,
-    	input [15:0] inM,         	// M value input  (M = contents of RAM[A])
-    	input [15:0] instruction, 	// Instruction for execution
-		input reset,				// Signals whether to re-start the current
-                         			// program (reset==1) or continue executing
-                         			// the current program (reset==0).
+        input clk,
+        input [15:0] inM,            // M value input  (M = contents of RAM[A])
+        input [15:0] instruction,    // Instruction for execution
+        input reset,                 // Signals whether to re-start the current
+                                     // program (reset==1) or continue executing
+                                     // the current program (reset==0).
 
-    	output [15:0] outM,			// M value output
-    	output writeM,				// Write to M? 
-    	output [15:0] addressM,		// Address in data memory (of M) to read
-    	output [15:0] pc			// address of next instruction
+        output [15:0] outM,         // M value output
+        output writeM,              // Write to M?
+        output [15:0] addressM,     // Address in data memory (of M) to read
+        output [15:0] pc            // address of next instruction
 );
 
-	// Put your code here:
+    // Put your code here:
+    wire loadA;
+    wire loadD;
+    wire is_A;
+    wire is_C;
+    wire zr;
+    wire ng;
+    wire inc;
+    wire load;
+    wire jump;
+    wire [15:0] toA;
+    wire [15:0] toD;
+    wire [15:0] toPC;
+    wire [15:0] fromA;
+    wire [15:0] fromD;
+    wire [15:0] fromPC;
+    wire [15:0] fromAorM;
+    wire [15:0] fromALU;
+
+    reg [15:0] tempM;
+    reg [15:0] tempPC;
+
+
+    assign is_C = instruction[15] & instruction[14] & instruction[13];
+    assign is_A = ~is_C;
+
+
+    assign loadD = is_C & instruction[4];
+    assign loadA = (is_C & instruction[5]) || is_A;
+
+    assign fromAorM = instruction[12] ? inM : fromA;
+    assign toA = is_A ? instruction : outM;
+
+
+    // jump if j1 bit set and ng bit set
+    // jump if j2 bit set and zr bit set
+    // jump if j3 bit set and zr, ng bit not set
+    assign jump = is_C
+                & ((instruction[2] & ng)
+                || (instruction[1] & zr)
+                || (instruction[0] & ~(zr | ng)));
+    assign inc = ~jump;
+
+    assign outM = fromALU;
+
+    //assign toPC = jump? fromA : pc;
+
+    //xxxx xxxx xxxx xxxx
+    Register RegA(clk, toA, loadA, fromA);
+    Register RegD(clk, fromALU, loadD, fromD);
+    PC PC(clk, fromA, jump, inc, reset, pc);
+    ALU ALU(
+        fromD,
+        fromAorM,
+        instruction[11],
+        instruction[10],
+        instruction[9],
+        instruction[8],
+        instruction[7],
+        instruction[6],
+        fromALU,
+        zr,
+        ng
+    );
+
+    assign addressM = fromA;
+    assign writeM = is_C & instruction[3];
 
 endmodule
diff --git a/05_Computer_Architecture/Clock25_Reset20.v b/05_Computer_Architecture/Clock25_Reset20.v
index ad8a746..16f1378 100644
--- a/05_Computer_Architecture/Clock25_Reset20.v
+++ b/05_Computer_Architecture/Clock25_Reset20.v
@@ -4,12 +4,24 @@
 * a reset signal of approx. 20us length
 */
 `default_nettype none
-module Clock25_Reset20( 
-    input CLK,			// external clock 100 MHz	
-	output clk,			// internal clock 25 Mhz
-	output reset 		// reset signal approx. 20us
+module Clock25_Reset20(
+    input CLK,              // external clock 100 MHz
+    output reg clk,         // internal clock 25 Mhz
+    output reg reset        // reset signal approx. 20us
 );
 
-	// Put your code here:
+    // Put your code here:
+    reg boot=1;
+    reg [3:0]  ccount=0;
+    reg [12:0] rcount=0;
 
+    always @(posedge CLK) begin
+        if (boot == 1) begin
+            boot <= (rcount == 4095) ? 0 : 1;
+            rcount <= (rcount == 4095) ? 0 : rcount + 1;
+            reset <= (rcount >= 2048) ? 0 : 1;
+        end
+        ccount <= (ccount == 3) ? 0 : ccount + 1;
+        clk <= (ccount >= 2) ? 1 : 0;
+    end
 endmodule
diff --git a/05_Computer_Architecture/HACK.v b/05_Computer_Architecture/HACK.v
index dfae7f6..8034513 100644
--- a/05_Computer_Architecture/HACK.v
+++ b/05_Computer_Architecture/HACK.v
@@ -8,12 +8,89 @@
  */
 
 `default_nettype none
-module HACK( 
-    input CLK,			// external clock 100 MHz	
-	input [1:0] BUT,	// user button (0 if pressed, 1 if released)
-	output [1:0] LED	// leds (0 off, 1 on)
+module HACK(
+    input CLK,          // external clock 100 MHz
+    input [1:0] BUT,    // user button (0 if pressed, 1 if released)
+    output [1:0] LED    // leds (0 off, 1 on)
 );
 
-	// Put your code here:
+
+    wire loadRAM;
+    wire loadIO0;
+    wire loadIO1;
+    wire loadIO2;
+    wire loadIO3;
+    wire loadIO4;
+    wire loadIO5;
+    wire loadIO6;
+    wire loadIO7;
+    wire loadIO8;
+    wire loadIO9;
+    wire loadIOA;
+    wire loadIOB;
+    wire loadIOC;
+    wire loadIOD;
+    wire loadIOE;
+    wire loadIOF;
+    wire [15:0] inRAM;
+    wire [15:0] inIO0;
+    wire [15:0] inIO1;
+    wire [15:0] inIO2=0;
+    wire [15:0] inIO3=0;
+    wire [15:0] inIO4=0;
+    wire [15:0] inIO5=0;
+    wire [15:0] inIO6=0;
+    wire [15:0] inIO7=0;
+    wire [15:0] inIO8=0;
+    wire [15:0] inIO9=0;
+    wire [15:0] inIOA=0;
+    wire [15:0] inIOB;
+    wire [15:0] inIOC;
+    wire [15:0] inIOD;
+    wire [15:0] inIOE;
+    wire [15:0] inIOF;
+
+    wire writeM;
+    wire [15:0] inM;
+    wire [15:0] instruction;
+    wire [15:0] outM;
+    wire [15:0] addressM;
+    wire [15:0] pc;
+
+    wire clk, reset;
+    wire [15:0] outDEBUG0;
+    wire [15:0] outDEBUG1;
+    wire [15:0] outDEBUG2;
+    wire loadDEBUG0;
+    wire loadDEBUG1;
+    wire loadDEBUG2;
+    // Put your code here:
+    assign LED[1:0] = inIO0[1:0];
+    assign outDEBUG0 = inIOB;
+    assign outDEBUG1 = inIOC;
+    assign outDEBUG2 = inIOD;
+    assign loadDEBUG0 = loadIOB;
+    assign loadDEBUG1 = loadIOC;
+    assign loadDEBUG2 = loadIOD;
+    Clock25_Reset20 CLKR(CLK, clk, reset);
+    CPU CPU(clk, inM, instruction, reset, outM, writeM, addressM, pc);
+
+    Memory Memory(addressM, writeM, inM, loadRAM,
+        loadIO0, loadIO1, loadIO2, loadIO3, loadIO4, loadIO5, loadIO6, loadIO7,
+        loadIO8, loadIO9, loadIOA, loadIOB, loadIOC, loadIOD, loadIOE, loadIOF,
+        inRAM, inIO0, inIO1, inIO2, inIO3, inIO4, inIO5, inIO6, inIO7,
+        inIO8, inIO9, inIOA, inIOB, inIOC, inIOD, inIOE, inIOF);
+
+    ROM ROM(pc, instruction);
+    RAM3840 RAM(clk, addressM[11:0], outM, loadRAM, inRAM);
+
+    Register LED12(clk, outM, loadIO0, inIO0);
+    Register BUT12(clk, {14'b0, BUT[1:0]}, 1'b1, inIO1);
+
+    Register DEBUG0(clk, outM, loadIOB, inIOB);
+    Register DEBUG1(clk, outM, loadIOC, inIOC);
+    Register DEBUG2(clk, outM, loadIOD, inIOD);
+    Register DEBUG3(clk, outM, loadIOE, inIOE);
+    Register DEBUG4(clk, outM, loadIOF, inIOF);
 
 endmodule
diff --git a/05_Computer_Architecture/Memory.v b/05_Computer_Architecture/Memory.v
index 59207da..a362474 100644
--- a/05_Computer_Architecture/Memory.v
+++ b/05_Computer_Architecture/Memory.v
@@ -1,12 +1,12 @@
 /**
  * The complete address space of the Hack computer's memory,
- * including RAM and memory-mapped I/O. 
+ * including RAM and memory-mapped I/O.
  * The chip facilitates read and write operations, as follows:
  *     Read:  out(t) = Memory[address(t)](t)
  *     Write: if load(t-1) then Memory[address(t-1)](t) = in(t-1)
- * In words: the chip always outputs the value stored at the memory 
- * location specified by address. If load==1, the in value is loaded 
- * into the memory location specified by address. This value becomes 
+ * In words: the chip always outputs the value stored at the memory
+ * location specified by address. If load==1, the in value is loaded
+ * into the memory location specified by address. This value becomes
  * available through the out output from the next time step onward.
  * Address space rules:
  * RAM 0x0000 - 0x0EFF (3840 words)
@@ -16,45 +16,80 @@
 
 `default_nettype none
 module Memory(
-	input [15:0] address,
-	input load,
-	output [15:0] out,
-	output loadRAM,
-	output loadIO0,
-	output loadIO1,
-	output loadIO2,
-	output loadIO3,
-	output loadIO4,
-	output loadIO5,
-	output loadIO6,
-	output loadIO7,
-	output loadIO8,
-	output loadIO9,
-	output loadIOA,
-	output loadIOB,
-	output loadIOC,
-	output loadIOD,
-	output loadIOE,
-	output loadIOF,
-	input [15:0] inRAM,
-	input [15:0] inIO0,
-	input [15:0] inIO1,
-	input [15:0] inIO2,
-	input [15:0] inIO3,
-	input [15:0] inIO4,
-	input [15:0] inIO5,
-	input [15:0] inIO6,
-	input [15:0] inIO7,
-	input [15:0] inIO8,
-	input [15:0] inIO9,
-	input [15:0] inIOA,
-	input [15:0] inIOB,
-	input [15:0] inIOC,
-	input [15:0] inIOD,
-	input [15:0] inIOE,
-	input [15:0] inIOF
+    input [15:0] address,
+    input load,
+    output [15:0] out,
+    output loadRAM,
+    output loadIO0,
+    output loadIO1,
+    output loadIO2,
+    output loadIO3,
+    output loadIO4,
+    output loadIO5,
+    output loadIO6,
+    output loadIO7,
+    output loadIO8,
+    output loadIO9,
+    output loadIOA,
+    output loadIOB,
+    output loadIOC,
+    output loadIOD,
+    output loadIOE,
+    output loadIOF,
+    input [15:0] inRAM,
+    input [15:0] inIO0,
+    input [15:0] inIO1,
+    input [15:0] inIO2,
+    input [15:0] inIO3,
+    input [15:0] inIO4,
+    input [15:0] inIO5,
+    input [15:0] inIO6,
+    input [15:0] inIO7,
+    input [15:0] inIO8,
+    input [15:0] inIO9,
+    input [15:0] inIOA,
+    input [15:0] inIOB,
+    input [15:0] inIOC,
+    input [15:0] inIOD,
+    input [15:0] inIOE,
+    input [15:0] inIOF
 );
 
-	// Put your code here:
+    // Put your code here:
+    wire selA;
+    wire selB;
+    wire loadA;
+    wire loadB;
+
+    wire [15:0] outA;
+    wire [15:0] outB;
+    wire [15:0] outAB;
+
+    DMux DMUX(address[12], address[3], selA, selB);
+    And ANDA(selA,load,loadA);
+    And ANDB(selB,load,loadB);
+    And ANDR(~address[12], load, loadRAM);
+
+    DMux8Way DMUXLOADA(loadA, address[2:0],
+        loadIO0, loadIO1, loadIO2, loadIO3,
+        loadIO4, loadIO5, loadIO6, loadIO7);
+
+    DMux8Way DMUXLOADB(loadB, address[2:0],
+        loadIO8, loadIO9, loadIOA, loadIOB,
+        loadIOC, loadIOD, loadIOE, loadIOF);
+
+    Mux8Way16 Mux8Way16A(
+        inIO0[15:0], inIO1[15:0], inIO2[15:0], inIO3[15:0],
+        inIO4[15:0], inIO5[15:0], inIO6[15:0], inIO7[15:0],
+        address[2:0], outA[15:0]
+    );
+    Mux8Way16 Mux8Way16B(
+        inIO8[15:0], inIO9[15:0], inIOA[15:0], inIOB[15:0],
+        inIOC[15:0], inIOD[15:0], inIOE[15:0], inIOF[15:0],
+        address[2:0], outB[15:0]
+    );
+
+    Mux16 MUX16AB(outA[15:0], outB[15:0], address[3], outAB[15:0]);
+    Mux16 MUX16ABR(inRAM[15:0], outAB[15:0], address[12], out[15:0]);
 
 endmodule