nand2/01_Boolean_Logic/DMux8Way.v

40 lines
866 B
Verilog

/**
* 8-way demultiplexor:
* {a, b, c, d, e, f, g, h} = {in, 0, 0, 0, 0, 0, 0, 0} if sel == 000
* {0, in, 0, 0, 0, 0, 0, 0} if sel == 001
* etc.
* {0, 0, 0, 0, 0, 0, 0, in} if sel == 111
*/
`default_nettype none
module DMux8Way(
input in,
input [2:0] sel,
output a,
output b,
output c,
output d,
output e,
output f,
output g,
output h
);
// Put your code here:
wire outi;
wire outj;
wire outw;
wire outx;
wire outy;
wire outz;
DMux DMUXA(in, sel[2], outi, outj);
DMux DMUXB(outi, sel[1], outw, outx);
DMux DMUXC(outj, sel[1], outy, outz);
DMux DMUXD(outw, sel[0], a, b);
DMux DMUXE(outx, sel[0], c, d);
DMux DMUXF(outy, sel[0], e, f);
DMux DMUXG(outz, sel[0], g, h);
endmodule