nand2/01_Boolean_Logic/Not16.v

30 lines
661 B
Verilog

/**
* 16-bit Not:
* for i=0..15: out[i] = not in[i]
*/
`default_nettype none
module Not16(
input [15:0] in,
output [15:0] out
);
// Put your code here:
Not NOT0(in[0], out[0]);
Not NOT1(in[1], out[1]);
Not NOT2(in[2], out[2]);
Not NOT3(in[3], out[3]);
Not NOT4(in[4], out[4]);
Not NOT5(in[5], out[5]);
Not NOT6(in[6], out[6]);
Not NOT7(in[7], out[7]);
Not NOT8(in[8], out[8]);
Not NOT9(in[9], out[9]);
Not NOT10(in[10], out[10]);
Not NOT11(in[11], out[11]);
Not NOT12(in[12], out[12]);
Not NOT13(in[13], out[13]);
Not NOT14(in[14], out[14]);
Not NOT15(in[15], out[15]);
endmodule