22 lines
317 B
Verilog
22 lines
317 B
Verilog
/**
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* Demultiplexor:
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* {a, b} = {in, 0} if sel == 0
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* {0, in} if sel == 1
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*/
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`default_nettype none
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module DMux(
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input in,
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input sel,
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output a,
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output b
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);
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// Put your code here:
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wire nsel;
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Not NOT1(sel, nsel);
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And AND1(in, sel, b);
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And AND2(in, nsel, a);
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endmodule
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