nand2/01_Boolean_Logic/Xor.v

26 lines
351 B
Verilog

/**
* Exclusive-or gate:
* out = not (a == b)
*/
`default_nettype none
module Xor(
input a,
input b,
output out
);
// Put your code here:
wire nota;
wire notb;
Not NOT1(a, nota);
Not NOT2(b, notb);
wire w1;
wire w2;
And AND1(a, notb, w1);
And AND2(nota, b, w2);
Or OR(w1, w2, out);
endmodule