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add project 1, 2, 3 HDLs

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Konarak
2021-12-05 09:07:22 +05:30
parent 8fe4e35950
commit bde2161900
28 changed files with 834 additions and 0 deletions
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projects/03/a/Bit.hdl Normal file
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// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/Bit.hdl
/**
* 1-bit register:
* If load[t] == 1 then out[t+1] = in[t]
* else out does not change (out[t+1] = out[t])
*/
CHIP Bit {
IN in, load;
OUT out;
PARTS:
// Put your code here:
Mux(a=dffout, b=in, sel=load, out=muxout);
DFF(in=muxout, out=out, out=dffout);
}

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// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/PC.hdl
/**
* A 16-bit counter with load and reset control bits.
* if (reset[t] == 1) out[t+1] = 0
* else if (load[t] == 1) out[t+1] = in[t]
* else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition)
* else out[t+1] = out[t]
*/
CHIP PC {
IN in[16], load, inc, reset;
OUT out[16];
PARTS:
// Put your code here:
Inc16(in=registerValue, out=incrementedValue);
Mux16(a=registerValue, b=incrementedValue, sel=inc, out=incBitStep);
Mux16(a=incBitStep, b=in, sel=load, out=loadBitStep);
Mux16(a=loadBitStep, b=false, sel=reset, out=resetBitStep);
Register(in=resetBitStep, load=true, out=out, out=registerValue);
}

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projects/03/a/RAM64.hdl Normal file
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// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/RAM64.hdl
/**
* Memory of 64 registers, each 16 bit-wide. Out holds the value
* stored at the memory location specified by address. If load==1, then
* the in value is loaded into the memory location specified by address
* (the loaded value will be emitted to out from the next time step onward).
*/
CHIP RAM64 {
IN in[16], load, address[6];
OUT out[16];
PARTS:
// Put your code here:
DMux8Way(in=load, sel=address[3..5], a=toRAM8A,
b=toRAM8B,
c=toRAM8C,
d=toRAM8D,
e=toRAM8E,
f=toRAM8F,
g=toRAM8G,
h=toRAM8H);
RAM8(in=in, load=toRAM8A, address=address[0..2], out=fromRAM8A);
RAM8(in=in, load=toRAM8B, address=address[0..2], out=fromRAM8B);
RAM8(in=in, load=toRAM8C, address=address[0..2], out=fromRAM8C);
RAM8(in=in, load=toRAM8D, address=address[0..2], out=fromRAM8D);
RAM8(in=in, load=toRAM8E, address=address[0..2], out=fromRAM8E);
RAM8(in=in, load=toRAM8F, address=address[0..2], out=fromRAM8F);
RAM8(in=in, load=toRAM8G, address=address[0..2], out=fromRAM8G);
RAM8(in=in, load=toRAM8H, address=address[0..2], out=fromRAM8H);
Mux8Way16(sel=address[3..5], out=out, a=fromRAM8A,
b=fromRAM8B,
c=fromRAM8C,
d=fromRAM8D,
e=fromRAM8E,
f=fromRAM8F,
g=fromRAM8G,
h=fromRAM8H);
}

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// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/RAM8.hdl
/**
* Memory of 8 registers, each 16 bit-wide. Out holds the value
* stored at the memory location specified by address. If load==1, then
* the in value is loaded into the memory location specified by address
* (the loaded value will be emitted to out from the next time step onward).
*/
CHIP RAM8 {
IN in[16], load, address[3];
OUT out[16];
PARTS:
// Put your code here:
DMux8Way(in=load, sel=address, a=toRegisterA,
b=toRegisterB,
c=toRegisterC,
d=toRegisterD,
e=toRegisterE,
f=toRegisterF,
g=toRegisterG,
h=toRegisterH);
Register(in=in, load=toRegisterA, out=fromRegisterA);
Register(in=in, load=toRegisterB, out=fromRegisterB);
Register(in=in, load=toRegisterC, out=fromRegisterC);
Register(in=in, load=toRegisterD, out=fromRegisterD);
Register(in=in, load=toRegisterE, out=fromRegisterE);
Register(in=in, load=toRegisterF, out=fromRegisterF);
Register(in=in, load=toRegisterG, out=fromRegisterG);
Register(in=in, load=toRegisterH, out=fromRegisterH);
Mux8Way16(sel=address, out=out, a=fromRegisterA,
b=fromRegisterB,
c=fromRegisterC,
d=fromRegisterD,
e=fromRegisterE,
f=fromRegisterF,
g=fromRegisterG,
h=fromRegisterH);
}

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// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/Register.hdl
/**
* 16-bit register:
* If load[t] == 1 then out[t+1] = in[t]
* else out does not change
*/
CHIP Register {
IN in[16], load;
OUT out[16];
PARTS:
// Put your code here:
Bit(in=in[0], load=load, out=out[0]);
Bit(in=in[1], load=load, out=out[1]);
Bit(in=in[2], load=load, out=out[2]);
Bit(in=in[3], load=load, out=out[3]);
Bit(in=in[4], load=load, out=out[4]);
Bit(in=in[5], load=load, out=out[5]);
Bit(in=in[6], load=load, out=out[6]);
Bit(in=in[7], load=load, out=out[7]);
Bit(in=in[8], load=load, out=out[8]);
Bit(in=in[9], load=load, out=out[9]);
Bit(in=in[10], load=load, out=out[10]);
Bit(in=in[11], load=load, out=out[11]);
Bit(in=in[12], load=load, out=out[12]);
Bit(in=in[13], load=load, out=out[13]);
Bit(in=in[14], load=load, out=out[14]);
Bit(in=in[15], load=load, out=out[15]);
}

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// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM16K.hdl
/**
* Memory of 16K registers, each 16 bit-wide. Out holds the value
* stored at the memory location specified by address. If load==1, then
* the in value is loaded into the memory location specified by address
* (the loaded value will be emitted to out from the next time step onward).
*/
CHIP RAM16K {
IN in[16], load, address[14];
OUT out[16];
PARTS:
// Put your code here:
DMux4Way(in=load, sel=address[12..13], a=toRAM4KA,
b=toRAM4KB,
c=toRAM4KC,
d=toRAM4KD);
RAM4K(in=in, load=toRAM4KA, address=address[0..11], out=fromRAM4KA);
RAM4K(in=in, load=toRAM4KB, address=address[0..11], out=fromRAM4KB);
RAM4K(in=in, load=toRAM4KC, address=address[0..11], out=fromRAM4KC);
RAM4K(in=in, load=toRAM4KD, address=address[0..11], out=fromRAM4KD);
Mux4Way16(sel=address[12..13], out=out, a=fromRAM4KA,
b=fromRAM4KB,
c=fromRAM4KC,
d=fromRAM4KD);
}

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// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM4K.hdl
/**
* Memory of 4K registers, each 16 bit-wide. Out holds the value
* stored at the memory location specified by address. If load==1, then
* the in value is loaded into the memory location specified by address
* (the loaded value will be emitted to out from the next time step onward).
*/
CHIP RAM4K {
IN in[16], load, address[12];
OUT out[16];
PARTS:
// Put your code here:
DMux8Way(in=load, sel=address[9..11], a=toRAM512A,
b=toRAM512B,
c=toRAM512C,
d=toRAM512D,
e=toRAM512E,
f=toRAM512F,
g=toRAM512G,
h=toRAM512H);
RAM512(in=in, load=toRAM512A, address=address[0..8], out=fromRAM512A);
RAM512(in=in, load=toRAM512B, address=address[0..8], out=fromRAM512B);
RAM512(in=in, load=toRAM512C, address=address[0..8], out=fromRAM512C);
RAM512(in=in, load=toRAM512D, address=address[0..8], out=fromRAM512D);
RAM512(in=in, load=toRAM512E, address=address[0..8], out=fromRAM512E);
RAM512(in=in, load=toRAM512F, address=address[0..8], out=fromRAM512F);
RAM512(in=in, load=toRAM512G, address=address[0..8], out=fromRAM512G);
RAM512(in=in, load=toRAM512H, address=address[0..8], out=fromRAM512H);
Mux8Way16(sel=address[9..11], out=out, a=fromRAM512A,
b=fromRAM512B,
c=fromRAM512C,
d=fromRAM512D,
e=fromRAM512E,
f=fromRAM512F,
g=fromRAM512G,
h=fromRAM512H);
}

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// This file is part of the materials accompanying the book
// "The Elements of Computing Systems" by Nisan and Schocken,
// MIT Press. Book site: www.idc.ac.il/tecs
// File name: projects/03/b/RAM512.hdl
/**
* Memory of 512 registers, each 16 bit-wide. Out holds the value
* stored at the memory location specified by address. If load==1, then
* the in value is loaded into the memory location specified by address
* (the loaded value will be emitted to out from the next time step onward).
*/
CHIP RAM512 {
IN in[16], load, address[9];
OUT out[16];
PARTS:
// Put your code here:
DMux8Way(in=load, sel=address[6..8], a=toRAM64A,
b=toRAM64B,
c=toRAM64C,
d=toRAM64D,
e=toRAM64E,
f=toRAM64F,
g=toRAM64G,
h=toRAM64H);
RAM64(in=in, load=toRAM64A, address=address[0..5], out=fromRAM64A);
RAM64(in=in, load=toRAM64B, address=address[0..5], out=fromRAM64B);
RAM64(in=in, load=toRAM64C, address=address[0..5], out=fromRAM64C);
RAM64(in=in, load=toRAM64D, address=address[0..5], out=fromRAM64D);
RAM64(in=in, load=toRAM64E, address=address[0..5], out=fromRAM64E);
RAM64(in=in, load=toRAM64F, address=address[0..5], out=fromRAM64F);
RAM64(in=in, load=toRAM64G, address=address[0..5], out=fromRAM64G);
RAM64(in=in, load=toRAM64H, address=address[0..5], out=fromRAM64H);
Mux8Way16(sel=address[6..8], out=out, a=fromRAM64A,
b=fromRAM64B,
c=fromRAM64C,
d=fromRAM64D,
e=fromRAM64E,
f=fromRAM64F,
g=fromRAM64G,
h=fromRAM64H);
}