From bde2161900077af5ff8d46b7a8cad13632db41d2 Mon Sep 17 00:00:00 2001 From: Konarak Date: Sun, 5 Dec 2021 09:07:22 +0530 Subject: [PATCH] add project 1, 2, 3 HDLs --- projects/01/And.hdl | 20 ++++++++++++ projects/01/And16.hdl | 33 +++++++++++++++++++ projects/01/DMux.hdl | 21 ++++++++++++ projects/01/DMux4Way.hdl | 25 +++++++++++++++ projects/01/DMux8Way.hdl | 27 ++++++++++++++++ projects/01/Mux.hdl | 22 +++++++++++++ projects/01/Mux16.hdl | 34 ++++++++++++++++++++ projects/01/Mux4Way16.hdl | 25 +++++++++++++++ projects/01/Mux8Way16.hdl | 29 +++++++++++++++++ projects/01/Not.hdl | 18 +++++++++++ projects/01/Not16.hdl | 33 +++++++++++++++++++ projects/01/Or.hdl | 21 ++++++++++++ projects/01/Or16.hdl | 33 +++++++++++++++++++ projects/01/Or8Way.hdl | 24 ++++++++++++++ projects/01/Xor.hdl | 21 ++++++++++++ projects/02/ALU.hdl | 66 ++++++++++++++++++++++++++++++++++++++ projects/02/Add16.hdl | 33 +++++++++++++++++++ projects/02/FullAdder.hdl | 20 ++++++++++++ projects/02/HalfAdder.hdl | 19 +++++++++++ projects/02/Inc16.hdl | 18 +++++++++++ projects/03/a/Bit.hdl | 20 ++++++++++++ projects/03/a/PC.hdl | 25 +++++++++++++++ projects/03/a/RAM64.hdl | 45 ++++++++++++++++++++++++++ projects/03/a/RAM8.hdl | 45 ++++++++++++++++++++++++++ projects/03/a/Register.hdl | 34 ++++++++++++++++++++ projects/03/b/RAM16K.hdl | 33 +++++++++++++++++++ projects/03/b/RAM4K.hdl | 45 ++++++++++++++++++++++++++ projects/03/b/RAM512.hdl | 45 ++++++++++++++++++++++++++ 28 files changed, 834 insertions(+) create mode 100644 projects/01/And.hdl create mode 100644 projects/01/And16.hdl create mode 100644 projects/01/DMux.hdl create mode 100644 projects/01/DMux4Way.hdl create mode 100644 projects/01/DMux8Way.hdl create mode 100644 projects/01/Mux.hdl create mode 100644 projects/01/Mux16.hdl create mode 100644 projects/01/Mux4Way16.hdl create mode 100644 projects/01/Mux8Way16.hdl create mode 100644 projects/01/Not.hdl create mode 100644 projects/01/Not16.hdl create mode 100644 projects/01/Or.hdl create mode 100644 projects/01/Or16.hdl create mode 100644 projects/01/Or8Way.hdl create mode 100644 projects/01/Xor.hdl create mode 100644 projects/02/ALU.hdl create mode 100644 projects/02/Add16.hdl create mode 100644 projects/02/FullAdder.hdl create mode 100644 projects/02/HalfAdder.hdl create mode 100644 projects/02/Inc16.hdl create mode 100644 projects/03/a/Bit.hdl create mode 100644 projects/03/a/PC.hdl create mode 100644 projects/03/a/RAM64.hdl create mode 100644 projects/03/a/RAM8.hdl create mode 100644 projects/03/a/Register.hdl create mode 100644 projects/03/b/RAM16K.hdl create mode 100644 projects/03/b/RAM4K.hdl create mode 100644 projects/03/b/RAM512.hdl diff --git a/projects/01/And.hdl b/projects/01/And.hdl new file mode 100644 index 0000000..593b3bb --- /dev/null +++ b/projects/01/And.hdl @@ -0,0 +1,20 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/And.hdl + +/** + * And gate: + * out = 1 if (a == 1 and b == 1) + * 0 otherwise + */ + +CHIP And { + IN a, b; + OUT out; + + PARTS: + // Put your code here: + Nand(a=a, b=b, out=outz); + Nand(a=outz, b=outz, out=out); +} diff --git a/projects/01/And16.hdl b/projects/01/And16.hdl new file mode 100644 index 0000000..a683e14 --- /dev/null +++ b/projects/01/And16.hdl @@ -0,0 +1,33 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/And16.hdl + +/** + * 16-bit bitwise And: + * for i = 0..15: out[i] = (a[i] and b[i]) + */ + +CHIP And16 { + IN a[16], b[16]; + OUT out[16]; + + PARTS: + // Put your code here: + And(a=a[0], b=b[0], out=out[0]); + And(a=a[1], b=b[1], out=out[1]); + And(a=a[2], b=b[2], out=out[2]); + And(a=a[3], b=b[3], out=out[3]); + And(a=a[4], b=b[4], out=out[4]); + And(a=a[5], b=b[5], out=out[5]); + And(a=a[6], b=b[6], out=out[6]); + And(a=a[7], b=b[7], out=out[7]); + And(a=a[8], b=b[8], out=out[8]); + And(a=a[9], b=b[9], out=out[9]); + And(a=a[10], b=b[10], out=out[10]); + And(a=a[11], b=b[11], out=out[11]); + And(a=a[12], b=b[12], out=out[12]); + And(a=a[13], b=b[13], out=out[13]); + And(a=a[14], b=b[14], out=out[14]); + And(a=a[15], b=b[15], out=out[15]); +} \ No newline at end of file diff --git a/projects/01/DMux.hdl b/projects/01/DMux.hdl new file mode 100644 index 0000000..1f0b6b0 --- /dev/null +++ b/projects/01/DMux.hdl @@ -0,0 +1,21 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/DMux.hdl + +/** + * Demultiplexor: + * {a, b} = {in, 0} if sel == 0 + * {0, in} if sel == 1 + */ + +CHIP DMux { + IN in, sel; + OUT a, b; + + PARTS: + // Put your code here: + Not(in=sel, out=nsel); + And(a=in, b=sel, out=b); + And(a=in, b=nsel, out=a); +} diff --git a/projects/01/DMux4Way.hdl b/projects/01/DMux4Way.hdl new file mode 100644 index 0000000..ae56d64 --- /dev/null +++ b/projects/01/DMux4Way.hdl @@ -0,0 +1,25 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/DMux4Way.hdl + +/** + * 4-way demultiplexor: + * {a, b, c, d} = {in, 0, 0, 0} if sel == 00 + * {0, in, 0, 0} if sel == 01 + * {0, 0, in, 0} if sel == 10 + * {0, 0, 0, in} if sel == 11 + */ + +CHIP DMux4Way { + IN in, sel[2]; + OUT a, b, c, d; + + PARTS: + // Put your code here: + // IN in, sel; + // OUT a, b; + DMux(in=in, sel=sel[1], a=x, b=y); + DMux(in=x, sel=sel[0], a=a, b=b); + DMux(in=y, sel=sel[0], a=c, b=d); +} \ No newline at end of file diff --git a/projects/01/DMux8Way.hdl b/projects/01/DMux8Way.hdl new file mode 100644 index 0000000..9d887c0 --- /dev/null +++ b/projects/01/DMux8Way.hdl @@ -0,0 +1,27 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/DMux8Way.hdl + +/** + * 8-way demultiplexor: + * {a, b, c, d, e, f, g, h} = {in, 0, 0, 0, 0, 0, 0, 0} if sel == 000 + * {0, in, 0, 0, 0, 0, 0, 0} if sel == 001 + * etc. + * {0, 0, 0, 0, 0, 0, 0, in} if sel == 111 + */ + +CHIP DMux8Way { + IN in, sel[3]; + OUT a, b, c, d, e, f, g, h; + + PARTS: + // Put your code here: + DMux(in=in, sel=sel[2], a=i, b=j); + DMux(in=i, sel=sel[1], a=w, b=x); + DMux(in=j, sel=sel[1], a=y, b=z); + DMux(in=w, sel=sel[0], a=a, b=b); + DMux(in=x, sel=sel[0], a=c, b=d); + DMux(in=y, sel=sel[0], a=e, b=f); + DMux(in=z, sel=sel[0], a=g, b=h); +} \ No newline at end of file diff --git a/projects/01/Mux.hdl b/projects/01/Mux.hdl new file mode 100644 index 0000000..47951b0 --- /dev/null +++ b/projects/01/Mux.hdl @@ -0,0 +1,22 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Mux.hdl + +/** + * Multiplexor: + * out = a if sel == 0 + * b otherwise + */ + +CHIP Mux { + IN a, b, sel; + OUT out; + + PARTS: + // Put your code here: + Not(in=sel, out=nsel); + And(a=b, b=sel, out=outx); + And(a=a, b=nsel, out=outy); + Or(a=outx, b=outy, out=out); +} \ No newline at end of file diff --git a/projects/01/Mux16.hdl b/projects/01/Mux16.hdl new file mode 100644 index 0000000..7a3564c --- /dev/null +++ b/projects/01/Mux16.hdl @@ -0,0 +1,34 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Mux16.hdl + +/** + * 16-bit multiplexor: + * for i = 0..15 out[i] = a[i] if sel == 0 + * b[i] if sel == 1 + */ + +CHIP Mux16 { + IN a[16], b[16], sel; + OUT out[16]; + + PARTS: + // Put your code here: + Mux(a=a[0], b=b[0], sel=sel, out=out[0]); + Mux(a=a[1], b=b[1], sel=sel, out=out[1]); + Mux(a=a[2], b=b[2], sel=sel, out=out[2]); + Mux(a=a[3], b=b[3], sel=sel, out=out[3]); + Mux(a=a[4], b=b[4], sel=sel, out=out[4]); + Mux(a=a[5], b=b[5], sel=sel, out=out[5]); + Mux(a=a[6], b=b[6], sel=sel, out=out[6]); + Mux(a=a[7], b=b[7], sel=sel, out=out[7]); + Mux(a=a[8], b=b[8], sel=sel, out=out[8]); + Mux(a=a[9], b=b[9], sel=sel, out=out[9]); + Mux(a=a[10], b=b[10], sel=sel, out=out[10]); + Mux(a=a[11], b=b[11], sel=sel, out=out[11]); + Mux(a=a[12], b=b[12], sel=sel, out=out[12]); + Mux(a=a[13], b=b[13], sel=sel, out=out[13]); + Mux(a=a[14], b=b[14], sel=sel, out=out[14]); + Mux(a=a[15], b=b[15], sel=sel, out=out[15]); +} diff --git a/projects/01/Mux4Way16.hdl b/projects/01/Mux4Way16.hdl new file mode 100644 index 0000000..6aa3fbc --- /dev/null +++ b/projects/01/Mux4Way16.hdl @@ -0,0 +1,25 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Mux4Way16.hdl + +/** + * 4-way 16-bit multiplexor: + * out = a if sel == 00 + * b if sel == 01 + * c if sel == 10 + * d if sel == 11 + */ + +CHIP Mux4Way16 { + IN a[16], b[16], c[16], d[16], sel[2]; + OUT out[16]; + + PARTS: + // Put your code here: + // IN a[16], b[16], sel; + // OUT out[16]; + Mux16(a=a, b=b, sel=sel[0], out=outab); + Mux16(a=c, b=d, sel=sel[0], out=outcd); + Mux16(a=outab, b=outcd, sel=sel[1], out=out); +} \ No newline at end of file diff --git a/projects/01/Mux8Way16.hdl b/projects/01/Mux8Way16.hdl new file mode 100644 index 0000000..95e60a5 --- /dev/null +++ b/projects/01/Mux8Way16.hdl @@ -0,0 +1,29 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Mux8Way16.hdl + +/** + * 8-way 16-bit multiplexor: + * out = a if sel == 000 + * b if sel == 001 + * etc. + * h if sel == 111 + */ + +CHIP Mux8Way16 { + IN a[16], b[16], c[16], d[16], + e[16], f[16], g[16], h[16], + sel[3]; + OUT out[16]; + + PARTS: + // Put your code here: + Mux16(a=a, b=b, sel=sel[0], out=outab); + Mux16(a=c, b=d, sel=sel[0], out=outcd); + Mux16(a=e, b=f, sel=sel[0], out=outef); + Mux16(a=g, b=h, sel=sel[0], out=outgh); + Mux16(a=outab, b=outcd, sel=sel[1], out=outabcd); + Mux16(a=outef, b=outgh, sel=sel[1], out=outefgh); + Mux16(a=outabcd, b=outefgh, sel=sel[2], out=out); +} \ No newline at end of file diff --git a/projects/01/Not.hdl b/projects/01/Not.hdl new file mode 100644 index 0000000..460aa7a --- /dev/null +++ b/projects/01/Not.hdl @@ -0,0 +1,18 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Not.hdl + +/** + * Not gate: + * out = not in + */ + +CHIP Not { + IN in; + OUT out; + + PARTS: + // Put your code here: + Nand(a=in, b=in, out=out); +} \ No newline at end of file diff --git a/projects/01/Not16.hdl b/projects/01/Not16.hdl new file mode 100644 index 0000000..2cac3bd --- /dev/null +++ b/projects/01/Not16.hdl @@ -0,0 +1,33 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Not16.hdl + +/** + * 16-bit Not: + * for i=0..15: out[i] = not in[i] + */ + +CHIP Not16 { + IN in[16]; + OUT out[16]; + + PARTS: + // Put your code here: + Not(in=in[0], out=out[0]); + Not(in=in[1], out=out[1]); + Not(in=in[2], out=out[2]); + Not(in=in[3], out=out[3]); + Not(in=in[4], out=out[4]); + Not(in=in[5], out=out[5]); + Not(in=in[6], out=out[6]); + Not(in=in[7], out=out[7]); + Not(in=in[8], out=out[8]); + Not(in=in[9], out=out[9]); + Not(in=in[10], out=out[10]); + Not(in=in[11], out=out[11]); + Not(in=in[12], out=out[12]); + Not(in=in[13], out=out[13]); + Not(in=in[14], out=out[14]); + Not(in=in[15], out=out[15]); +} \ No newline at end of file diff --git a/projects/01/Or.hdl b/projects/01/Or.hdl new file mode 100644 index 0000000..a1a5ad2 --- /dev/null +++ b/projects/01/Or.hdl @@ -0,0 +1,21 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Or.hdl + + /** + * Or gate: + * out = 1 if (a == 1 or b == 1) + * 0 otherwise + */ + +CHIP Or { + IN a, b; + OUT out; + + PARTS: + // Put your code here: + Nand(a=a, b=a, out=outx); + Nand(a=b, b=b, out=outy); + Nand(a=outx, b=outy, out=out); +} diff --git a/projects/01/Or16.hdl b/projects/01/Or16.hdl new file mode 100644 index 0000000..4244490 --- /dev/null +++ b/projects/01/Or16.hdl @@ -0,0 +1,33 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Or16.hdl + +/** + * 16-bit bitwise Or: + * for i = 0..15 out[i] = (a[i] or b[i]) + */ + +CHIP Or16 { + IN a[16], b[16]; + OUT out[16]; + + PARTS: + // Put your code here: + Or(a=a[0], b=b[0], out=out[0]); + Or(a=a[1], b=b[1], out=out[1]); + Or(a=a[2], b=b[2], out=out[2]); + Or(a=a[3], b=b[3], out=out[3]); + Or(a=a[4], b=b[4], out=out[4]); + Or(a=a[5], b=b[5], out=out[5]); + Or(a=a[6], b=b[6], out=out[6]); + Or(a=a[7], b=b[7], out=out[7]); + Or(a=a[8], b=b[8], out=out[8]); + Or(a=a[9], b=b[9], out=out[9]); + Or(a=a[10], b=b[10], out=out[10]); + Or(a=a[11], b=b[11], out=out[11]); + Or(a=a[12], b=b[12], out=out[12]); + Or(a=a[13], b=b[13], out=out[13]); + Or(a=a[14], b=b[14], out=out[14]); + Or(a=a[15], b=b[15], out=out[15]); +} \ No newline at end of file diff --git a/projects/01/Or8Way.hdl b/projects/01/Or8Way.hdl new file mode 100644 index 0000000..21a9d9d --- /dev/null +++ b/projects/01/Or8Way.hdl @@ -0,0 +1,24 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Or8Way.hdl + +/** + * 8-way Or: + * out = (in[0] or in[1] or ... or in[7]) + */ + +CHIP Or8Way { + IN in[8]; + OUT out; + + PARTS: + // Put your code here: + Or(a=in[0], b=in[1], out=stepA); + Or(a=in[2], b=stepA, out=stepB); + Or(a=in[3], b=stepB, out=stepC); + Or(a=in[4], b=stepC, out=stepD); + Or(a=in[5], b=stepD, out=stepE); + Or(a=in[6], b=stepE, out=stepF); + Or(a=in[7], b=stepF, out=out); +} diff --git a/projects/01/Xor.hdl b/projects/01/Xor.hdl new file mode 100644 index 0000000..075383f --- /dev/null +++ b/projects/01/Xor.hdl @@ -0,0 +1,21 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Xor.hdl + +/** + * Exclusive-or gate: + * out = not (a == b) + */ + +CHIP Xor { + IN a, b; + OUT out; + + PARTS: + // Put your code here: + Nand(a=a, b=b, out=outz); + Nand(a=a, b=outz, out=outx); + Nand(a=b, b=outz, out=outy); + Nand(a=outx, b=outy, out=out); +} \ No newline at end of file diff --git a/projects/02/ALU.hdl b/projects/02/ALU.hdl new file mode 100644 index 0000000..5e8983a --- /dev/null +++ b/projects/02/ALU.hdl @@ -0,0 +1,66 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/02/ALU.hdl + +/** + * The ALU (Arithmetic Logic Unit). + * Computes one of the following functions: + * x+y, x-y, y-x, 0, 1, -1, x, y, -x, -y, !x, !y, + * x+1, y+1, x-1, y-1, x&y, x|y on two 16-bit inputs, + * according to 6 input bits denoted zx,nx,zy,ny,f,no. + * In addition, the ALU computes two 1-bit outputs: + * if the ALU output == 0, zr is set to 1; otherwise zr is set to 0; + * if the ALU output < 0, ng is set to 1; otherwise ng is set to 0. + */ + +// Implementation: the ALU logic manipulates the x and y inputs +// and operates on the resulting values, as follows: +// if (zx == 1) set x = 0 // 16-bit constant +// if (nx == 1) set x = !x // bitwise not +// if (zy == 1) set y = 0 // 16-bit constant +// if (ny == 1) set y = !y // bitwise not +// if (f == 1) set out = x + y // integer 2's complement addition +// if (f == 0) set out = x & y // bitwise and +// if (no == 1) set out = !out // bitwise not +// if (out == 0) set zr = 1 +// if (out < 0) set ng = 1 + +CHIP ALU { + IN + x[16], y[16], // 16-bit inputs + zx, // zero the x input? + nx, // negate the x input? + zy, // zero the y input? + ny, // negate the y input? + f, // compute out = x + y (if 1) or x & y (if 0) + no; // negate the out output? + + OUT + out[16], // 16-bit output + zr, // 1 if (out == 0), 0 otherwise + ng; // 1 if (out < 0), 0 otherwise + + PARTS: + // Put you code here: + Mux16(a=x, b=false, sel=zx, out=xa); + Not16(in=xa, out=xb); + Mux16(a=xa, b=xb, sel=nx, out=xc); + + Mux16(a=y, b=false, sel=zy, out=ya); + Not16(in=ya, out=yb); + Mux16(a=ya, b=yb, sel=ny, out=yc); + + And16(a=xc, b=yc, out=xandy); + Add16(a=xc, b=yc, out=xplusy); + Mux16(a=xandy, b=xplusy, sel=f, out=xf); + + Not16(in=xf, out=xn); + Mux16(a=xf, b=xn, sel=no, out=out, out[15]=ngr, out[0..7]=zri, out[8..15]=zrj); + + Or8Way(in=zri, out=zrm); + Or8Way(in=zrj, out=zrn); + Or(a=zrm, b=zrn, out=zro); + Not(in=zro, out=zr); + Mux(a=false, b=true, sel=ngr, out=ng); +} diff --git a/projects/02/Add16.hdl b/projects/02/Add16.hdl new file mode 100644 index 0000000..ad87f34 --- /dev/null +++ b/projects/02/Add16.hdl @@ -0,0 +1,33 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/02/Adder16.hdl + +/** + * Adds two 16-bit values. + * The most significant carry bit is ignored. + */ + +CHIP Add16 { + IN a[16], b[16]; + OUT out[16]; + + PARTS: + // Put you code here: + HalfAdder(a=a[0], b=b[0], sum=out[0], carry=carry0); + FullAdder(a=a[1], b=b[1], c=carry0, sum=out[1], carry=carry1); + FullAdder(a=a[2], b=b[2], c=carry1, sum=out[2], carry=carry2); + FullAdder(a=a[3], b=b[3], c=carry2, sum=out[3], carry=carry3); + FullAdder(a=a[4], b=b[4], c=carry3, sum=out[4], carry=carry4); + FullAdder(a=a[5], b=b[5], c=carry4, sum=out[5], carry=carry5); + FullAdder(a=a[6], b=b[6], c=carry5, sum=out[6], carry=carry6); + FullAdder(a=a[7], b=b[7], c=carry6, sum=out[7], carry=carry7); + FullAdder(a=a[8], b=b[8], c=carry7, sum=out[8], carry=carry8); + FullAdder(a=a[9], b=b[9], c=carry8, sum=out[9], carry=carry9); + FullAdder(a=a[10], b=b[10], c=carry9, sum=out[10], carry=carry10); + FullAdder(a=a[11], b=b[11], c=carry10, sum=out[11], carry=carry11); + FullAdder(a=a[12], b=b[12], c=carry11, sum=out[12], carry=carry12); + FullAdder(a=a[13], b=b[13], c=carry12, sum=out[13], carry=carry13); + FullAdder(a=a[14], b=b[14], c=carry13, sum=out[14], carry=carry14); + FullAdder(a=a[15], b=b[15], c=carry14, sum=out[15], carry=carry15); +} \ No newline at end of file diff --git a/projects/02/FullAdder.hdl b/projects/02/FullAdder.hdl new file mode 100644 index 0000000..802052d --- /dev/null +++ b/projects/02/FullAdder.hdl @@ -0,0 +1,20 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/02/FullAdder.hdl + +/** + * Computes the sum of three bits. + */ + +CHIP FullAdder { + IN a, b, c; // 1-bit inputs + OUT sum, // Right bit of a + b + c + carry; // Left bit of a + b + c + + PARTS: + // Put you code here: + HalfAdder(a=a, b=b, sum=sumi, carry=carryi); + HalfAdder(a=c, b=sumi, sum=sum, carry=carryj); + Or(a=carryi, b=carryj, out=carry); +} diff --git a/projects/02/HalfAdder.hdl b/projects/02/HalfAdder.hdl new file mode 100644 index 0000000..4bcb03c --- /dev/null +++ b/projects/02/HalfAdder.hdl @@ -0,0 +1,19 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/02/HalfAdder.hdl + +/** + * Computes the sum of two bits. + */ + +CHIP HalfAdder { + IN a, b; // 1-bit inputs + OUT sum, // Right bit of a + b + carry; // Left bit of a + b + + PARTS: + // Put you code here: + Xor(a=a, b=b, out=sum); + And(a=a, b=b, out=carry); +} diff --git a/projects/02/Inc16.hdl b/projects/02/Inc16.hdl new file mode 100644 index 0000000..5f5d9bd --- /dev/null +++ b/projects/02/Inc16.hdl @@ -0,0 +1,18 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/02/Inc16.hdl + +/** + * 16-bit incrementer: + * out = in + 1 (arithmetic addition) + */ + +CHIP Inc16 { + IN in[16]; + OUT out[16]; + + PARTS: + // Put you code here: + Add16(a=in, b[0]=true, b[1..15]=false, out=out); +} \ No newline at end of file diff --git a/projects/03/a/Bit.hdl b/projects/03/a/Bit.hdl new file mode 100644 index 0000000..8029591 --- /dev/null +++ b/projects/03/a/Bit.hdl @@ -0,0 +1,20 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/a/Bit.hdl + +/** + * 1-bit register: + * If load[t] == 1 then out[t+1] = in[t] + * else out does not change (out[t+1] = out[t]) + */ + +CHIP Bit { + IN in, load; + OUT out; + + PARTS: + // Put your code here: + Mux(a=dffout, b=in, sel=load, out=muxout); + DFF(in=muxout, out=out, out=dffout); +} diff --git a/projects/03/a/PC.hdl b/projects/03/a/PC.hdl new file mode 100644 index 0000000..fe5fdde --- /dev/null +++ b/projects/03/a/PC.hdl @@ -0,0 +1,25 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/a/PC.hdl + +/** + * A 16-bit counter with load and reset control bits. + * if (reset[t] == 1) out[t+1] = 0 + * else if (load[t] == 1) out[t+1] = in[t] + * else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition) + * else out[t+1] = out[t] + */ + +CHIP PC { + IN in[16], load, inc, reset; + OUT out[16]; + + PARTS: + // Put your code here: + Inc16(in=registerValue, out=incrementedValue); + Mux16(a=registerValue, b=incrementedValue, sel=inc, out=incBitStep); + Mux16(a=incBitStep, b=in, sel=load, out=loadBitStep); + Mux16(a=loadBitStep, b=false, sel=reset, out=resetBitStep); + Register(in=resetBitStep, load=true, out=out, out=registerValue); +} diff --git a/projects/03/a/RAM64.hdl b/projects/03/a/RAM64.hdl new file mode 100644 index 0000000..b58b13a --- /dev/null +++ b/projects/03/a/RAM64.hdl @@ -0,0 +1,45 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/a/RAM64.hdl + +/** + * Memory of 64 registers, each 16 bit-wide. Out holds the value + * stored at the memory location specified by address. If load==1, then + * the in value is loaded into the memory location specified by address + * (the loaded value will be emitted to out from the next time step onward). + */ + +CHIP RAM64 { + IN in[16], load, address[6]; + OUT out[16]; + + PARTS: + // Put your code here: + DMux8Way(in=load, sel=address[3..5], a=toRAM8A, + b=toRAM8B, + c=toRAM8C, + d=toRAM8D, + e=toRAM8E, + f=toRAM8F, + g=toRAM8G, + h=toRAM8H); + + RAM8(in=in, load=toRAM8A, address=address[0..2], out=fromRAM8A); + RAM8(in=in, load=toRAM8B, address=address[0..2], out=fromRAM8B); + RAM8(in=in, load=toRAM8C, address=address[0..2], out=fromRAM8C); + RAM8(in=in, load=toRAM8D, address=address[0..2], out=fromRAM8D); + RAM8(in=in, load=toRAM8E, address=address[0..2], out=fromRAM8E); + RAM8(in=in, load=toRAM8F, address=address[0..2], out=fromRAM8F); + RAM8(in=in, load=toRAM8G, address=address[0..2], out=fromRAM8G); + RAM8(in=in, load=toRAM8H, address=address[0..2], out=fromRAM8H); + + Mux8Way16(sel=address[3..5], out=out, a=fromRAM8A, + b=fromRAM8B, + c=fromRAM8C, + d=fromRAM8D, + e=fromRAM8E, + f=fromRAM8F, + g=fromRAM8G, + h=fromRAM8H); +} diff --git a/projects/03/a/RAM8.hdl b/projects/03/a/RAM8.hdl new file mode 100644 index 0000000..3c0fb1a --- /dev/null +++ b/projects/03/a/RAM8.hdl @@ -0,0 +1,45 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/a/RAM8.hdl + +/** + * Memory of 8 registers, each 16 bit-wide. Out holds the value + * stored at the memory location specified by address. If load==1, then + * the in value is loaded into the memory location specified by address + * (the loaded value will be emitted to out from the next time step onward). + */ + +CHIP RAM8 { + IN in[16], load, address[3]; + OUT out[16]; + + PARTS: + // Put your code here: + DMux8Way(in=load, sel=address, a=toRegisterA, + b=toRegisterB, + c=toRegisterC, + d=toRegisterD, + e=toRegisterE, + f=toRegisterF, + g=toRegisterG, + h=toRegisterH); + + Register(in=in, load=toRegisterA, out=fromRegisterA); + Register(in=in, load=toRegisterB, out=fromRegisterB); + Register(in=in, load=toRegisterC, out=fromRegisterC); + Register(in=in, load=toRegisterD, out=fromRegisterD); + Register(in=in, load=toRegisterE, out=fromRegisterE); + Register(in=in, load=toRegisterF, out=fromRegisterF); + Register(in=in, load=toRegisterG, out=fromRegisterG); + Register(in=in, load=toRegisterH, out=fromRegisterH); + + Mux8Way16(sel=address, out=out, a=fromRegisterA, + b=fromRegisterB, + c=fromRegisterC, + d=fromRegisterD, + e=fromRegisterE, + f=fromRegisterF, + g=fromRegisterG, + h=fromRegisterH); +} diff --git a/projects/03/a/Register.hdl b/projects/03/a/Register.hdl new file mode 100644 index 0000000..44493aa --- /dev/null +++ b/projects/03/a/Register.hdl @@ -0,0 +1,34 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/a/Register.hdl + +/** + * 16-bit register: + * If load[t] == 1 then out[t+1] = in[t] + * else out does not change + */ + +CHIP Register { + IN in[16], load; + OUT out[16]; + + PARTS: + // Put your code here: + Bit(in=in[0], load=load, out=out[0]); + Bit(in=in[1], load=load, out=out[1]); + Bit(in=in[2], load=load, out=out[2]); + Bit(in=in[3], load=load, out=out[3]); + Bit(in=in[4], load=load, out=out[4]); + Bit(in=in[5], load=load, out=out[5]); + Bit(in=in[6], load=load, out=out[6]); + Bit(in=in[7], load=load, out=out[7]); + Bit(in=in[8], load=load, out=out[8]); + Bit(in=in[9], load=load, out=out[9]); + Bit(in=in[10], load=load, out=out[10]); + Bit(in=in[11], load=load, out=out[11]); + Bit(in=in[12], load=load, out=out[12]); + Bit(in=in[13], load=load, out=out[13]); + Bit(in=in[14], load=load, out=out[14]); + Bit(in=in[15], load=load, out=out[15]); +} diff --git a/projects/03/b/RAM16K.hdl b/projects/03/b/RAM16K.hdl new file mode 100644 index 0000000..c11a14d --- /dev/null +++ b/projects/03/b/RAM16K.hdl @@ -0,0 +1,33 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/b/RAM16K.hdl + +/** + * Memory of 16K registers, each 16 bit-wide. Out holds the value + * stored at the memory location specified by address. If load==1, then + * the in value is loaded into the memory location specified by address + * (the loaded value will be emitted to out from the next time step onward). + */ + +CHIP RAM16K { + IN in[16], load, address[14]; + OUT out[16]; + + PARTS: + // Put your code here: + DMux4Way(in=load, sel=address[12..13], a=toRAM4KA, + b=toRAM4KB, + c=toRAM4KC, + d=toRAM4KD); + + RAM4K(in=in, load=toRAM4KA, address=address[0..11], out=fromRAM4KA); + RAM4K(in=in, load=toRAM4KB, address=address[0..11], out=fromRAM4KB); + RAM4K(in=in, load=toRAM4KC, address=address[0..11], out=fromRAM4KC); + RAM4K(in=in, load=toRAM4KD, address=address[0..11], out=fromRAM4KD); + + Mux4Way16(sel=address[12..13], out=out, a=fromRAM4KA, + b=fromRAM4KB, + c=fromRAM4KC, + d=fromRAM4KD); +} diff --git a/projects/03/b/RAM4K.hdl b/projects/03/b/RAM4K.hdl new file mode 100644 index 0000000..3da79f3 --- /dev/null +++ b/projects/03/b/RAM4K.hdl @@ -0,0 +1,45 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/b/RAM4K.hdl + +/** + * Memory of 4K registers, each 16 bit-wide. Out holds the value + * stored at the memory location specified by address. If load==1, then + * the in value is loaded into the memory location specified by address + * (the loaded value will be emitted to out from the next time step onward). + */ + +CHIP RAM4K { + IN in[16], load, address[12]; + OUT out[16]; + + PARTS: + // Put your code here: + DMux8Way(in=load, sel=address[9..11], a=toRAM512A, + b=toRAM512B, + c=toRAM512C, + d=toRAM512D, + e=toRAM512E, + f=toRAM512F, + g=toRAM512G, + h=toRAM512H); + + RAM512(in=in, load=toRAM512A, address=address[0..8], out=fromRAM512A); + RAM512(in=in, load=toRAM512B, address=address[0..8], out=fromRAM512B); + RAM512(in=in, load=toRAM512C, address=address[0..8], out=fromRAM512C); + RAM512(in=in, load=toRAM512D, address=address[0..8], out=fromRAM512D); + RAM512(in=in, load=toRAM512E, address=address[0..8], out=fromRAM512E); + RAM512(in=in, load=toRAM512F, address=address[0..8], out=fromRAM512F); + RAM512(in=in, load=toRAM512G, address=address[0..8], out=fromRAM512G); + RAM512(in=in, load=toRAM512H, address=address[0..8], out=fromRAM512H); + + Mux8Way16(sel=address[9..11], out=out, a=fromRAM512A, + b=fromRAM512B, + c=fromRAM512C, + d=fromRAM512D, + e=fromRAM512E, + f=fromRAM512F, + g=fromRAM512G, + h=fromRAM512H); +} diff --git a/projects/03/b/RAM512.hdl b/projects/03/b/RAM512.hdl new file mode 100644 index 0000000..cae77f6 --- /dev/null +++ b/projects/03/b/RAM512.hdl @@ -0,0 +1,45 @@ +// This file is part of the materials accompanying the book +// "The Elements of Computing Systems" by Nisan and Schocken, +// MIT Press. Book site: www.idc.ac.il/tecs +// File name: projects/03/b/RAM512.hdl + +/** + * Memory of 512 registers, each 16 bit-wide. Out holds the value + * stored at the memory location specified by address. If load==1, then + * the in value is loaded into the memory location specified by address + * (the loaded value will be emitted to out from the next time step onward). + */ + +CHIP RAM512 { + IN in[16], load, address[9]; + OUT out[16]; + + PARTS: + // Put your code here: + DMux8Way(in=load, sel=address[6..8], a=toRAM64A, + b=toRAM64B, + c=toRAM64C, + d=toRAM64D, + e=toRAM64E, + f=toRAM64F, + g=toRAM64G, + h=toRAM64H); + + RAM64(in=in, load=toRAM64A, address=address[0..5], out=fromRAM64A); + RAM64(in=in, load=toRAM64B, address=address[0..5], out=fromRAM64B); + RAM64(in=in, load=toRAM64C, address=address[0..5], out=fromRAM64C); + RAM64(in=in, load=toRAM64D, address=address[0..5], out=fromRAM64D); + RAM64(in=in, load=toRAM64E, address=address[0..5], out=fromRAM64E); + RAM64(in=in, load=toRAM64F, address=address[0..5], out=fromRAM64F); + RAM64(in=in, load=toRAM64G, address=address[0..5], out=fromRAM64G); + RAM64(in=in, load=toRAM64H, address=address[0..5], out=fromRAM64H); + + Mux8Way16(sel=address[6..8], out=out, a=fromRAM64A, + b=fromRAM64B, + c=fromRAM64C, + d=fromRAM64D, + e=fromRAM64E, + f=fromRAM64F, + g=fromRAM64G, + h=fromRAM64H); +}