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5527f9e8b2
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spi test dump
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2024-10-25 13:47:27 -04:00 |
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2026be6851
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build hack with UART TX / RX support
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2024-10-21 20:04:09 -04:00 |
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ecacf86e9f
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wip dump
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2024-10-21 20:01:45 -04:00 |
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792efa70cd
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add verilog files for project one through five
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2024-10-17 14:38:28 -04:00 |
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Michael Schröder
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b16bfcfd43
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changed python tools to python3.11
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2023-08-04 16:44:31 +02:00 |
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Michael Schröder
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f476ed8da2
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corrected leds.png and mult.png
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2023-08-04 09:42:15 +02:00 |
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Michael Schröder
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c3cd7b1058
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corrected typo in BitShift9R
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2023-04-15 08:29:38 +02:00 |
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Michael Schröder
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6f6eb8436a
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typo in description of in[8]
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2023-02-03 15:39:21 +01:00 |
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Michael Schröder
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971b323822
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added v2.0
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2023-01-11 23:04:57 +01:00 |
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Michael Schröder
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2a5a64ca91
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added Readme.md
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2023-01-11 11:09:47 +01:00 |
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