WIP optimizations on SPI/UART
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@ -134,7 +134,7 @@ module HACK(
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Mux16 SWITCHD(ROM_DATA, inIO6, load_sram, instruction);
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Register SRAM_A(clk, outM, loadIO5, inIO5);
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SRAM_D SRAM_D(clk, loadIO6, outM, inIO6, SRAM_DATA, SRAM_CSX, SRAM_OEX, SRAM_WEX);
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LCD LCD(clk, loadIO8, loadIO9, outM, fromLCD, LCD_DCX, LCD_CSX, LCD_SDO, LCD_SCK);
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//LCD LCD(clk, loadIO8, loadIO9, outM, fromLCD, LCD_DCX, LCD_CSX, LCD_SDO, LCD_SCK);
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Register DEBUG0(clk, outM, loadIOB, inIOB);
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Register DEBUG1(clk, outM, loadIOC, inIOC);
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@ -150,10 +150,10 @@ module HACK(
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//assign SRAM_WEX=0;
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//assign SRAM_OEX=0;
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//assign SRAM_CSX=0;
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//assign LCD_DCX=0;
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//assign LCD_SDO=0;
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//assign LCD_SCK=0;
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//assign LCD_CSX=0;
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assign LCD_DCX=0;
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assign LCD_SDO=0;
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assign LCD_SCK=0;
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assign LCD_CSX=0;
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assign RTP_SDO=0;
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assign RTP_SCK=0;
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endmodule
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@ -22,103 +22,64 @@ module SPI(
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// Put your code here:
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// 1100 0000 0101 1011
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// 1000 0000 0101 1011
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reg active=0;
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reg csx_low=0;
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reg out_low=1;
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reg [7:0] totx;
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reg [7:0] torx;
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reg [4:0] is16;
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reg active;
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reg [2:0] bit_index;
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reg [7:0] shift_out;
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reg [7:0] shift_in;
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reg [4:0] count;
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wire is_sample_phase = (count >= 1 && count <= 15 && count[0] == 1);
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wire is_shift_phase = (count >= 2 && count <= 16 && count[0] == 0);
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initial begin
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SDO <= 0;
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CSX <= 1'b1;
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out <= 16'b0;
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bit_index <= 3'b0;
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end
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always @(posedge clk) begin
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CSX <= (csx_low) ? 0 : 1;
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SDO <= 0;
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SCK <= 0;
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out <= (out)? out : 0;
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if (load == 1) begin
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out_low=0;
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out[14:8] <= 0;
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out[7:0] <= in[7:0];
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if (in[8]==1) begin
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out[15] <= 0;
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csx_low <= 0;
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CSX <= 1;
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end
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else if (in[8]==0) begin
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out[15] <= 1;
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csx_low <= 1;
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CSX <= 0;
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CSX <= 1;
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out <= { 8'b0, in[7:0] };
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if (!in[8]) begin
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active <= 1;
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is16 <= 1;
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totx[7:0] <= in[7:0];
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count <= 1;
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bit_index <= 7; // byte order MSB->LSB
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CSX <= 0;
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out[15] <= 1;
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shift_out[7:0] <= in[7:0];
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SDO <= in[7];
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end
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end
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else if (active==1) begin
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SCK <= ~SCK;
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if (is16 == 16) begin
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if (count == 16) begin
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SDO <= 0;
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out <= {8'b0, shift_in};
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active <= 0;
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out <= {8'b0, torx[7:0]};
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end else begin
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count <= count + 1;
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if (is_shift_phase) begin
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// bit_index = bit_index - 1
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bit_index <= 7 - ((count) >> 1);
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out[7:0] <= {out[6:0], shift_in[bit_index]};
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shift_out <= {shift_out[6:0], 1'b0};
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SDO <= shift_out[6]; // next bit
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end
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if (is_sample_phase) begin
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shift_in[bit_index] <= SDI;
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end
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end
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else begin
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csx_low <= 1;
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is16 <= is16 + 1;
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case (is16+1)
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2 : SDO <= totx[7];
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3 : SDO <= totx[6];
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4 : SDO <= totx[6];
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5 : SDO <= totx[5];
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6 : SDO <= totx[5];
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7 : SDO <= totx[4];
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8 : SDO <= totx[4];
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9 : SDO <= totx[3];
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10 : SDO <= totx[3];
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11 : SDO <= totx[2];
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12 : SDO <= totx[2];
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13 : SDO <= totx[1];
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14 : SDO <= totx[1];
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15 : SDO <= totx[0];
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16 : SDO <= totx[0];
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endcase
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case (is16)
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1 : torx[7] <= SDI;
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3 : torx[6] <= SDI;
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5 : torx[5] <= SDI;
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7 : torx[4] <= SDI;
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9 : torx[3] <= SDI;
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11 : torx[2] <= SDI;
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13 : torx[1] <= SDI;
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15 : torx[0] <= SDI;
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endcase
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case (is16)
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2 : out <= (out<<1);
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4 : out <= (out<<1);
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6 : out <= (out<<1);
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8 : out <= (out<<1);
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10 : out <= (out<<1);
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12 : out <= (out<<1);
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14 : out <= (out<<1);
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endcase
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case (is16)
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2 : out[0] <= torx[7];
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4 : out[0] <= torx[6];
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6 : out[0] <= torx[5];
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8 : out[0] <= torx[4];
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10 : out[0] <= torx[3];
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12 : out[0] <= torx[2];
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14 : out[0] <= torx[1];
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endcase
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case (is16)
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2 : out[15:8] <= 8'b10000000;
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4 : out[15:8] <= 8'b10000000;
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6 : out[15:8] <= 8'b10000000;
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8 : out[15:8] <= 8'b10000000;
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10 : out[15:8] <= 8'b10000000;
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12 : out[15:8] <= 8'b10000000;
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14 : out[15:8] <= 8'b10000000;
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endcase
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end
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end else begin
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out <= out_low? 16'b0 : out;
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end
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end
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endmodule
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@ -7,47 +7,49 @@
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* of byte completes, chip ouputs the received byte to out[7:0]] with out[15]=0.
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*/
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`default_nettype none
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module UartRX(
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input clk,
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input clear,
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input RX,
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module UartRX (
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input wire clk,
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input wire clear,
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input wire RX,
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output reg [15:0] out
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);
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// Put your code here:
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wire clkdRX;
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reg active=0;
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reg out_set=0;
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reg [7:0] uart;
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reg [3:0] nthbit;
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reg [9:0] is216;
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reg [7:0] baud_count;
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reg [3:0] bit_index;
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reg [7:0] rx_shift;
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reg rx_active;
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initial begin
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out <= 16'b0;
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rx_active <= 1'b0;
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end
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always @(posedge clk) begin
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out_set <= clear ? 1 : out_set;
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out <= clear ? 16'h8000 : (out_set ? out : 16'h0000);
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if ((active==0) && (RX == 0)) begin
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out_set <=1;
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active <= 1;
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is216 <= 1;
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uart <= 0;
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nthbit <= 0;
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end
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else if (active==1) begin
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is216 <= (is216 == 216) ? 0 : is216 + 1;
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nthbit <= (is216 == 108) ? nthbit + 1 : nthbit;
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case (nthbit)
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1 : uart[0] <= RX;
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2 : uart[1] <= RX;
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3 : uart[2] <= RX;
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4 : uart[3] <= RX;
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5 : uart[4] <= RX;
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6 : uart[5] <= RX;
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7 : uart[6] <= RX;
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8 : uart[7] <= RX;
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endcase
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if (nthbit == 10 && is216 == 216) begin
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active <= 0;
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out <= {8'b0, uart};
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out <= (clear | out[15]) ? 16'h8000 : out;
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if (!rx_active && !RX) begin
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// RX Falling edge: Start bit detected
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rx_active <= 1;
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rx_shift <= 0;
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baud_count <= 1;
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bit_index <= 0;
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end else if (rx_active) begin
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baud_count <= (baud_count == 216) ? 0 : baud_count + 1;
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bit_index <= (baud_count == 108) ? bit_index + 1 : bit_index;
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if (bit_index >= 1 && bit_index <= 8 && baud_count == 108) begin
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rx_shift <= {RX, rx_shift[7:1]};
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end
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if (bit_index == 10 && baud_count == 216) begin
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rx_active <= 0; // Done receiving 8 bits + stop
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out <= {8'b0, rx_shift};
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end
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end
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end
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endmodule
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@ -8,47 +8,50 @@
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* low again (ready).
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*/
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`default_nettype none
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module UartTX(
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input clk,
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input load,
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input [15:0] in,
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output TX,
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module UartTX (
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input wire clk,
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input wire load,
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input wire [15:0] in,
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output wire TX,
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output reg [15:0] out
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);
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reg uart=1;
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reg active=0;
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reg [7:0] to_send;
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reg [3:0] nthbit=0;
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reg [9:0] is216;
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always @(posedge clk) begin
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out <= (load || active) ? 16'h8000 : 16'h0000;
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reg [9:0] baud_count;
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reg [3:0] bit_index;
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reg [9:0] shift_reg;
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reg tx_active;
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if ((active==0) && (load == 1)) begin
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active <= 1;
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is216 <= 1;
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nthbit <= 0;
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uart <= 0;
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to_send <= in[7:0];
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end
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else if (active==1) begin
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is216 <= (is216 == 216) ? 0 : is216 + 1;
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nthbit <= (is216 == 216) ? nthbit + 1 : nthbit;
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case (nthbit)
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0 : uart <= 0;
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1 : uart <= to_send[0];
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2 : uart <= to_send[1];
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3 : uart <= to_send[2];
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4 : uart <= to_send[3];
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5 : uart <= to_send[4];
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6 : uart <= to_send[5];
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7 : uart <= to_send[6];
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8 : uart <= to_send[7];
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9 : uart <= 1;
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10 : begin active <= 0; out <= 16'h0000; end
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endcase
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initial begin
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tx_active <= 1'b0;
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shift_reg <= 10'b1;
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end
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always @(posedge clk) begin
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// Output status
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out <= (load || tx_active) ? 16'h8000 : 16'h0000;
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if (!tx_active && load) begin
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// Load start bit + data + stop bit into shift register
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shift_reg <= {1'b1, in[7:0], 1'b0}; // {stop, data[7:0], start}
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tx_active <= 1;
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baud_count <= 0;
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bit_index <= 0;
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end else if (tx_active) begin
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if (baud_count == 216) begin
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baud_count <= 0;
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bit_index <= bit_index + 1;
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shift_reg <= {1'b1, shift_reg[9:1]}; // shift in stop bit after final bit
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if (bit_index == 9) begin
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tx_active <= 0;
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out <= 16'h0000;
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end
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end else begin
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baud_count <= baud_count + 1;
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end
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end
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end
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assign TX = uart;
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assign TX = shift_reg[0];
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endmodule
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