added v2.0

01_Boolean_Logic/00_Nand/Include.v

@@ -0,0 +1 @@
+`include "../../01_Boolean_Logic/Nand.v"

01_Boolean_Logic/00_Nand/Nand_tb.gtkw

@@ -0,0 +1,32 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:24:30 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/00_Nand/Nand_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:23:51 2022"
+[dumpfile_size] 466
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/00_Nand/Nand_tb.gtkw"
+[timestart] 0
+[size] 1348 589
+[pos] -1 -1
+*-0.771027 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 100
+[sst_expanded] 1
+[sst_vpaned_height] 129
+@200
+-IN
+@28
+Nand_tb.a
+Nand_tb.b
+@200
+-OUT
+@28
+Nand_tb.out
+@200
+-CMP
+@28
+Nand_tb.out_cmp
+Nand_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/00_Nand/Nand_tb.v

@@ -0,0 +1,47 @@
+`default_nettype none
+module Nand_tb();
+	
+	// IN,OUT
+	reg a,b;
+	wire out;
+
+	// Part
+	Nand NAND(
+		.a(a),
+		.b(b),
+		.out(out)
+	);
+
+	// Compare
+	wire out_cmp;
+	assign out_cmp = ~(a&b);
+	
+	reg fail = 0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: a=%1b, b=%1b, out=%1b",a,b,out);
+				fail=1;
+			end
+	endtask
+	  
+  	// Test	
+	initial begin
+  		$dumpfile("Nand_tb.vcd");
+  		$dumpvars(0, Nand_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Nand");
+		
+		a=0;b=0;check();
+		a=0;b=1;check();
+		a=1;b=0;check();
+		a=1;b=1;check();
+			
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/00_Nand/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/00_Nand/iCE40HX1K.pcf

@@ -0,0 +1,10 @@
+# physical constrain file
+# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB
+# compare to the schematic of the board and the datasheet of fpga
+
+set_io BUT1 41	# BUT1
+set_io BUT2 42	# BUT2
+
+set_io LED1 40	# LED1
+set_io LED2 51	# LED2
+

01_Boolean_Logic/00_Nand/top.v

@@ -0,0 +1,11 @@
+`default_nettype none
+module top(
+	input BUT1,
+	input BUT2,
+	output LED1,
+	output LED2
+);
+
+	Nand NAND(.a(BUT1),.b(BUT2),.out(LED1));
+	
+endmodule

01_Boolean_Logic/01_Not/Include.v

@@ -0,0 +1,2 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"

01_Boolean_Logic/01_Not/Not_tb.gtkw

@@ -0,0 +1,32 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:25:30 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/01_Not/Not_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:25:02 2022"
+[dumpfile_size] 404
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/01_Not/Not_tb.gtkw"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*-0.034062 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 100
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@28
+Not_tb.in
+@200
+-OUT
+@28
+Not_tb.out
+@200
+-Test
+@29
+Not_tb.out_cmp
+@28
+Not_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/01_Not/Not_tb.v

@@ -0,0 +1,44 @@
+`default_nettype none
+module Not_tb();
+
+	// IN,OUT
+	reg in;
+	wire out;
+
+	// Part
+	Not NOT(
+		.in(in),
+		.out(out)
+	);
+
+	// Compare
+	wire out_cmp;
+	assign out_cmp = ~in;
+
+	reg fail = 0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: in=%1b, out=%1b",in,out);
+				fail=1;
+			end
+	endtask
+	
+	// Test 
+  	initial begin
+  		$dumpfile("Not_tb.vcd");
+  		$dumpvars(0, Not_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Not");
+		
+		in=0;check();
+		in=1;check();
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/01_Not/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/01_Not/iCE40HX1K.pcf

@@ -0,0 +1,10 @@
+# physical constrain file
+# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB
+# compare to the schematic of the board and the datasheet of fpga
+
+set_io BUT1 41	# BUT1
+set_io BUT2 42	# BUT2
+
+set_io LED1 40	# LED1
+set_io LED2 51	# LED2
+

01_Boolean_Logic/01_Not/top.v

@@ -0,0 +1,12 @@
+`default_nettype none
+module top(
+	input BUT1,
+	input BUT2,
+	output LED1,
+	output LED2
+);
+
+	Not NOT1(.in(BUT1),.out(LED1));
+	Not NOT2(.in(BUT2),.out(LED2));
+	
+endmodule

01_Boolean_Logic/02_Buffer/Buffer_tb.gtkw

@@ -0,0 +1,31 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Fri Nov 25 09:50:44 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/0_Buffer/Buffer_tb.vcd"
+[dumpfile_mtime] "Fri Nov 25 09:50:10 2022"
+[dumpfile_size] 413
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/0_Buffer/Buffer_tb.gtkw"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*-0.034062 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 100
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@201
+-IN
+@28
+Buffer_tb.in
+@200
+-OUT
+@28
+Buffer_tb.out
+@200
+-CMP
+@28
+Buffer_tb.out_cmp
+Buffer_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/02_Buffer/Buffer_tb.v

@@ -0,0 +1,44 @@
+`default_nettype none
+module Buffer_tb();
+	
+	// IN,OUT
+	reg in;
+	wire out;
+
+	// Part
+	Buffer BUFFER(
+		.in(in),
+		.out(out)
+	);
+
+	// Compare
+	wire out_cmp;
+	assign out_cmp = in;
+	
+	reg fail = 0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: in=%1b, out=%1b",in,out);
+				fail=1;
+			end
+	endtask
+	  
+  	// Test	
+	initial begin
+  		$dumpfile("Buffer_tb.vcd");
+  		$dumpvars(0, Buffer_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Buffer");
+		
+		in=0;check();
+		in=1;check();
+			
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/02_Buffer/Include.v

@@ -0,0 +1,3 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"

01_Boolean_Logic/02_Buffer/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/02_Buffer/iCE40HX1K.pcf

@@ -0,0 +1,10 @@
+# physical constrain file
+# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB
+# compare to the schematic of the board and the datasheet of fpga
+
+set_io BUT1 41	# BUT1
+set_io BUT2 42	# BUT2
+
+set_io LED1 40	# LED1
+set_io LED2 51	# LED2
+

01_Boolean_Logic/02_Buffer/top.v

@@ -0,0 +1,12 @@
+`default_nettype none
+module top(
+	input BUT1,
+	input BUT2,
+	output LED1,
+	output LED2
+);
+
+	Buffer BUFFER1(.in(BUT1),.out(LED1));
+	Buffer BUFFER2(.in(BUT2),.out(LED2));
+	
+endmodule

01_Boolean_Logic/03_And/And_tb.gtkw

@@ -0,0 +1,33 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:37:27 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/03_And/And_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:36:57 2022"
+[dumpfile_size] 779
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/03_And/And_tb.gtkw"
+[timestart] 0
+[size] 1227 600
+[pos] -1 -1
+*-0.771027 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 100
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@29
+And_tb.a
+@28
+And_tb.b
+@200
+-OUT
+@28
+And_tb.out
+@200
+-CMP
+@28
+And_tb.out_cmp
+And_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/03_And/And_tb.v

@@ -0,0 +1,47 @@
+`default_nettype none
+module And_tb();
+
+	// IN,OUT
+	reg a,b;
+	wire out;
+
+	// Part
+	And AND(
+		.a(a),
+		.b(b),
+		.out(out)
+	);
+	
+	// Compare
+	wire out_cmp;
+	assign out_cmp = a&b;
+
+	reg fail = 0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: a=%1b,b=%1b,out=%1b",a,b,out);
+				fail=1;
+			end
+	endtask
+	  
+  	// Test
+	initial begin
+  		$dumpfile("And_tb.vcd");
+  		$dumpvars(0, And_tb);
+		
+		$display("------------------------");
+		$display("Testbench: And");
+		
+		a=0;b=0;check();
+		a=0;b=1;check();
+		a=1;b=0;check();
+		a=1;b=1;check();
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/03_And/Include.v

@@ -0,0 +1,4 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"

01_Boolean_Logic/03_And/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/03_And/iCE40HX1K.pcf

@@ -0,0 +1,10 @@
+# physical constrain file
+# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB
+# compare to the schematic of the board and the datasheet of fpga
+
+set_io BUT1 41	# BUT1
+set_io BUT2 42	# BUT2
+
+set_io LED1 40	# LED1
+set_io LED2 51	# LED2
+

01_Boolean_Logic/03_And/top.v

@@ -0,0 +1,11 @@
+`default_nettype none
+module top(
+	input BUT1,
+	input BUT2,
+	output LED1,
+	output LED2
+);
+
+	And AND(.a(BUT1),.b(BUT2),.out(LED1));
+	
+endmodule

01_Boolean_Logic/04_Or/Include.v

@@ -0,0 +1,5 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"

01_Boolean_Logic/04_Or/Or_tb.gtkw

@@ -0,0 +1,35 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:50:31 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/04_Or/Or_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:50:17 2022"
+[dumpfile_size] 999
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/04_Or/Or_tb.gtkw"
+[timestart] 0
+[size] 1292 600
+[pos] -1 -1
+*-0.771027 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 100
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@28
+Or_tb.a
+Or_tb.b
+@200
+-OUT
+@28
+Or_tb.out
+@200
+-CMP
+@29
+Or_tb.out_cmp
+@200
+-Test
+@28
+Or_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/04_Or/Or_tb.v

@@ -0,0 +1,48 @@
+`default_nettype none
+module Or_tb();
+
+	// IN,OUT
+	reg a,b;
+	wire out;
+
+	// Part
+	Or OR(
+		.a(a),
+		.b(b),
+		.out(out)
+	);
+
+	// Compare
+	wire out_cmp;
+	assign out_cmp = a|b;
+
+	reg fail=0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: a=%1b, b=%1b, out=%1b",a,b,out);
+				fail=1;
+			end
+	endtask
+	  
+  	// Test
+	initial begin
+  		$dumpfile("Or_tb.vcd");
+  		$dumpvars(0, Or_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Or");
+		
+		a=0;b=0;check();
+		a=0;b=1;check();
+		a=1;b=0;check();
+		a=1;b=1;check();
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/04_Or/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/04_Or/iCE40HX1K.pcf

@@ -0,0 +1,10 @@
+# physical constrain file
+# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB
+# compare to the schematic of the board and the datasheet of fpga
+
+set_io BUT1 41	# BUT1
+set_io BUT2 42	# BUT2
+
+set_io LED1 40	# LED1
+set_io LED2 51	# LED2
+

01_Boolean_Logic/04_Or/top.v

@@ -0,0 +1,11 @@
+`default_nettype none
+module top(
+	input BUT1,
+	input BUT2,
+	output LED1,
+	output LED2
+);
+
+	Or OR(.a(BUT1),.b(BUT2),.out(LED1));
+	
+endmodule

01_Boolean_Logic/05_Xor/Include.v

@@ -0,0 +1,6 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"

01_Boolean_Logic/05_Xor/Xor_tb.gtkw

@@ -0,0 +1,35 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:50:07 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/05_Xor/Xor_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:49:53 2022"
+[dumpfile_size] 987
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/05_Xor/Xor_tb.gtkw"
+[timestart] 0
+[size] 1332 600
+[pos] -1 -1
+*-0.771027 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 100
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@28
+Xor_tb.a
+Xor_tb.b
+@200
+-OUT
+@28
+Xor_tb.out
+@200
+-CMP
+@29
+Xor_tb.out_cmp
+@200
+-Test
+@28
+Xor_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/05_Xor/Xor_tb.v

@@ -0,0 +1,47 @@
+`default_nettype none
+module Xor_tb();
+
+	// IN,OUT
+	reg a,b;
+	wire out;
+
+	// Part
+	Xor XOR(
+		.a(a),
+		.b(b),
+		.out(out)
+	);
+	
+	// Compare
+	wire out_cmp;
+	assign out_cmp = a^b;
+
+	reg fail = 0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: a=%1b, b=%1b, out=%1b",a,b,out);
+				fail = 1;
+			end
+	endtask
+	 
+	// Test 
+  	initial begin
+  		$dumpfile("Xor_tb.vcd");
+  		$dumpvars(0, Xor_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Xor");
+		
+		a=0;b=0;check();
+		a=0;b=1;check();
+		a=1;b=0;check();
+		a=1;b=1;check();
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/05_Xor/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/05_Xor/iCE40HX1K.pcf

@@ -0,0 +1,10 @@
+# physical constrain file
+# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB
+# compare to the schematic of the board and the datasheet of fpga
+
+set_io BUT1 41	# BUT1
+set_io BUT2 42	# BUT2
+
+set_io LED1 40	# LED1
+set_io LED2 51	# LED2
+

01_Boolean_Logic/05_Xor/top.v

@@ -0,0 +1,11 @@
+`default_nettype none
+module top(
+	input BUT1,
+	input BUT2,
+	output LED1,
+	output LED2
+);
+
+	Xor XOR(.a(BUT1),.b(BUT2),.out(LED1));
+	
+endmodule

01_Boolean_Logic/06_Mux/Include.v

@@ -0,0 +1,7 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"

01_Boolean_Logic/06_Mux/Mux_tb.gtkw

@@ -0,0 +1,36 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:49:39 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/06_Mux/Mux_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:49:24 2022"
+[dumpfile_size] 2362
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/06_Mux/Mux_tb.gtkw"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*-1.619024 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 100
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@28
+Mux_tb.a
+Mux_tb.b
+Mux_tb.sel
+@200
+-OUT
+@28
+Mux_tb.out
+@200
+-CMP
+@29
+Mux_tb.out_cmp
+@200
+-Test
+@28
+Mux_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/06_Mux/Mux_tb.v

@@ -0,0 +1,52 @@
+`default_nettype none
+module Mux_tb();
+
+	// IN,OUT
+	reg a,b,sel;
+	wire out;
+
+	// Part
+	Mux MUX(
+		.a(a),
+		.b(b),
+		.sel(sel),
+		.out(out)
+	);
+	
+	// Compare
+	wire out_cmp;
+	assign out_cmp = (sel?b:a);
+	
+	reg fail = 0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: a=%1b, b=%1b, sel=%1b, out=%1b",a,b,sel,out);
+				fail=1;
+			end
+	endtask
+	 
+	// Test 
+  	initial begin
+  		$dumpfile("Mux_tb.vcd");
+  		$dumpvars(0, Mux_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Mux");
+		
+		a=0;b=0;sel=0;check();
+		a=0;b=0;sel=1;check();
+		a=0;b=1;sel=0;check();
+		a=0;b=1;sel=1;check();
+		a=1;b=0;sel=0;check();
+		a=1;b=0;sel=1;check();
+		a=1;b=1;sel=0;check();
+		a=1;b=1;sel=1;check();
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/06_Mux/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/07_DMux/DMux_tb.gtkw

@@ -0,0 +1,37 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:49:10 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/07_DMux/DMux_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:48:46 2022"
+[dumpfile_size] 1611
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/07_DMux/DMux_tb.gtkw"
+[timestart] 0
+[size] 1355 600
+[pos] -1 -1
+*-0.771027 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 80
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@28
+DMux_tb.in
+DMux_tb.sel
+@200
+-OUT
+@28
+DMux_tb.a
+DMux_tb.b
+@200
+-CMP
+@28
+DMux_tb.a_cmp
+DMux_tb.b_cmp
+@200
+-Test
+@29
+DMux_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/07_DMux/DMux_tb.v

@@ -0,0 +1,49 @@
+`default_nettype none
+module DMux_tb();
+
+	// IN,OUT
+	reg in,sel;
+	wire a,b;
+	
+	// Part
+	DMux DMUX(
+		.in(in),
+		.sel(sel),
+		.a(a),
+		.b(b)
+	);
+
+	// Compare
+	wire a_cmp,b_cmp;
+	assign a_cmp = (~sel&in);
+	assign b_cmp = sel∈
+
+	reg fail=0;
+	task check;
+		#1
+		if ((a != a_cmp) || (b != b_cmp)) 
+			begin
+				$display("FAIL: in=%1b, sel=%1b, a=%1b, b=%1b",in,sel,a,b);
+				fail=1;
+			end
+	endtask
+	
+	// Test 
+  	initial begin
+  		$dumpfile("DMux_tb.vcd");
+  		$dumpvars(0, DMux_tb);
+		
+		$display("------------------------");
+		$display("Testbench: DMux");
+		
+		in=0;sel=0;check();
+		in=0;sel=1;check();
+		in=1;sel=0;check();
+		in=1;sel=1;check();
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/07_DMux/Include.v

@@ -0,0 +1,8 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"

01_Boolean_Logic/07_DMux/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/07_DMux/iCE40HX1K.pcf

@@ -0,0 +1,10 @@
+# physical constrain file
+# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB
+# compare to the schematic of the board and the datasheet of fpga
+
+set_io BUT1 41	# BUT1
+set_io BUT2 42	# BUT2
+
+set_io LED1 40	# LED1
+set_io LED2 51	# LED2
+

01_Boolean_Logic/07_DMux/top.v

@@ -0,0 +1,11 @@
+`default_nettype none
+module top(
+	input BUT1,
+	input BUT2,
+	output LED1,
+	output LED2
+);
+
+	DMux DMUX(.in(BUT1),.sel(BUT2),.a(LED1),.b(LED2));
+	
+endmodule

01_Boolean_Logic/08_Not16/Include.v

@@ -0,0 +1,9 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"

01_Boolean_Logic/08_Not16/Not16_tb.gtkw

@@ -0,0 +1,34 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:48:32 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/08_Not16/Not16_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:48:11 2022"
+[dumpfile_size] 1656008
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/08_Not16/Not16_tb.gtkw"
+[timestart] 0
+[size] 1486 562
+[pos] -1 -1
+*-2.107311 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 160
+[sst_expanded] 1
+[sst_vpaned_height] 119
+@200
+-IN
+@22
+Not16_tb.in[0:15]
+@200
+-OUT
+@22
+Not16_tb.out[0:15]
+@200
+-CMP
+@22
+Not16_tb.out_cmp[15:0]
+@201
+-Test
+@28
+Not16_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/08_Not16/Not16_tb.v

@@ -0,0 +1,48 @@
+`default_nettype none
+module Not16_tb();
+
+	// IN,OUT
+	reg [0:15] in;
+	wire [0:15] out;
+
+	// Part
+	Not16 NOT16(
+		.in(in),
+		.out(out)
+	);
+	
+	// Compare
+	wire [15:0] out_cmp;
+	assign out_cmp = ~in;
+
+	reg fail = 0;
+	reg [15:0] n = 0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: a=%16b, out=%16b",in,out);
+				fail=1;
+			end
+	endtask
+	
+	// Test 
+  	initial begin
+  		$dumpfile("Not16_tb.vcd");
+  		$dumpvars(0, Not16_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Not16");
+		
+		for (n=0; n<10000;n=n+1) 
+			begin
+				in=$random;
+				check();
+			end
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/08_Not16/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/09_Buffer16/Buffer16_tb.gtkw

@@ -0,0 +1,34 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Wed Jan  4 11:28:38 2023
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/01_Boolean_Logic/09_Buffer16/Buffer16_tb.vcd"
+[dumpfile_mtime] "Wed Jan  4 11:27:59 2023"
+[dumpfile_size] 3089054
+[savefile] "/home/micha/gitlab/nand2tetris-fpga/01_Boolean_Logic/09_Buffer16/Buffer16_tb.gtkw"
+[timestart] 0
+[size] 1547 481
+[pos] -1 -1
+*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 160
+[sst_expanded] 1
+[sst_vpaned_height] 91
+@200
+-IN
+@23
+Buffer16_tb.in[15:0]
+@200
+-OUT
+@22
+Buffer16_tb.out[15:0]
+@200
+-CMP
+@22
+Buffer16_tb.out_cmp[15:0]
+@200
+-Test
+@28
+Buffer16_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/09_Buffer16/Buffer16_tb.v

@@ -0,0 +1,49 @@
+`default_nettype none
+module Buffer16_tb();
+	
+	// IN,OUT
+	reg [15:0] in;
+	wire [15:0] out;
+
+	// Part
+	Buffer16 BUFFER16(
+		.in(in),
+		.out(out)
+	);
+
+	// Compare
+	wire [15:0] out_cmp;
+	assign out_cmp = in;
+	
+	reg fail = 0;
+	reg [15:0] n = 0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: in=%16b, out=%16b",in,out);
+				fail=1;
+			end
+	endtask
+	  
+  	// Test	
+	initial begin
+  		$dumpfile("Buffer16_tb.vcd");
+  		$dumpvars(0, Buffer16_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Buffer16");
+		
+		for (n=0; n<10000;n=n+1) 
+			begin
+				in=$random;
+				check();
+		
+			end
+			
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/09_Buffer16/Include.v

@@ -0,0 +1,10 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"

01_Boolean_Logic/09_Buffer16/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/10_And16/And16_tb.gtkw

@@ -0,0 +1,35 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:47:53 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/09_And16/And16_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:47:31 2022"
+[dumpfile_size] 2339414
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/09_And16/And16_tb.gtkw"
+[timestart] 5
+[size] 1000 600
+[pos] -1 -1
+*-2.000000 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 160
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@22
+And16_tb.a[15:0]
+And16_tb.b[15:0]
+@200
+-OUT
+@22
+And16_tb.out[15:0]
+@200
+-CMP
+@23
+And16_tb.out_cmp[15:0]
+@200
+-Test
+@28
+And16_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/10_And16/And16_tb.v

@@ -0,0 +1,51 @@
+`default_nettype none
+module And16_tb();
+	
+	// IN,OUT	
+	reg [15:0] a,b;
+	wire [15:0] out;
+
+	// Part
+	And16 AND16(
+		.a(a),
+		.b(b),
+		.out(out)
+	);
+	
+	// Compare
+	wire [15:0] out_cmp;
+	assign out_cmp = a&b;
+
+	reg fail = 0;
+	reg [15:0] n = 0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: a=%16b, b=%16b, out=%16b",a,b,out);
+				fail=1;
+			end
+	endtask
+	  
+	// Test
+  	initial begin
+  		$dumpfile("And16_tb.vcd");
+  		$dumpvars(0, And16_tb);
+		
+		$display("------------------------");
+		$display("Testbench: And16");
+				
+		for (n=0; n<10000;n=n+1) 
+			begin
+				a=$random;
+				b=$random;
+				check();
+		
+			end
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/10_And16/Include.v

@@ -0,0 +1,11 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"

01_Boolean_Logic/10_And16/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/11_Or16/Include.v

@@ -0,0 +1,12 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"

01_Boolean_Logic/11_Or16/Or16_tb.gtkw

@@ -0,0 +1,35 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:47:03 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/10_Or16/Or16_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:46:45 2022"
+[dumpfile_size] 2724821
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/10_Or16/Or16_tb.gtkw"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 160
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@22
+Or16_tb.a[15:0]
+Or16_tb.b[15:0]
+@200
+-OUT
+@22
+Or16_tb.out[15:0]
+@200
+-CMP
+@22
+Or16_tb.out_cmp[15:0]
+@200
+-Test
+@29
+Or16_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/11_Or16/Or16_tb.v

@@ -0,0 +1,50 @@
+`default_nettype none
+module Or16_tb();
+
+	// IN,OUT	
+	reg [15:0] a,b;
+	wire [15:0] out;
+
+	// Part
+	Or16 OR16(
+		.a(a),
+		.b(b),
+		.out(out)
+	);
+
+	// Compare
+	wire [15:0] out_cmp;
+	assign out_cmp = a|b;
+	
+	reg fail = 0;
+	reg [15:0] n = 0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: a=%16b, b=%16b, out=%16b",a,b,out);
+				fail=1;
+			end
+	endtask
+	 
+	// Test
+  	initial begin
+  		$dumpfile("Or16_tb.vcd");
+  		$dumpvars(0, Or16_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Or16");
+				
+		for (n=0; n<10000;n=n+1) 
+			begin
+				a=$random;
+				b=$random;
+				check();
+			end
+	
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/11_Or16/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/12_Mux16/Include.v

@@ -0,0 +1,13 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"

01_Boolean_Logic/12_Mux16/Mux16_tb.gtkw

@@ -0,0 +1,37 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:45:15 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/11_Mux16/Mux16_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:44:57 2022"
+[dumpfile_size] 7849723
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/11_Mux16/Mux16_tb.gtkw"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*0.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 160
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@22
+Mux16_tb.a[15:0]
+Mux16_tb.b[15:0]
+@28
+Mux16_tb.sel
+@200
+-OUT
+@22
+Mux16_tb.out[15:0]
+@200
+-CMP
+@22
+Mux16_tb.out_cmp[15:0]
+@201
+-Test
+@28
+Mux16_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/12_Mux16/Mux16_tb.v

@@ -0,0 +1,53 @@
+`default_nettype none
+module Mux16_tb();
+
+	// IN,OUT
+	reg [15:0] a,b;
+	reg sel;
+	wire [15:0] out;
+
+	// Part
+	Mux16 MUX16(
+		.a(a),
+		.b(b),
+		.sel(sel),
+		.out(out)
+	);
+
+	// Compare
+	wire [15:0] out_cmp;
+	assign out_cmp = sel?b:a;
+	
+	reg fail = 0;
+	reg [15:0] n = 0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: a=%16b, b=%16b, sel=%1b, out=%16b",a,b,sel,out);
+				fail=1;
+			end
+	endtask
+	
+	// Test 
+  	initial begin
+  		$dumpfile("Mux16_tb.vcd");
+  		$dumpvars(0, Mux16_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Mux16");
+		
+		for (n=0; n<10000;n=n+1) 
+			begin
+				a=$random;
+				b=$random;
+				sel=0;check();
+				sel=1;check();
+			end
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/12_Mux16/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/13_Or8Way/Include.v

@@ -0,0 +1,14 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"

01_Boolean_Logic/13_Or8Way/Or8Way_tb.gtkw

@@ -0,0 +1,34 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:44:04 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/12_Or8Way/Or8Way_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:43:43 2022"
+[dumpfile_size] 792009
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/12_Or8Way/Or8Way_tb.gtkw"
+[timestart] 0
+[size] 1920 963
+[pos] -1 -1
+*-2.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 100
+[sst_expanded] 1
+[sst_vpaned_height] 259
+@200
+-IN
+@22
+Or8Way_tb.in[7:0]
+@200
+-OUT
+@28
+Or8Way_tb.out
+@200
+-CMP
+@28
+Or8Way_tb.out_cmp
+@201
+-Test
+@28
+Or8Way_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/13_Or8Way/Or8Way_tb.v

@@ -0,0 +1,50 @@
+`default_nettype none
+module Or8Way_tb();
+	
+	// IN,OUT
+	reg [7:0] in;
+	wire out;
+
+	// Part
+	Or8Way OR8WAY(
+		.in(in),
+		.out(out)
+	);
+
+	// Compare
+	wire out_cmp;
+	assign out_cmp = |in;
+
+	reg fail = 0;
+	reg [15:0] n=0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: in=%8b, out=%1b",in,out);
+				fail=1;
+			end
+	endtask
+	
+	// Test 
+  	initial begin
+  		$dumpfile("Or8Way_tb.vcd");
+  		$dumpvars(0, Or8Way_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Or8Way");
+
+		in=0;
+		check();				
+		for (n=0; n<10000;n=n+1) 
+			begin
+				in=$random;
+				check();
+			end
+	
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/13_Or8Way/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/14_Mux4Way16/Include.v

@@ -0,0 +1,15 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+`include "../../01_Boolean_Logic/Mux4Way16.v"

01_Boolean_Logic/14_Mux4Way16/Mux4Way16_tb.gtkw

@@ -0,0 +1,40 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:42:01 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/13_Mux4Way16/Mux4Way16_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:41:40 2022"
+[dumpfile_size] 4764720
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/13_Mux4Way16/Mux4Way16_tb.gtkw"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*0.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] Mux4Way16_tb.
+[sst_width] 281
+[signals_width] 160
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@22
+Mux4Way16_tb.a[15:0]
+Mux4Way16_tb.b[15:0]
+Mux4Way16_tb.c[15:0]
+Mux4Way16_tb.d[15:0]
+@28
+Mux4Way16_tb.sel[1:0]
+@200
+-OUT
+@22
+Mux4Way16_tb.out[15:0]
+@200
+-CMP
+@22
+Mux4Way16_tb.out_cmp[15:0]
+@201
+-Test
+@28
+Mux4Way16_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/14_Mux4Way16/Mux4Way16_tb.v

@@ -0,0 +1,59 @@
+`default_nettype none
+module Mux4Way16_tb();
+
+	// IN,OUT
+	reg [15:0] a,b,c,d;
+	reg [1:0] sel;
+	wire [15:0] out;
+	
+	// Part
+	Mux4Way16 MUX4WAY16(
+		.a(a),
+		.b(b),
+		.c(c),
+		.d(d),
+		.sel(sel),
+		.out(out)
+	);
+
+	// Compare
+	wire [15:0] out_cmp;
+	assign out_cmp = (sel[1]? (sel[0]?d:c):(sel[0]?b:a));
+	
+	reg fail = 0;
+	reg [15:0] n = 0;
+	task check;
+		#1
+			if (out != out_cmp)
+			begin
+				$display("FAIL: a=%16b, b=%16b, c=%16b, d=%16b, sel=%2b, out=%16b",a,b,c,d,sel,out);
+				fail=1;
+			end
+	endtask
+	 
+	// Test 
+  	initial begin
+  		$dumpfile("Mux4Way16_tb.vcd");
+  		$dumpvars(0, Mux4Way16_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Mux4Way16");
+		
+		for (n=0; n<1000;n=n+1) 
+			begin
+				a=$random;
+				b=$random;
+				c=$random;
+				d=$random;
+				sel=0;check();
+				sel=1;check();
+				sel=2;check();
+				sel=3;check();
+			end
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/14_Mux4Way16/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/15_Mux8Way16/Include.v

@@ -0,0 +1,16 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+`include "../../01_Boolean_Logic/Mux4Way16.v"
+`include "../../01_Boolean_Logic/Mux8Way16.v"

01_Boolean_Logic/15_Mux8Way16/Mux8Way16_tb.gtkw

@@ -0,0 +1,43 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:41:14 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/14_Mux8Way16/Mux8Way16_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:40:51 2022"
+[dumpfile_size] 2373256
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/14_Mux8Way16/Mux8Way16_tb.gtkw"
+[timestart] 0
+[size] 1920 963
+[pos] -1 -1
+*0.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 160
+[sst_expanded] 1
+[sst_vpaned_height] 259
+@200
+-IN
+@22
+Mux8Way16_tb.a[15:0]
+Mux8Way16_tb.b[15:0]
+Mux8Way16_tb.c[15:0]
+Mux8Way16_tb.d[15:0]
+Mux8Way16_tb.e[15:0]
+Mux8Way16_tb.f[15:0]
+Mux8Way16_tb.g[15:0]
+Mux8Way16_tb.h[15:0]
+@28
+Mux8Way16_tb.sel[2:0]
+@200
+-OUT
+@22
+Mux8Way16_tb.out[15:0]
+@200
+-CMP
+@22
+Mux8Way16_tb.out_cmp[15:0]
+@201
+-Test
+@28
+Mux8Way16_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/15_Mux8Way16/Mux8Way16_tb.v

@@ -0,0 +1,71 @@
+`default_nettype none
+module Mux8Way16_tb();
+
+	// IN,OUT
+	reg [15:0] a,b,c,d,e,f,g,h;
+	reg [2:0] sel;
+	wire [15:0] out;
+
+	// PART
+	Mux8Way16 MUX8WAY16(
+		.a(a),
+		.b(b),
+		.c(c),
+		.d(d),
+		.e(e),
+		.f(f),
+		.g(g),
+		.h(h),
+		.sel(sel),
+		.out(out)
+	);
+	
+	// Compare
+	wire [15:0] out_cmp;
+	assign out_cmp = (sel[2]?(sel[1]? (sel[0]?h:g):(sel[0]?f:e)):
+							 (sel[1]? (sel[0]?d:c):(sel[0]?b:a)));
+
+	reg fail = 0;
+	reg [15:0] n = 0;
+	task check;
+		#1
+		if (out != out_cmp)
+			begin
+				$display("FAIL: a=%16b, b=%16b, c=%16b, d=%16b, e=%16b, f=%16b, g=%16b, h=%16b, sel=%3b, out=%16b",a,b,c,d,e,f,g,h,sel,out);
+				fail=1;
+			end
+	endtask
+	  
+  	initial begin
+  		$dumpfile("Mux8Way16_tb.vcd");
+  		$dumpvars(0, Mux8Way16_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Mux8Way16");
+		
+		for (n=0; n<100;n=n+1) 
+			begin
+				a=$random;
+				b=$random;
+				c=$random;
+				d=$random;
+				e=$random;
+				f=$random;
+				g=$random;
+				h=$random;
+				sel=0;check();
+				sel=1;check();
+				sel=2;check();
+				sel=3;check();
+				sel=4;check();
+				sel=5;check();
+				sel=6;check();
+				sel=7;check();
+			end
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/15_Mux8Way16/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/16_DMux4Way/DMux4Way_tb.gtkw

@@ -0,0 +1,43 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:40:27 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/15_DMux4Way/DMux4Way_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:39:53 2022"
+[dumpfile_size] 4551
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/15_DMux4Way/DMux4Way_tb.gtkw"
+[timestart] 0
+[size] 1920 963
+[pos] -1 -1
+*-1.619024 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 110
+[sst_expanded] 1
+[sst_vpaned_height] 258
+@200
+-IN
+@28
+DMux4Way_tb.in
+DMux4Way_tb.sel[1:0]
+@200
+-OUT
+@28
+DMux4Way_tb.a
+DMux4Way_tb.b
+DMux4Way_tb.c
+DMux4Way_tb.d
+@200
+-CMP
+@28
+DMux4Way_tb.a_cmp
+@29
+DMux4Way_tb.b_cmp
+@28
+DMux4Way_tb.c_cmp
+DMux4Way_tb.d_cmp
+@200
+-Test
+@28
+DMux4Way_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/16_DMux4Way/DMux4Way_tb.v

@@ -0,0 +1,57 @@
+`default_nettype none
+module DMux4Way_tb();
+
+	// IN,OUT
+	reg in;
+	reg [1:0] sel;
+	wire a,b,c,d;
+	
+	// Part
+	DMux4Way DMUX4WAY(
+		.in(in),
+		.sel(sel),
+		.a(a),
+		.b(b),
+		.c(c),
+		.d(d)
+	);
+
+	// Compare
+	wire a_cmp,b_cmp,c_cmp,d_cmp;
+	assign a_cmp = (sel==0)?in:0;
+	assign b_cmp = (sel==1)?in:0;
+	assign c_cmp = (sel==2)?in:0;
+	assign d_cmp = (sel==3)?in:0;
+
+	reg fail = 0;
+	task check;
+		#1
+		if ((a != a_cmp) || (b != b_cmp) || (c != c_cmp) || (d != d_cmp)) 
+			begin
+				$display("FAIL: in=%1b, sel=%1b, a=%1b, b=%1b, c=%1b, d=%1b",in,sel,a,b,c,d);
+				fail=1;
+			end
+	endtask
+	  
+  	initial begin
+  		$dumpfile("DMux4Way_tb.vcd");
+  		$dumpvars(0, DMux4Way_tb);
+		
+		$display("------------------------");
+		$display("Testbench: DMux4Way");
+		
+		in=0;sel=0;check();
+		in=0;sel=1;check();
+		in=0;sel=2;check();
+		in=0;sel=3;check();
+		in=1;sel=0;check();
+		in=1;sel=1;check();
+		in=1;sel=2;check();
+		in=1;sel=3;check();
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/16_DMux4Way/Include.v

@@ -0,0 +1,17 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+`include "../../01_Boolean_Logic/Mux4Way16.v"
+`include "../../01_Boolean_Logic/Mux8Way16.v"
+`include "../../01_Boolean_Logic/DMux4Way.v"

01_Boolean_Logic/16_DMux4Way/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/17_DMux8Way/DMux8Way_tb.gtkw

@@ -0,0 +1,49 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:39:25 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/16_DMux8Way/DMux8Way_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:38:18 2022"
+[dumpfile_size] 10742
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/16_DMux8Way/DMux8Way_tb.gtkw"
+[timestart] 0
+[size] 1669 793
+[pos] -1 -1
+*-1.619024 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 110
+[sst_expanded] 1
+[sst_vpaned_height] 197
+@200
+-IN
+@28
+DMux8Way_tb.in
+DMux8Way_tb.sel[2:0]
+@200
+-OUT
+@28
+DMux8Way_tb.a
+DMux8Way_tb.b
+DMux8Way_tb.c
+DMux8Way_tb.d
+DMux8Way_tb.e
+DMux8Way_tb.f
+DMux8Way_tb.g
+DMux8Way_tb.h
+@200
+-CMP
+@28
+DMux8Way_tb.a_cmp
+DMux8Way_tb.b_cmp
+DMux8Way_tb.c_cmp
+DMux8Way_tb.d_cmp
+DMux8Way_tb.e_cmp
+DMux8Way_tb.f_cmp
+DMux8Way_tb.g_cmp
+DMux8Way_tb.h_cmp
+@201
+-Test
+@28
+DMux8Way_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/17_DMux8Way/DMux8Way_tb.v

@@ -0,0 +1,74 @@
+`default_nettype none
+module DMux8Way_tb();
+
+	// IN,OUT
+	reg in;
+	reg [2:0] sel;
+	wire a,b,c,d,e,f,g,h;
+	
+	// Part
+	DMux8Way DMUX8WAY(
+		.in(in),
+		.sel(sel),
+		.a(a),
+		.b(b),
+		.c(c),
+		.d(d),
+		.e(e),
+		.f(f),
+		.g(g),
+		.h(h)
+	);
+	
+	// Compare
+	wire a_cmp,b_cmp,c_cmp,d_cmp,e_cmp,f_cmp,g_cmp,h_cmp;
+	assign a_cmp = (sel==0)?in:0;
+	assign b_cmp = (sel==1)?in:0;
+	assign c_cmp = (sel==2)?in:0;
+	assign d_cmp = (sel==3)?in:0;
+	assign e_cmp = (sel==4)?in:0;
+	assign f_cmp = (sel==5)?in:0;
+	assign g_cmp = (sel==6)?in:0;
+	assign h_cmp = (sel==7)?in:0;
+ 
+	reg fail = 0;
+	task check;
+		#1
+		if ((a!=a_cmp)||(b!=b_cmp)||(c!=c_cmp)||(d!=d_cmp)||(e!=e_cmp)||(f!=f_cmp)||(g!=g_cmp)||(h!=h_cmp))
+			begin
+				$display("FAIL: in=%1b, sel=%2b, a=%1b, b=%1b, c=%1b, d=%1b, e=%1b, f=%1b, g=%1b, h=%1b",in,sel,a,b,c,d,e,f,g,h);
+				fail=1;
+			end
+	endtask
+
+	// Test 
+  	initial begin
+  		$dumpfile("DMux8Way_tb.vcd");
+  		$dumpvars(0, DMux8Way_tb);
+		
+		$display("------------------------");
+		$display("Testbench: DMux8Way");
+		
+		in=0;sel=0;check();
+		in=0;sel=1;check();
+		in=0;sel=2;check();
+		in=0;sel=3;check();
+		in=0;sel=4;check();
+		in=0;sel=5;check();
+		in=0;sel=6;check();
+		in=0;sel=7;check();
+		in=1;sel=0;check();
+		in=1;sel=1;check();
+		in=1;sel=2;check();
+		in=1;sel=3;check();
+		in=1;sel=4;check();
+		in=1;sel=5;check();
+		in=1;sel=6;check();
+		in=1;sel=7;check();
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/17_DMux8Way/Include.v

@@ -0,0 +1,18 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+`include "../../01_Boolean_Logic/Mux4Way16.v"
+`include "../../01_Boolean_Logic/Mux8Way16.v"
+`include "../../01_Boolean_Logic/DMux4Way.v"
+`include "../../01_Boolean_Logic/DMux8Way.v"

01_Boolean_Logic/17_DMux8Way/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/And.v

@@ -0,0 +1,16 @@
+/**
+ * And gate: 
+ * out = 1 if (a == 1 and b == 1)
+ *       0 otherwise
+ */
+
+`default_nettype none
+module And(
+	input a,
+	input b,
+	output out
+);
+
+	// Put your code here:
+
+endmodule

01_Boolean_Logic/And16.v

@@ -0,0 +1,15 @@
+/**
+ * 16-bit bitwise And:
+ * for i = 0..15: out[i] = (a[i] and b[i])
+ */
+
+`default_nettype none
+module And16(
+	input [15:0] a,
+	input [15:0] b,
+	output [15:0] out
+);
+
+	// Put your code here:
+
+endmodule

01_Boolean_Logic/Buffer.v

@@ -0,0 +1,14 @@
+/**
+ * Buffer:
+ * out = in
+ */
+
+`default_nettype none
+module Buffer(
+	input in,
+	output out
+);
+
+	// Put your code here:
+
+endmodule

01_Boolean_Logic/Buffer16.v

@@ -0,0 +1,14 @@
+/**
+ * 16-bit bitwise Buffer:
+ * for i = 0..15: out[i] = in[i]
+ */
+
+`default_nettype none
+module Buffer16(
+	input [15:0] in,
+	output [15:0] out
+);
+
+	// Put your code here:
+
+endmodule

01_Boolean_Logic/DMux.v

@@ -0,0 +1,17 @@
+/**
+ * Demultiplexor:
+ * {a, b} = {in, 0} if sel == 0
+ *          {0, in} if sel == 1
+ */
+
+`default_nettype none
+module DMux(
+	input in,
+	input sel,
+    output a,
+	output b
+);
+
+	// Put your code here:
+
+endmodule

01_Boolean_Logic/DMux4Way.v

@@ -0,0 +1,21 @@
+/**
+ * 4-way demultiplexor:
+ * {a, b, c, d} = {in, 0, 0, 0} if sel == 00
+ *                {0, in, 0, 0} if sel == 01
+ *                {0, 0, in, 0} if sel == 10
+ *                {0, 0, 0, in} if sel == 11
+ */
+
+`default_nettype none
+module DMux4Way(
+	input in,
+	input [1:0] sel,
+    output a,
+	output b,
+	output c,
+	output d
+);
+	
+	// Put your code here:	
+
+endmodule

01_Boolean_Logic/DMux8Way.v

@@ -0,0 +1,25 @@
+/**
+ * 8-way demultiplexor:
+ * {a, b, c, d, e, f, g, h} = {in, 0, 0, 0, 0, 0, 0, 0} if sel == 000
+ *                            {0, in, 0, 0, 0, 0, 0, 0} if sel == 001
+ *                            etc.
+ *                            {0, 0, 0, 0, 0, 0, 0, in} if sel == 111
+ */
+
+`default_nettype none
+module DMux8Way(
+	input in,
+	input [2:0] sel,
+    output a,
+	output b,
+	output c,
+	output d,
+	output e,
+	output f,
+	output g,
+	output h
+);
+
+	// Put your code here:
+
+endmodule

01_Boolean_Logic/Mux.v

@@ -0,0 +1,17 @@
+/** 
+ * Multiplexor:
+ * out = a if sel == 0
+ *       b otherwise
+ */
+
+`default_nettype none
+module Mux(
+	input a,
+	input b,
+	input sel,
+	output out
+);
+
+	// Put your code here:
+
+endmodule

01_Boolean_Logic/Mux16.v

@@ -0,0 +1,17 @@
+/**
+ * 16-bit multiplexor: 
+ * for i = 0..15 out[i] = a[i] if sel == 0 
+ *                        b[i] if sel == 1
+ */
+
+`default_nettype none
+module Mux16(
+	input [15:0] a,
+	input [15:0] b,
+   	input sel,
+	output [15:0] out
+);
+
+	// Put your code here:
+
+endmodule

01_Boolean_Logic/Mux4Way16.v

@@ -0,0 +1,19 @@
+/**
+ * 16-bit multiplexor: 
+ * for i = 0..15 out[i] = a[i] if sel == 0 
+ *                        b[i] if sel == 1
+ */
+
+`default_nettype none
+module Mux4Way16(
+	input [15:0] a,
+	input [15:0] b,
+	input [15:0] c,
+	input [15:0] d,
+   	input [1:0] sel,
+	output [15:0] out
+);
+	
+	// Put your code here:
+
+endmodule

01_Boolean_Logic/Mux8Way16.v

@@ -0,0 +1,23 @@
+/**
+ * 16-bit multiplexor: 
+ * for i = 0..15 out[i] = a[i] if sel == 0 
+ *                        b[i] if sel == 1
+ */
+
+`default_nettype none
+module Mux8Way16(
+	input [15:0] a,
+	input [15:0] b,
+	input [15:0] c,
+	input [15:0] d,
+	input [15:0] e,
+	input [15:0] f,
+	input [15:0] g,
+	input [15:0] h,
+   	input [2:0] sel,
+	output [15:0] out
+);
+
+	// Put your code here:
+
+endmodule

01_Boolean_Logic/Nand.v

@@ -0,0 +1,18 @@
+/**
+ * Nand gate: 
+ * out = 0 if (a == 1 and b == 1)
+ *       1 otherwise
+ */
+
+`default_nettype none
+module Nand(
+	input a,
+	input b,
+	output out
+);
+
+	// No need to implement this chip
+	// This chip is implemented using verilog primitives
+	nand(out,a,b);
+
+endmodule

01_Boolean_Logic/Not.v

@@ -0,0 +1,14 @@
+/**
+ * Not gate:
+ * out = not in
+ */
+
+`default_nettype none
+module Not(
+	input in,
+	output out
+);
+
+	// Put your code here:
+
+endmodule