18 lines
187 B
Verilog
18 lines
187 B
Verilog
/**
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* Multiplexor:
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* out = a if sel == 0
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* b otherwise
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*/
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`default_nettype none
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module Mux(
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input a,
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input b,
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input sel,
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output out
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);
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// Put your code here:
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endmodule
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