17 lines
183 B
Verilog
17 lines
183 B
Verilog
/**
|
|
* And gate:
|
|
* out = 1 if (a == 1 and b == 1)
|
|
* 0 otherwise
|
|
*/
|
|
|
|
`default_nettype none
|
|
module And(
|
|
input a,
|
|
input b,
|
|
output out
|
|
);
|
|
|
|
// Put your code here:
|
|
|
|
endmodule
|