diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..f241cb1 --- /dev/null +++ b/.gitignore @@ -0,0 +1,12 @@ +*~ +*.asc +*.json +*.bin +*.out +*.vcd +*.dblite +*.hack +*.vm +out.asm +out.hack +.* diff --git a/00_Requirement/BOM.png b/00_Requirement/BOM.png new file mode 100644 index 0000000..9a2ed07 Binary files /dev/null and b/00_Requirement/BOM.png differ diff --git a/00_Requirement/ICE40PGM.jpg b/00_Requirement/ICE40PGM.jpg new file mode 100644 index 0000000..816a283 Binary files /dev/null and b/00_Requirement/ICE40PGM.jpg differ diff --git a/00_Requirement/Readme.md b/00_Requirement/Readme.md new file mode 100644 index 0000000..c0e8706 --- /dev/null +++ b/00_Requirement/Readme.md @@ -0,0 +1,110 @@ +## 00 Requirement + +### FPGA-Board + +In this project we will implement the HACK computer of the nand2tetris course in real hardware. This is done with a development board featuring a so called field programmable array (FPGA). The fpga chip is a small piece of silicon holding lots of logic cells (LC) and block ram (BRAM), which can be routed programmatically. + +In this tutorial we use the FPGA-board iCE40HX1K-EVB from Olimex Ltd., which has the nice property of being completely open source. The whole project uses only FOSS free and open source hard- and software, so everybody can build their own HACK following this instructions. + +![](fpga.png) + +On iCE40HX1K-EVB board you will find: + +* FPGA-chip iCE40HX1K: holds 1280 logic cells and 64Kbits block ram, which can be routed programmatically +* Serial flash memory W25Q16BV (16MBit): holds the bitstream data, which is a binary representation of the circuits, you want to implement on the FPGA. At startup the FPGA loads the bitstream from serial flash memory and configures its logic cells to become the machine you want the FPGA to be. +* LED, BUT: The development board come with two leds and two buttons. This are user programmable and can be used to enter data or for debugging. +* SRAM (256k x 16 bit): iCE40HX1K-EVB has a static RAM chip on board. This is usefull, because more memory is needed than available with blockram inside FPGA. We will use the SRAM chip as instruction memory ROM to run serious application like tetris or pong on on HACK. +* GPIO1 34 pin connector: the board come with a lot of general purpose in-/output pins. This pins can be used to connect external hardware. We will use this pins to connect an LCD screen with Touchpanel MOD-LCD2.8RTP. + +To communicate to the iCE40HX1K-EVB we need an arduino like board, which can be connected to iCE40HX1K over the 10 pin UEXT connector . We will use Olimexino 32u4 board, wich has two modes: + +* programmer: used to upload the bitstream file to serial flash memory. +* UART bridge: used to communicate to HACK at runtime. + +### Tools + +The chips of our HACK computer (ALU, CPU, Register, Memory, IO-Devices) are implemented in verilog, an industrial standard hardware description language similar to HDL from nand2tetris. So we need tools to translate Verilog-code to the so called bitstream, which is a binary representation of all the wires between the logic cells we want to activate. Finally we need tools to upload the bitstream file to the fpga board. + +We will use iCE40-FPGA from Lattice Semiconductors, because they have the nice property that there exists a complete free and open source toolchain [Project Icestorm](http://www.clifford.at/icestorm/) for programming: + +* YoSYS: Syntesize the verilog code +* nextpnr: place and route tool +* iceprogduino: programmer +* gtkwave: tool to simulate and visualize signals in fpga circuits + +![](toolchain.png) + +To run HACK we also need some software written for HACK. The simpler projects like a blinking LED can be programmed direcly in Assembler. Harder tasks like the driver for the LCD-screen are programmed in Jack, translated for the virtual machine and finally compiled to HACK code. + +*** + +## Get started + +### Buy the hardware ... + +To build projects 1-5 any FPGA board will work. If you want to run serious application like Pong or Tetris on top of the Jack-OS you need an FPGA-board with more memory and connect to I/O-Devices like a screen and a touchpanel. The project has been tested with the following devices: + +* iCE40 Board: [iCE40HX1K-EVB](https://www.olimex.com/Products/FPGA/iCE40/) +* Programmer: [Olimexino-32u4](https://www.olimex.com/Products/Duino/AVR/OLIMEXINO-32U4/open-source-hardware) +* 2.8 Inch LCD color screen with resistive touch panel: [MOD-LCD2.8RTP](https://www.olimex.com/Products/Modules/LCD/MOD-LCD2-8RTP) + +Check the bill of material and consider to buy at Olimex Ltd., the company with the highest number of registered OSHW-projects. + +![](BOM.png) + +## ... install the tools ... + +### apio + +Apio (pronounced [ˈa.pjo]) is a multiplatform toolbox, with static pre-built packages, project configuration tools and easy command interface to verify, synthesize, simulate and upload your verilog designs. + + Visit [apio](https://github.com/FPGAwars/apio) and follow the install instruction. This will automatically install the whole toolchain consisting of: + +* iCE40 tools: [Project Icestorm](http://www.clifford.at/icestorm/) +* Signal visualizer: [gtkwave](http://gtkwave.sourceforge.net/) + +``` +$ pip install -U apio +``` + + To learn usage of apio do the example projects provided by apio. + +``` +$ apio install oss-cad-suite +$ apio install gtkwave +$ apio install examples +$ apio examples -d iCE40-HX1K-EVB/leds +$ cd iCE40-HX1K-EVB/leds +$ apio sim +$ apio build +$ apio upload +``` + +### programmer Olimexino-32u4 + +If you go with Olimex boards you additionally have to install the programmer software [iceprogduino](https://github.com/OLIMEX/iCE40HX1K-EVB/tree/master/programmer/olimexino-32u4%20firmware). The firmware has to be flashed on olimexino-32u4 with the Arduino development platform. Additionally you have to install the programm iceprogduino on your computer: + +``` +$ git clone https://github.com/OLIMEX/iCE40HX1K-EVB.git +$ cd iCE40HX1K-EVB/programmer/iceprogduino +$ make +$ sudo make install +``` + +Test the programmer with the test project provided by Olimex. + +**Tipp:** Connect the solder jumper 3.3V_E1 on iCE40HX1K-EVB to power the fpga board iCE40HX1K-EVB over the IDC10 cable connected to Olimexino 32u4 over UEXT. This supersedes the need of the external 3.3V DC power supply. + + ![](ICE40PGM.jpg) + +![](jumper3V.png) + +### JACK-HACK-tools + +JACK-HACK-Tools: JackCompiler, VirtualMachine Translator and Assembler vor Hack should be developed by yourself. Follow guidelines at [nand2tetris](https://www.nand2tetris.org/). If you don't have your own JACK-HACK-tools yet, you can use the compiled python version the JACK-HACK-toolchain provided in the folder [tools](../tools). + +### ... and do some verilog examples + +There is no need to learn much verilog. Just dig into the example `Xor` and learn how to "translate" your HDL-files from nand2tetris into verilog. + +If you like to have some verilog-background I recommend to do the tutorial of Juan González-Gomez (Obijuan), which starts at absolute beginners level [open-fpga-verilog-tutorial](https://github.com/Obijuan/open-fpga-verilog-tutorial/), best tutorial! diff --git a/00_Requirement/fpga.dia b/00_Requirement/fpga.dia new file mode 100644 index 0000000..3c3fcec Binary files /dev/null and b/00_Requirement/fpga.dia differ diff --git a/00_Requirement/fpga.png b/00_Requirement/fpga.png new file mode 100644 index 0000000..5c46965 Binary files /dev/null and b/00_Requirement/fpga.png differ diff --git a/00_Requirement/jumper3V.png b/00_Requirement/jumper3V.png new file mode 100644 index 0000000..01d6d1c Binary files /dev/null and b/00_Requirement/jumper3V.png differ diff --git a/00_Requirement/toolchain.dia b/00_Requirement/toolchain.dia new file mode 100644 index 0000000..ff2d41f Binary files /dev/null and b/00_Requirement/toolchain.dia differ diff --git a/00_Requirement/toolchain.png b/00_Requirement/toolchain.png new file mode 100644 index 0000000..7fdae0a Binary files /dev/null and b/00_Requirement/toolchain.png differ diff --git a/01_Boolean_Logic/00_Nand/Include.v b/01_Boolean_Logic/00_Nand/Include.v new file mode 100644 index 0000000..7f7e1a5 --- /dev/null +++ b/01_Boolean_Logic/00_Nand/Include.v @@ -0,0 +1 @@ +`include "../../01_Boolean_Logic/Nand.v" diff --git a/01_Boolean_Logic/00_Nand/Nand_tb.gtkw b/01_Boolean_Logic/00_Nand/Nand_tb.gtkw new file mode 100644 index 0000000..597e049 --- /dev/null +++ b/01_Boolean_Logic/00_Nand/Nand_tb.gtkw @@ -0,0 +1,32 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:24:30 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/00_Nand/Nand_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:23:51 2022" +[dumpfile_size] 466 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/00_Nand/Nand_tb.gtkw" +[timestart] 0 +[size] 1348 589 +[pos] -1 -1 +*-0.771027 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 100 +[sst_expanded] 1 +[sst_vpaned_height] 129 +@200 +-IN +@28 +Nand_tb.a +Nand_tb.b +@200 +-OUT +@28 +Nand_tb.out +@200 +-CMP +@28 +Nand_tb.out_cmp +Nand_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/00_Nand/Nand_tb.v b/01_Boolean_Logic/00_Nand/Nand_tb.v new file mode 100644 index 0000000..281d8c3 --- /dev/null +++ b/01_Boolean_Logic/00_Nand/Nand_tb.v @@ -0,0 +1,47 @@ +`default_nettype none +module Nand_tb(); + + // IN,OUT + reg a,b; + wire out; + + // Part + Nand NAND( + .a(a), + .b(b), + .out(out) + ); + + // Compare + wire out_cmp; + assign out_cmp = ~(a&b); + + reg fail = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: a=%1b, b=%1b, out=%1b",a,b,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("Nand_tb.vcd"); + $dumpvars(0, Nand_tb); + + $display("------------------------"); + $display("Testbench: Nand"); + + a=0;b=0;check(); + a=0;b=1;check(); + a=1;b=0;check(); + a=1;b=1;check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/00_Nand/apio.ini b/01_Boolean_Logic/00_Nand/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/00_Nand/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/00_Nand/iCE40HX1K.pcf b/01_Boolean_Logic/00_Nand/iCE40HX1K.pcf new file mode 100644 index 0000000..bd6b479 --- /dev/null +++ b/01_Boolean_Logic/00_Nand/iCE40HX1K.pcf @@ -0,0 +1,10 @@ +# physical constrain file +# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB +# compare to the schematic of the board and the datasheet of fpga + +set_io BUT1 41 # BUT1 +set_io BUT2 42 # BUT2 + +set_io LED1 40 # LED1 +set_io LED2 51 # LED2 + diff --git a/01_Boolean_Logic/00_Nand/top.v b/01_Boolean_Logic/00_Nand/top.v new file mode 100644 index 0000000..9602cc1 --- /dev/null +++ b/01_Boolean_Logic/00_Nand/top.v @@ -0,0 +1,11 @@ +`default_nettype none +module top( + input BUT1, + input BUT2, + output LED1, + output LED2 +); + + Nand NAND(.a(BUT1),.b(BUT2),.out(LED1)); + +endmodule diff --git a/01_Boolean_Logic/01_Not/Include.v b/01_Boolean_Logic/01_Not/Include.v new file mode 100644 index 0000000..aff9700 --- /dev/null +++ b/01_Boolean_Logic/01_Not/Include.v @@ -0,0 +1,2 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" diff --git a/01_Boolean_Logic/01_Not/Not_tb.gtkw b/01_Boolean_Logic/01_Not/Not_tb.gtkw new file mode 100644 index 0000000..9a4a993 --- /dev/null +++ b/01_Boolean_Logic/01_Not/Not_tb.gtkw @@ -0,0 +1,32 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:25:30 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/01_Not/Not_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:25:02 2022" +[dumpfile_size] 404 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/01_Not/Not_tb.gtkw" +[timestart] 0 +[size] 1000 600 +[pos] -1 -1 +*-0.034062 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 100 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@200 +-IN +@28 +Not_tb.in +@200 +-OUT +@28 +Not_tb.out +@200 +-Test +@29 +Not_tb.out_cmp +@28 +Not_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/01_Not/Not_tb.v b/01_Boolean_Logic/01_Not/Not_tb.v new file mode 100644 index 0000000..a04e5e0 --- /dev/null +++ b/01_Boolean_Logic/01_Not/Not_tb.v @@ -0,0 +1,44 @@ +`default_nettype none +module Not_tb(); + + // IN,OUT + reg in; + wire out; + + // Part + Not NOT( + .in(in), + .out(out) + ); + + // Compare + wire out_cmp; + assign out_cmp = ~in; + + reg fail = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: in=%1b, out=%1b",in,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("Not_tb.vcd"); + $dumpvars(0, Not_tb); + + $display("------------------------"); + $display("Testbench: Not"); + + in=0;check(); + in=1;check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/01_Not/apio.ini b/01_Boolean_Logic/01_Not/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/01_Not/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/01_Not/iCE40HX1K.pcf b/01_Boolean_Logic/01_Not/iCE40HX1K.pcf new file mode 100644 index 0000000..bd6b479 --- /dev/null +++ b/01_Boolean_Logic/01_Not/iCE40HX1K.pcf @@ -0,0 +1,10 @@ +# physical constrain file +# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB +# compare to the schematic of the board and the datasheet of fpga + +set_io BUT1 41 # BUT1 +set_io BUT2 42 # BUT2 + +set_io LED1 40 # LED1 +set_io LED2 51 # LED2 + diff --git a/01_Boolean_Logic/01_Not/top.v b/01_Boolean_Logic/01_Not/top.v new file mode 100644 index 0000000..c0d50f2 --- /dev/null +++ b/01_Boolean_Logic/01_Not/top.v @@ -0,0 +1,12 @@ +`default_nettype none +module top( + input BUT1, + input BUT2, + output LED1, + output LED2 +); + + Not NOT1(.in(BUT1),.out(LED1)); + Not NOT2(.in(BUT2),.out(LED2)); + +endmodule diff --git a/01_Boolean_Logic/02_Buffer/Buffer_tb.gtkw b/01_Boolean_Logic/02_Buffer/Buffer_tb.gtkw new file mode 100644 index 0000000..5107420 --- /dev/null +++ b/01_Boolean_Logic/02_Buffer/Buffer_tb.gtkw @@ -0,0 +1,31 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Fri Nov 25 09:50:44 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/0_Buffer/Buffer_tb.vcd" +[dumpfile_mtime] "Fri Nov 25 09:50:10 2022" +[dumpfile_size] 413 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/0_Buffer/Buffer_tb.gtkw" +[timestart] 0 +[size] 1000 600 +[pos] -1 -1 +*-0.034062 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 100 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@201 +-IN +@28 +Buffer_tb.in +@200 +-OUT +@28 +Buffer_tb.out +@200 +-CMP +@28 +Buffer_tb.out_cmp +Buffer_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/02_Buffer/Buffer_tb.v b/01_Boolean_Logic/02_Buffer/Buffer_tb.v new file mode 100644 index 0000000..79eacd0 --- /dev/null +++ b/01_Boolean_Logic/02_Buffer/Buffer_tb.v @@ -0,0 +1,44 @@ +`default_nettype none +module Buffer_tb(); + + // IN,OUT + reg in; + wire out; + + // Part + Buffer BUFFER( + .in(in), + .out(out) + ); + + // Compare + wire out_cmp; + assign out_cmp = in; + + reg fail = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: in=%1b, out=%1b",in,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("Buffer_tb.vcd"); + $dumpvars(0, Buffer_tb); + + $display("------------------------"); + $display("Testbench: Buffer"); + + in=0;check(); + in=1;check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/02_Buffer/Include.v b/01_Boolean_Logic/02_Buffer/Include.v new file mode 100644 index 0000000..0280ed4 --- /dev/null +++ b/01_Boolean_Logic/02_Buffer/Include.v @@ -0,0 +1,3 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" diff --git a/01_Boolean_Logic/02_Buffer/apio.ini b/01_Boolean_Logic/02_Buffer/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/02_Buffer/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/02_Buffer/iCE40HX1K.pcf b/01_Boolean_Logic/02_Buffer/iCE40HX1K.pcf new file mode 100644 index 0000000..bd6b479 --- /dev/null +++ b/01_Boolean_Logic/02_Buffer/iCE40HX1K.pcf @@ -0,0 +1,10 @@ +# physical constrain file +# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB +# compare to the schematic of the board and the datasheet of fpga + +set_io BUT1 41 # BUT1 +set_io BUT2 42 # BUT2 + +set_io LED1 40 # LED1 +set_io LED2 51 # LED2 + diff --git a/01_Boolean_Logic/02_Buffer/top.v b/01_Boolean_Logic/02_Buffer/top.v new file mode 100644 index 0000000..069cf0c --- /dev/null +++ b/01_Boolean_Logic/02_Buffer/top.v @@ -0,0 +1,12 @@ +`default_nettype none +module top( + input BUT1, + input BUT2, + output LED1, + output LED2 +); + + Buffer BUFFER1(.in(BUT1),.out(LED1)); + Buffer BUFFER2(.in(BUT2),.out(LED2)); + +endmodule diff --git a/01_Boolean_Logic/03_And/And_tb.gtkw b/01_Boolean_Logic/03_And/And_tb.gtkw new file mode 100644 index 0000000..5017b1d --- /dev/null +++ b/01_Boolean_Logic/03_And/And_tb.gtkw @@ -0,0 +1,33 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:37:27 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/03_And/And_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:36:57 2022" +[dumpfile_size] 779 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/03_And/And_tb.gtkw" +[timestart] 0 +[size] 1227 600 +[pos] -1 -1 +*-0.771027 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 100 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@200 +-IN +@29 +And_tb.a +@28 +And_tb.b +@200 +-OUT +@28 +And_tb.out +@200 +-CMP +@28 +And_tb.out_cmp +And_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/03_And/And_tb.v b/01_Boolean_Logic/03_And/And_tb.v new file mode 100644 index 0000000..b273aff --- /dev/null +++ b/01_Boolean_Logic/03_And/And_tb.v @@ -0,0 +1,47 @@ +`default_nettype none +module And_tb(); + + // IN,OUT + reg a,b; + wire out; + + // Part + And AND( + .a(a), + .b(b), + .out(out) + ); + + // Compare + wire out_cmp; + assign out_cmp = a&b; + + reg fail = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: a=%1b,b=%1b,out=%1b",a,b,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("And_tb.vcd"); + $dumpvars(0, And_tb); + + $display("------------------------"); + $display("Testbench: And"); + + a=0;b=0;check(); + a=0;b=1;check(); + a=1;b=0;check(); + a=1;b=1;check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/03_And/Include.v b/01_Boolean_Logic/03_And/Include.v new file mode 100644 index 0000000..d78fbd5 --- /dev/null +++ b/01_Boolean_Logic/03_And/Include.v @@ -0,0 +1,4 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" diff --git a/01_Boolean_Logic/03_And/apio.ini b/01_Boolean_Logic/03_And/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/03_And/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/03_And/iCE40HX1K.pcf b/01_Boolean_Logic/03_And/iCE40HX1K.pcf new file mode 100644 index 0000000..bd6b479 --- /dev/null +++ b/01_Boolean_Logic/03_And/iCE40HX1K.pcf @@ -0,0 +1,10 @@ +# physical constrain file +# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB +# compare to the schematic of the board and the datasheet of fpga + +set_io BUT1 41 # BUT1 +set_io BUT2 42 # BUT2 + +set_io LED1 40 # LED1 +set_io LED2 51 # LED2 + diff --git a/01_Boolean_Logic/03_And/top.v b/01_Boolean_Logic/03_And/top.v new file mode 100644 index 0000000..386e894 --- /dev/null +++ b/01_Boolean_Logic/03_And/top.v @@ -0,0 +1,11 @@ +`default_nettype none +module top( + input BUT1, + input BUT2, + output LED1, + output LED2 +); + + And AND(.a(BUT1),.b(BUT2),.out(LED1)); + +endmodule diff --git a/01_Boolean_Logic/04_Or/Include.v b/01_Boolean_Logic/04_Or/Include.v new file mode 100644 index 0000000..b333870 --- /dev/null +++ b/01_Boolean_Logic/04_Or/Include.v @@ -0,0 +1,5 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" diff --git a/01_Boolean_Logic/04_Or/Or_tb.gtkw b/01_Boolean_Logic/04_Or/Or_tb.gtkw new file mode 100644 index 0000000..4fcb1d7 --- /dev/null +++ b/01_Boolean_Logic/04_Or/Or_tb.gtkw @@ -0,0 +1,35 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:50:31 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/04_Or/Or_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:50:17 2022" +[dumpfile_size] 999 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/04_Or/Or_tb.gtkw" +[timestart] 0 +[size] 1292 600 +[pos] -1 -1 +*-0.771027 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 100 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@200 +-IN +@28 +Or_tb.a +Or_tb.b +@200 +-OUT +@28 +Or_tb.out +@200 +-CMP +@29 +Or_tb.out_cmp +@200 +-Test +@28 +Or_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/04_Or/Or_tb.v b/01_Boolean_Logic/04_Or/Or_tb.v new file mode 100644 index 0000000..2a8b47f --- /dev/null +++ b/01_Boolean_Logic/04_Or/Or_tb.v @@ -0,0 +1,48 @@ +`default_nettype none +module Or_tb(); + + // IN,OUT + reg a,b; + wire out; + + // Part + Or OR( + .a(a), + .b(b), + .out(out) + ); + + // Compare + wire out_cmp; + assign out_cmp = a|b; + + reg fail=0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: a=%1b, b=%1b, out=%1b",a,b,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("Or_tb.vcd"); + $dumpvars(0, Or_tb); + + $display("------------------------"); + $display("Testbench: Or"); + + a=0;b=0;check(); + a=0;b=1;check(); + a=1;b=0;check(); + a=1;b=1;check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/04_Or/apio.ini b/01_Boolean_Logic/04_Or/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/04_Or/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/04_Or/iCE40HX1K.pcf b/01_Boolean_Logic/04_Or/iCE40HX1K.pcf new file mode 100644 index 0000000..bd6b479 --- /dev/null +++ b/01_Boolean_Logic/04_Or/iCE40HX1K.pcf @@ -0,0 +1,10 @@ +# physical constrain file +# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB +# compare to the schematic of the board and the datasheet of fpga + +set_io BUT1 41 # BUT1 +set_io BUT2 42 # BUT2 + +set_io LED1 40 # LED1 +set_io LED2 51 # LED2 + diff --git a/01_Boolean_Logic/04_Or/top.v b/01_Boolean_Logic/04_Or/top.v new file mode 100644 index 0000000..a6abec7 --- /dev/null +++ b/01_Boolean_Logic/04_Or/top.v @@ -0,0 +1,11 @@ +`default_nettype none +module top( + input BUT1, + input BUT2, + output LED1, + output LED2 +); + + Or OR(.a(BUT1),.b(BUT2),.out(LED1)); + +endmodule diff --git a/01_Boolean_Logic/05_Xor/Include.v b/01_Boolean_Logic/05_Xor/Include.v new file mode 100644 index 0000000..6449106 --- /dev/null +++ b/01_Boolean_Logic/05_Xor/Include.v @@ -0,0 +1,6 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" diff --git a/01_Boolean_Logic/05_Xor/Xor.png b/01_Boolean_Logic/05_Xor/Xor.png new file mode 100644 index 0000000..aa83d26 Binary files /dev/null and b/01_Boolean_Logic/05_Xor/Xor.png differ diff --git a/01_Boolean_Logic/05_Xor/Xor_tb.gtkw b/01_Boolean_Logic/05_Xor/Xor_tb.gtkw new file mode 100644 index 0000000..a2c858e --- /dev/null +++ b/01_Boolean_Logic/05_Xor/Xor_tb.gtkw @@ -0,0 +1,35 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:50:07 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/05_Xor/Xor_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:49:53 2022" +[dumpfile_size] 987 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/05_Xor/Xor_tb.gtkw" +[timestart] 0 +[size] 1332 600 +[pos] -1 -1 +*-0.771027 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 100 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@200 +-IN +@28 +Xor_tb.a +Xor_tb.b +@200 +-OUT +@28 +Xor_tb.out +@200 +-CMP +@29 +Xor_tb.out_cmp +@200 +-Test +@28 +Xor_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/05_Xor/Xor_tb.v b/01_Boolean_Logic/05_Xor/Xor_tb.v new file mode 100644 index 0000000..d89d063 --- /dev/null +++ b/01_Boolean_Logic/05_Xor/Xor_tb.v @@ -0,0 +1,47 @@ +`default_nettype none +module Xor_tb(); + + // IN,OUT + reg a,b; + wire out; + + // Part + Xor XOR( + .a(a), + .b(b), + .out(out) + ); + + // Compare + wire out_cmp; + assign out_cmp = a^b; + + reg fail = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: a=%1b, b=%1b, out=%1b",a,b,out); + fail = 1; + end + endtask + + // Test + initial begin + $dumpfile("Xor_tb.vcd"); + $dumpvars(0, Xor_tb); + + $display("------------------------"); + $display("Testbench: Xor"); + + a=0;b=0;check(); + a=0;b=1;check(); + a=1;b=0;check(); + a=1;b=1;check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/05_Xor/apio.ini b/01_Boolean_Logic/05_Xor/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/05_Xor/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/05_Xor/iCE40HX1K.pcf b/01_Boolean_Logic/05_Xor/iCE40HX1K.pcf new file mode 100644 index 0000000..bd6b479 --- /dev/null +++ b/01_Boolean_Logic/05_Xor/iCE40HX1K.pcf @@ -0,0 +1,10 @@ +# physical constrain file +# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB +# compare to the schematic of the board and the datasheet of fpga + +set_io BUT1 41 # BUT1 +set_io BUT2 42 # BUT2 + +set_io LED1 40 # LED1 +set_io LED2 51 # LED2 + diff --git a/01_Boolean_Logic/05_Xor/top.v b/01_Boolean_Logic/05_Xor/top.v new file mode 100644 index 0000000..5dce974 --- /dev/null +++ b/01_Boolean_Logic/05_Xor/top.v @@ -0,0 +1,11 @@ +`default_nettype none +module top( + input BUT1, + input BUT2, + output LED1, + output LED2 +); + + Xor XOR(.a(BUT1),.b(BUT2),.out(LED1)); + +endmodule diff --git a/01_Boolean_Logic/06_Mux/Include.v b/01_Boolean_Logic/06_Mux/Include.v new file mode 100644 index 0000000..eabd3ed --- /dev/null +++ b/01_Boolean_Logic/06_Mux/Include.v @@ -0,0 +1,7 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" diff --git a/01_Boolean_Logic/06_Mux/Mux_tb.gtkw b/01_Boolean_Logic/06_Mux/Mux_tb.gtkw new file mode 100644 index 0000000..244a98f --- /dev/null +++ b/01_Boolean_Logic/06_Mux/Mux_tb.gtkw @@ -0,0 +1,36 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:49:39 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/06_Mux/Mux_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:49:24 2022" +[dumpfile_size] 2362 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/06_Mux/Mux_tb.gtkw" +[timestart] 0 +[size] 1000 600 +[pos] -1 -1 +*-1.619024 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 100 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@200 +-IN +@28 +Mux_tb.a +Mux_tb.b +Mux_tb.sel +@200 +-OUT +@28 +Mux_tb.out +@200 +-CMP +@29 +Mux_tb.out_cmp +@200 +-Test +@28 +Mux_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/06_Mux/Mux_tb.v b/01_Boolean_Logic/06_Mux/Mux_tb.v new file mode 100644 index 0000000..034c803 --- /dev/null +++ b/01_Boolean_Logic/06_Mux/Mux_tb.v @@ -0,0 +1,52 @@ +`default_nettype none +module Mux_tb(); + + // IN,OUT + reg a,b,sel; + wire out; + + // Part + Mux MUX( + .a(a), + .b(b), + .sel(sel), + .out(out) + ); + + // Compare + wire out_cmp; + assign out_cmp = (sel?b:a); + + reg fail = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: a=%1b, b=%1b, sel=%1b, out=%1b",a,b,sel,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("Mux_tb.vcd"); + $dumpvars(0, Mux_tb); + + $display("------------------------"); + $display("Testbench: Mux"); + + a=0;b=0;sel=0;check(); + a=0;b=0;sel=1;check(); + a=0;b=1;sel=0;check(); + a=0;b=1;sel=1;check(); + a=1;b=0;sel=0;check(); + a=1;b=0;sel=1;check(); + a=1;b=1;sel=0;check(); + a=1;b=1;sel=1;check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/06_Mux/apio.ini b/01_Boolean_Logic/06_Mux/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/06_Mux/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/07_DMux/DMux_tb.gtkw b/01_Boolean_Logic/07_DMux/DMux_tb.gtkw new file mode 100644 index 0000000..3232a71 --- /dev/null +++ b/01_Boolean_Logic/07_DMux/DMux_tb.gtkw @@ -0,0 +1,37 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:49:10 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/07_DMux/DMux_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:48:46 2022" +[dumpfile_size] 1611 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/07_DMux/DMux_tb.gtkw" +[timestart] 0 +[size] 1355 600 +[pos] -1 -1 +*-0.771027 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 80 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@200 +-IN +@28 +DMux_tb.in +DMux_tb.sel +@200 +-OUT +@28 +DMux_tb.a +DMux_tb.b +@200 +-CMP +@28 +DMux_tb.a_cmp +DMux_tb.b_cmp +@200 +-Test +@29 +DMux_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/07_DMux/DMux_tb.v b/01_Boolean_Logic/07_DMux/DMux_tb.v new file mode 100644 index 0000000..87bd5b3 --- /dev/null +++ b/01_Boolean_Logic/07_DMux/DMux_tb.v @@ -0,0 +1,49 @@ +`default_nettype none +module DMux_tb(); + + // IN,OUT + reg in,sel; + wire a,b; + + // Part + DMux DMUX( + .in(in), + .sel(sel), + .a(a), + .b(b) + ); + + // Compare + wire a_cmp,b_cmp; + assign a_cmp = (~sel&in); + assign b_cmp = sel∈ + + reg fail=0; + task check; + #1 + if ((a != a_cmp) || (b != b_cmp)) + begin + $display("FAIL: in=%1b, sel=%1b, a=%1b, b=%1b",in,sel,a,b); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("DMux_tb.vcd"); + $dumpvars(0, DMux_tb); + + $display("------------------------"); + $display("Testbench: DMux"); + + in=0;sel=0;check(); + in=0;sel=1;check(); + in=1;sel=0;check(); + in=1;sel=1;check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/07_DMux/Include.v b/01_Boolean_Logic/07_DMux/Include.v new file mode 100644 index 0000000..ec0655e --- /dev/null +++ b/01_Boolean_Logic/07_DMux/Include.v @@ -0,0 +1,8 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" diff --git a/01_Boolean_Logic/07_DMux/apio.ini b/01_Boolean_Logic/07_DMux/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/07_DMux/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/07_DMux/iCE40HX1K.pcf b/01_Boolean_Logic/07_DMux/iCE40HX1K.pcf new file mode 100644 index 0000000..bd6b479 --- /dev/null +++ b/01_Boolean_Logic/07_DMux/iCE40HX1K.pcf @@ -0,0 +1,10 @@ +# physical constrain file +# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB +# compare to the schematic of the board and the datasheet of fpga + +set_io BUT1 41 # BUT1 +set_io BUT2 42 # BUT2 + +set_io LED1 40 # LED1 +set_io LED2 51 # LED2 + diff --git a/01_Boolean_Logic/07_DMux/top.v b/01_Boolean_Logic/07_DMux/top.v new file mode 100644 index 0000000..b415c91 --- /dev/null +++ b/01_Boolean_Logic/07_DMux/top.v @@ -0,0 +1,11 @@ +`default_nettype none +module top( + input BUT1, + input BUT2, + output LED1, + output LED2 +); + + DMux DMUX(.in(BUT1),.sel(BUT2),.a(LED1),.b(LED2)); + +endmodule diff --git a/01_Boolean_Logic/08_Not16/Include.v b/01_Boolean_Logic/08_Not16/Include.v new file mode 100644 index 0000000..6b4c329 --- /dev/null +++ b/01_Boolean_Logic/08_Not16/Include.v @@ -0,0 +1,9 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" diff --git a/01_Boolean_Logic/08_Not16/Not16_tb.gtkw b/01_Boolean_Logic/08_Not16/Not16_tb.gtkw new file mode 100644 index 0000000..b2ce403 --- /dev/null +++ b/01_Boolean_Logic/08_Not16/Not16_tb.gtkw @@ -0,0 +1,34 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:48:32 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/08_Not16/Not16_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:48:11 2022" +[dumpfile_size] 1656008 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/08_Not16/Not16_tb.gtkw" +[timestart] 0 +[size] 1486 562 +[pos] -1 -1 +*-2.107311 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 119 +@200 +-IN +@22 +Not16_tb.in[0:15] +@200 +-OUT +@22 +Not16_tb.out[0:15] +@200 +-CMP +@22 +Not16_tb.out_cmp[15:0] +@201 +-Test +@28 +Not16_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/08_Not16/Not16_tb.v b/01_Boolean_Logic/08_Not16/Not16_tb.v new file mode 100644 index 0000000..e64c805 --- /dev/null +++ b/01_Boolean_Logic/08_Not16/Not16_tb.v @@ -0,0 +1,48 @@ +`default_nettype none +module Not16_tb(); + + // IN,OUT + reg [0:15] in; + wire [0:15] out; + + // Part + Not16 NOT16( + .in(in), + .out(out) + ); + + // Compare + wire [15:0] out_cmp; + assign out_cmp = ~in; + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: a=%16b, out=%16b",in,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("Not16_tb.vcd"); + $dumpvars(0, Not16_tb); + + $display("------------------------"); + $display("Testbench: Not16"); + + for (n=0; n<10000;n=n+1) + begin + in=$random; + check(); + end + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/08_Not16/apio.ini b/01_Boolean_Logic/08_Not16/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/08_Not16/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/09_Buffer16/Buffer16_tb.gtkw b/01_Boolean_Logic/09_Buffer16/Buffer16_tb.gtkw new file mode 100644 index 0000000..24835fc --- /dev/null +++ b/01_Boolean_Logic/09_Buffer16/Buffer16_tb.gtkw @@ -0,0 +1,34 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Wed Jan 4 11:28:38 2023 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/01_Boolean_Logic/09_Buffer16/Buffer16_tb.vcd" +[dumpfile_mtime] "Wed Jan 4 11:27:59 2023" +[dumpfile_size] 3089054 +[savefile] "/home/micha/gitlab/nand2tetris-fpga/01_Boolean_Logic/09_Buffer16/Buffer16_tb.gtkw" +[timestart] 0 +[size] 1547 481 +[pos] -1 -1 +*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 91 +@200 +-IN +@23 +Buffer16_tb.in[15:0] +@200 +-OUT +@22 +Buffer16_tb.out[15:0] +@200 +-CMP +@22 +Buffer16_tb.out_cmp[15:0] +@200 +-Test +@28 +Buffer16_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/09_Buffer16/Buffer16_tb.v b/01_Boolean_Logic/09_Buffer16/Buffer16_tb.v new file mode 100644 index 0000000..83a89d9 --- /dev/null +++ b/01_Boolean_Logic/09_Buffer16/Buffer16_tb.v @@ -0,0 +1,49 @@ +`default_nettype none +module Buffer16_tb(); + + // IN,OUT + reg [15:0] in; + wire [15:0] out; + + // Part + Buffer16 BUFFER16( + .in(in), + .out(out) + ); + + // Compare + wire [15:0] out_cmp; + assign out_cmp = in; + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: in=%16b, out=%16b",in,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("Buffer16_tb.vcd"); + $dumpvars(0, Buffer16_tb); + + $display("------------------------"); + $display("Testbench: Buffer16"); + + for (n=0; n<10000;n=n+1) + begin + in=$random; + check(); + + end + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/09_Buffer16/Include.v b/01_Boolean_Logic/09_Buffer16/Include.v new file mode 100644 index 0000000..71e680d --- /dev/null +++ b/01_Boolean_Logic/09_Buffer16/Include.v @@ -0,0 +1,10 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" diff --git a/01_Boolean_Logic/09_Buffer16/apio.ini b/01_Boolean_Logic/09_Buffer16/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/09_Buffer16/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/10_And16/And16_tb.gtkw b/01_Boolean_Logic/10_And16/And16_tb.gtkw new file mode 100644 index 0000000..924ec91 --- /dev/null +++ b/01_Boolean_Logic/10_And16/And16_tb.gtkw @@ -0,0 +1,35 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:47:53 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/09_And16/And16_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:47:31 2022" +[dumpfile_size] 2339414 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/09_And16/And16_tb.gtkw" +[timestart] 5 +[size] 1000 600 +[pos] -1 -1 +*-2.000000 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@200 +-IN +@22 +And16_tb.a[15:0] +And16_tb.b[15:0] +@200 +-OUT +@22 +And16_tb.out[15:0] +@200 +-CMP +@23 +And16_tb.out_cmp[15:0] +@200 +-Test +@28 +And16_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/10_And16/And16_tb.v b/01_Boolean_Logic/10_And16/And16_tb.v new file mode 100644 index 0000000..013b3c8 --- /dev/null +++ b/01_Boolean_Logic/10_And16/And16_tb.v @@ -0,0 +1,51 @@ +`default_nettype none +module And16_tb(); + + // IN,OUT + reg [15:0] a,b; + wire [15:0] out; + + // Part + And16 AND16( + .a(a), + .b(b), + .out(out) + ); + + // Compare + wire [15:0] out_cmp; + assign out_cmp = a&b; + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: a=%16b, b=%16b, out=%16b",a,b,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("And16_tb.vcd"); + $dumpvars(0, And16_tb); + + $display("------------------------"); + $display("Testbench: And16"); + + for (n=0; n<10000;n=n+1) + begin + a=$random; + b=$random; + check(); + + end + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/10_And16/Include.v b/01_Boolean_Logic/10_And16/Include.v new file mode 100644 index 0000000..ad81715 --- /dev/null +++ b/01_Boolean_Logic/10_And16/Include.v @@ -0,0 +1,11 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" diff --git a/01_Boolean_Logic/10_And16/apio.ini b/01_Boolean_Logic/10_And16/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/10_And16/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/11_Or16/Include.v b/01_Boolean_Logic/11_Or16/Include.v new file mode 100644 index 0000000..ac80367 --- /dev/null +++ b/01_Boolean_Logic/11_Or16/Include.v @@ -0,0 +1,12 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" diff --git a/01_Boolean_Logic/11_Or16/Or16_tb.gtkw b/01_Boolean_Logic/11_Or16/Or16_tb.gtkw new file mode 100644 index 0000000..8684413 --- /dev/null +++ b/01_Boolean_Logic/11_Or16/Or16_tb.gtkw @@ -0,0 +1,35 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:47:03 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/10_Or16/Or16_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:46:45 2022" +[dumpfile_size] 2724821 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/10_Or16/Or16_tb.gtkw" +[timestart] 0 +[size] 1000 600 +[pos] -1 -1 +*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@200 +-IN +@22 +Or16_tb.a[15:0] +Or16_tb.b[15:0] +@200 +-OUT +@22 +Or16_tb.out[15:0] +@200 +-CMP +@22 +Or16_tb.out_cmp[15:0] +@200 +-Test +@29 +Or16_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/11_Or16/Or16_tb.v b/01_Boolean_Logic/11_Or16/Or16_tb.v new file mode 100644 index 0000000..85a6345 --- /dev/null +++ b/01_Boolean_Logic/11_Or16/Or16_tb.v @@ -0,0 +1,50 @@ +`default_nettype none +module Or16_tb(); + + // IN,OUT + reg [15:0] a,b; + wire [15:0] out; + + // Part + Or16 OR16( + .a(a), + .b(b), + .out(out) + ); + + // Compare + wire [15:0] out_cmp; + assign out_cmp = a|b; + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: a=%16b, b=%16b, out=%16b",a,b,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("Or16_tb.vcd"); + $dumpvars(0, Or16_tb); + + $display("------------------------"); + $display("Testbench: Or16"); + + for (n=0; n<10000;n=n+1) + begin + a=$random; + b=$random; + check(); + end + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/11_Or16/apio.ini b/01_Boolean_Logic/11_Or16/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/11_Or16/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/12_Mux16/Include.v b/01_Boolean_Logic/12_Mux16/Include.v new file mode 100644 index 0000000..8589223 --- /dev/null +++ b/01_Boolean_Logic/12_Mux16/Include.v @@ -0,0 +1,13 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" diff --git a/01_Boolean_Logic/12_Mux16/Mux16_tb.gtkw b/01_Boolean_Logic/12_Mux16/Mux16_tb.gtkw new file mode 100644 index 0000000..759f58a --- /dev/null +++ b/01_Boolean_Logic/12_Mux16/Mux16_tb.gtkw @@ -0,0 +1,37 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:45:15 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/11_Mux16/Mux16_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:44:57 2022" +[dumpfile_size] 7849723 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/11_Mux16/Mux16_tb.gtkw" +[timestart] 0 +[size] 1000 600 +[pos] -1 -1 +*0.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@200 +-IN +@22 +Mux16_tb.a[15:0] +Mux16_tb.b[15:0] +@28 +Mux16_tb.sel +@200 +-OUT +@22 +Mux16_tb.out[15:0] +@200 +-CMP +@22 +Mux16_tb.out_cmp[15:0] +@201 +-Test +@28 +Mux16_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/12_Mux16/Mux16_tb.v b/01_Boolean_Logic/12_Mux16/Mux16_tb.v new file mode 100644 index 0000000..6d04ec1 --- /dev/null +++ b/01_Boolean_Logic/12_Mux16/Mux16_tb.v @@ -0,0 +1,53 @@ +`default_nettype none +module Mux16_tb(); + + // IN,OUT + reg [15:0] a,b; + reg sel; + wire [15:0] out; + + // Part + Mux16 MUX16( + .a(a), + .b(b), + .sel(sel), + .out(out) + ); + + // Compare + wire [15:0] out_cmp; + assign out_cmp = sel?b:a; + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: a=%16b, b=%16b, sel=%1b, out=%16b",a,b,sel,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("Mux16_tb.vcd"); + $dumpvars(0, Mux16_tb); + + $display("------------------------"); + $display("Testbench: Mux16"); + + for (n=0; n<10000;n=n+1) + begin + a=$random; + b=$random; + sel=0;check(); + sel=1;check(); + end + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/12_Mux16/apio.ini b/01_Boolean_Logic/12_Mux16/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/12_Mux16/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/13_Or8Way/Include.v b/01_Boolean_Logic/13_Or8Way/Include.v new file mode 100644 index 0000000..de0897c --- /dev/null +++ b/01_Boolean_Logic/13_Or8Way/Include.v @@ -0,0 +1,14 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" diff --git a/01_Boolean_Logic/13_Or8Way/Or8Way_tb.gtkw b/01_Boolean_Logic/13_Or8Way/Or8Way_tb.gtkw new file mode 100644 index 0000000..d29eff8 --- /dev/null +++ b/01_Boolean_Logic/13_Or8Way/Or8Way_tb.gtkw @@ -0,0 +1,34 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:44:04 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/12_Or8Way/Or8Way_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:43:43 2022" +[dumpfile_size] 792009 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/12_Or8Way/Or8Way_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -1 -1 +*-2.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 100 +[sst_expanded] 1 +[sst_vpaned_height] 259 +@200 +-IN +@22 +Or8Way_tb.in[7:0] +@200 +-OUT +@28 +Or8Way_tb.out +@200 +-CMP +@28 +Or8Way_tb.out_cmp +@201 +-Test +@28 +Or8Way_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/13_Or8Way/Or8Way_tb.v b/01_Boolean_Logic/13_Or8Way/Or8Way_tb.v new file mode 100644 index 0000000..18a05a8 --- /dev/null +++ b/01_Boolean_Logic/13_Or8Way/Or8Way_tb.v @@ -0,0 +1,50 @@ +`default_nettype none +module Or8Way_tb(); + + // IN,OUT + reg [7:0] in; + wire out; + + // Part + Or8Way OR8WAY( + .in(in), + .out(out) + ); + + // Compare + wire out_cmp; + assign out_cmp = |in; + + reg fail = 0; + reg [15:0] n=0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: in=%8b, out=%1b",in,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("Or8Way_tb.vcd"); + $dumpvars(0, Or8Way_tb); + + $display("------------------------"); + $display("Testbench: Or8Way"); + + in=0; + check(); + for (n=0; n<10000;n=n+1) + begin + in=$random; + check(); + end + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/13_Or8Way/apio.ini b/01_Boolean_Logic/13_Or8Way/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/13_Or8Way/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/14_Mux4Way16/Include.v b/01_Boolean_Logic/14_Mux4Way16/Include.v new file mode 100644 index 0000000..1c2060a --- /dev/null +++ b/01_Boolean_Logic/14_Mux4Way16/Include.v @@ -0,0 +1,15 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" diff --git a/01_Boolean_Logic/14_Mux4Way16/Mux4Way16_tb.gtkw b/01_Boolean_Logic/14_Mux4Way16/Mux4Way16_tb.gtkw new file mode 100644 index 0000000..713bab0 --- /dev/null +++ b/01_Boolean_Logic/14_Mux4Way16/Mux4Way16_tb.gtkw @@ -0,0 +1,40 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:42:01 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/13_Mux4Way16/Mux4Way16_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:41:40 2022" +[dumpfile_size] 4764720 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/13_Mux4Way16/Mux4Way16_tb.gtkw" +[timestart] 0 +[size] 1000 600 +[pos] -1 -1 +*0.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] Mux4Way16_tb. +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@200 +-IN +@22 +Mux4Way16_tb.a[15:0] +Mux4Way16_tb.b[15:0] +Mux4Way16_tb.c[15:0] +Mux4Way16_tb.d[15:0] +@28 +Mux4Way16_tb.sel[1:0] +@200 +-OUT +@22 +Mux4Way16_tb.out[15:0] +@200 +-CMP +@22 +Mux4Way16_tb.out_cmp[15:0] +@201 +-Test +@28 +Mux4Way16_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/14_Mux4Way16/Mux4Way16_tb.v b/01_Boolean_Logic/14_Mux4Way16/Mux4Way16_tb.v new file mode 100644 index 0000000..0aff0ef --- /dev/null +++ b/01_Boolean_Logic/14_Mux4Way16/Mux4Way16_tb.v @@ -0,0 +1,59 @@ +`default_nettype none +module Mux4Way16_tb(); + + // IN,OUT + reg [15:0] a,b,c,d; + reg [1:0] sel; + wire [15:0] out; + + // Part + Mux4Way16 MUX4WAY16( + .a(a), + .b(b), + .c(c), + .d(d), + .sel(sel), + .out(out) + ); + + // Compare + wire [15:0] out_cmp; + assign out_cmp = (sel[1]? (sel[0]?d:c):(sel[0]?b:a)); + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: a=%16b, b=%16b, c=%16b, d=%16b, sel=%2b, out=%16b",a,b,c,d,sel,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("Mux4Way16_tb.vcd"); + $dumpvars(0, Mux4Way16_tb); + + $display("------------------------"); + $display("Testbench: Mux4Way16"); + + for (n=0; n<1000;n=n+1) + begin + a=$random; + b=$random; + c=$random; + d=$random; + sel=0;check(); + sel=1;check(); + sel=2;check(); + sel=3;check(); + end + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/14_Mux4Way16/apio.ini b/01_Boolean_Logic/14_Mux4Way16/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/14_Mux4Way16/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/15_Mux8Way16/Include.v b/01_Boolean_Logic/15_Mux8Way16/Include.v new file mode 100644 index 0000000..17112d4 --- /dev/null +++ b/01_Boolean_Logic/15_Mux8Way16/Include.v @@ -0,0 +1,16 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" diff --git a/01_Boolean_Logic/15_Mux8Way16/Mux8Way16_tb.gtkw b/01_Boolean_Logic/15_Mux8Way16/Mux8Way16_tb.gtkw new file mode 100644 index 0000000..0899df6 --- /dev/null +++ b/01_Boolean_Logic/15_Mux8Way16/Mux8Way16_tb.gtkw @@ -0,0 +1,43 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:41:14 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/14_Mux8Way16/Mux8Way16_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:40:51 2022" +[dumpfile_size] 2373256 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/14_Mux8Way16/Mux8Way16_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -1 -1 +*0.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 259 +@200 +-IN +@22 +Mux8Way16_tb.a[15:0] +Mux8Way16_tb.b[15:0] +Mux8Way16_tb.c[15:0] +Mux8Way16_tb.d[15:0] +Mux8Way16_tb.e[15:0] +Mux8Way16_tb.f[15:0] +Mux8Way16_tb.g[15:0] +Mux8Way16_tb.h[15:0] +@28 +Mux8Way16_tb.sel[2:0] +@200 +-OUT +@22 +Mux8Way16_tb.out[15:0] +@200 +-CMP +@22 +Mux8Way16_tb.out_cmp[15:0] +@201 +-Test +@28 +Mux8Way16_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/15_Mux8Way16/Mux8Way16_tb.v b/01_Boolean_Logic/15_Mux8Way16/Mux8Way16_tb.v new file mode 100644 index 0000000..20f265a --- /dev/null +++ b/01_Boolean_Logic/15_Mux8Way16/Mux8Way16_tb.v @@ -0,0 +1,71 @@ +`default_nettype none +module Mux8Way16_tb(); + + // IN,OUT + reg [15:0] a,b,c,d,e,f,g,h; + reg [2:0] sel; + wire [15:0] out; + + // PART + Mux8Way16 MUX8WAY16( + .a(a), + .b(b), + .c(c), + .d(d), + .e(e), + .f(f), + .g(g), + .h(h), + .sel(sel), + .out(out) + ); + + // Compare + wire [15:0] out_cmp; + assign out_cmp = (sel[2]?(sel[1]? (sel[0]?h:g):(sel[0]?f:e)): + (sel[1]? (sel[0]?d:c):(sel[0]?b:a))); + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: a=%16b, b=%16b, c=%16b, d=%16b, e=%16b, f=%16b, g=%16b, h=%16b, sel=%3b, out=%16b",a,b,c,d,e,f,g,h,sel,out); + fail=1; + end + endtask + + initial begin + $dumpfile("Mux8Way16_tb.vcd"); + $dumpvars(0, Mux8Way16_tb); + + $display("------------------------"); + $display("Testbench: Mux8Way16"); + + for (n=0; n<100;n=n+1) + begin + a=$random; + b=$random; + c=$random; + d=$random; + e=$random; + f=$random; + g=$random; + h=$random; + sel=0;check(); + sel=1;check(); + sel=2;check(); + sel=3;check(); + sel=4;check(); + sel=5;check(); + sel=6;check(); + sel=7;check(); + end + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/15_Mux8Way16/apio.ini b/01_Boolean_Logic/15_Mux8Way16/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/15_Mux8Way16/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/16_DMux4Way/DMux4Way_tb.gtkw b/01_Boolean_Logic/16_DMux4Way/DMux4Way_tb.gtkw new file mode 100644 index 0000000..a25fecc --- /dev/null +++ b/01_Boolean_Logic/16_DMux4Way/DMux4Way_tb.gtkw @@ -0,0 +1,43 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:40:27 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/15_DMux4Way/DMux4Way_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:39:53 2022" +[dumpfile_size] 4551 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/15_DMux4Way/DMux4Way_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -1 -1 +*-1.619024 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 110 +[sst_expanded] 1 +[sst_vpaned_height] 258 +@200 +-IN +@28 +DMux4Way_tb.in +DMux4Way_tb.sel[1:0] +@200 +-OUT +@28 +DMux4Way_tb.a +DMux4Way_tb.b +DMux4Way_tb.c +DMux4Way_tb.d +@200 +-CMP +@28 +DMux4Way_tb.a_cmp +@29 +DMux4Way_tb.b_cmp +@28 +DMux4Way_tb.c_cmp +DMux4Way_tb.d_cmp +@200 +-Test +@28 +DMux4Way_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/16_DMux4Way/DMux4Way_tb.v b/01_Boolean_Logic/16_DMux4Way/DMux4Way_tb.v new file mode 100644 index 0000000..c3948bc --- /dev/null +++ b/01_Boolean_Logic/16_DMux4Way/DMux4Way_tb.v @@ -0,0 +1,57 @@ +`default_nettype none +module DMux4Way_tb(); + + // IN,OUT + reg in; + reg [1:0] sel; + wire a,b,c,d; + + // Part + DMux4Way DMUX4WAY( + .in(in), + .sel(sel), + .a(a), + .b(b), + .c(c), + .d(d) + ); + + // Compare + wire a_cmp,b_cmp,c_cmp,d_cmp; + assign a_cmp = (sel==0)?in:0; + assign b_cmp = (sel==1)?in:0; + assign c_cmp = (sel==2)?in:0; + assign d_cmp = (sel==3)?in:0; + + reg fail = 0; + task check; + #1 + if ((a != a_cmp) || (b != b_cmp) || (c != c_cmp) || (d != d_cmp)) + begin + $display("FAIL: in=%1b, sel=%1b, a=%1b, b=%1b, c=%1b, d=%1b",in,sel,a,b,c,d); + fail=1; + end + endtask + + initial begin + $dumpfile("DMux4Way_tb.vcd"); + $dumpvars(0, DMux4Way_tb); + + $display("------------------------"); + $display("Testbench: DMux4Way"); + + in=0;sel=0;check(); + in=0;sel=1;check(); + in=0;sel=2;check(); + in=0;sel=3;check(); + in=1;sel=0;check(); + in=1;sel=1;check(); + in=1;sel=2;check(); + in=1;sel=3;check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/16_DMux4Way/Include.v b/01_Boolean_Logic/16_DMux4Way/Include.v new file mode 100644 index 0000000..322481b --- /dev/null +++ b/01_Boolean_Logic/16_DMux4Way/Include.v @@ -0,0 +1,17 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" diff --git a/01_Boolean_Logic/16_DMux4Way/apio.ini b/01_Boolean_Logic/16_DMux4Way/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/16_DMux4Way/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/17_DMux8Way/DMux8Way_tb.gtkw b/01_Boolean_Logic/17_DMux8Way/DMux8Way_tb.gtkw new file mode 100644 index 0000000..5687e4a --- /dev/null +++ b/01_Boolean_Logic/17_DMux8Way/DMux8Way_tb.gtkw @@ -0,0 +1,49 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 14:39:25 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/16_DMux8Way/DMux8Way_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 14:38:18 2022" +[dumpfile_size] 10742 +[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/16_DMux8Way/DMux8Way_tb.gtkw" +[timestart] 0 +[size] 1669 793 +[pos] -1 -1 +*-1.619024 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 110 +[sst_expanded] 1 +[sst_vpaned_height] 197 +@200 +-IN +@28 +DMux8Way_tb.in +DMux8Way_tb.sel[2:0] +@200 +-OUT +@28 +DMux8Way_tb.a +DMux8Way_tb.b +DMux8Way_tb.c +DMux8Way_tb.d +DMux8Way_tb.e +DMux8Way_tb.f +DMux8Way_tb.g +DMux8Way_tb.h +@200 +-CMP +@28 +DMux8Way_tb.a_cmp +DMux8Way_tb.b_cmp +DMux8Way_tb.c_cmp +DMux8Way_tb.d_cmp +DMux8Way_tb.e_cmp +DMux8Way_tb.f_cmp +DMux8Way_tb.g_cmp +DMux8Way_tb.h_cmp +@201 +-Test +@28 +DMux8Way_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/01_Boolean_Logic/17_DMux8Way/DMux8Way_tb.v b/01_Boolean_Logic/17_DMux8Way/DMux8Way_tb.v new file mode 100644 index 0000000..1c25890 --- /dev/null +++ b/01_Boolean_Logic/17_DMux8Way/DMux8Way_tb.v @@ -0,0 +1,74 @@ +`default_nettype none +module DMux8Way_tb(); + + // IN,OUT + reg in; + reg [2:0] sel; + wire a,b,c,d,e,f,g,h; + + // Part + DMux8Way DMUX8WAY( + .in(in), + .sel(sel), + .a(a), + .b(b), + .c(c), + .d(d), + .e(e), + .f(f), + .g(g), + .h(h) + ); + + // Compare + wire a_cmp,b_cmp,c_cmp,d_cmp,e_cmp,f_cmp,g_cmp,h_cmp; + assign a_cmp = (sel==0)?in:0; + assign b_cmp = (sel==1)?in:0; + assign c_cmp = (sel==2)?in:0; + assign d_cmp = (sel==3)?in:0; + assign e_cmp = (sel==4)?in:0; + assign f_cmp = (sel==5)?in:0; + assign g_cmp = (sel==6)?in:0; + assign h_cmp = (sel==7)?in:0; + + reg fail = 0; + task check; + #1 + if ((a!=a_cmp)||(b!=b_cmp)||(c!=c_cmp)||(d!=d_cmp)||(e!=e_cmp)||(f!=f_cmp)||(g!=g_cmp)||(h!=h_cmp)) + begin + $display("FAIL: in=%1b, sel=%2b, a=%1b, b=%1b, c=%1b, d=%1b, e=%1b, f=%1b, g=%1b, h=%1b",in,sel,a,b,c,d,e,f,g,h); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("DMux8Way_tb.vcd"); + $dumpvars(0, DMux8Way_tb); + + $display("------------------------"); + $display("Testbench: DMux8Way"); + + in=0;sel=0;check(); + in=0;sel=1;check(); + in=0;sel=2;check(); + in=0;sel=3;check(); + in=0;sel=4;check(); + in=0;sel=5;check(); + in=0;sel=6;check(); + in=0;sel=7;check(); + in=1;sel=0;check(); + in=1;sel=1;check(); + in=1;sel=2;check(); + in=1;sel=3;check(); + in=1;sel=4;check(); + in=1;sel=5;check(); + in=1;sel=6;check(); + in=1;sel=7;check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/01_Boolean_Logic/17_DMux8Way/Include.v b/01_Boolean_Logic/17_DMux8Way/Include.v new file mode 100644 index 0000000..1c6d2cd --- /dev/null +++ b/01_Boolean_Logic/17_DMux8Way/Include.v @@ -0,0 +1,18 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" diff --git a/01_Boolean_Logic/17_DMux8Way/apio.ini b/01_Boolean_Logic/17_DMux8Way/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/01_Boolean_Logic/17_DMux8Way/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/01_Boolean_Logic/And.v b/01_Boolean_Logic/And.v new file mode 100644 index 0000000..0bc4814 --- /dev/null +++ b/01_Boolean_Logic/And.v @@ -0,0 +1,16 @@ +/** + * And gate: + * out = 1 if (a == 1 and b == 1) + * 0 otherwise + */ + +`default_nettype none +module And( + input a, + input b, + output out +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/And16.v b/01_Boolean_Logic/And16.v new file mode 100644 index 0000000..e0e7ffd --- /dev/null +++ b/01_Boolean_Logic/And16.v @@ -0,0 +1,15 @@ +/** + * 16-bit bitwise And: + * for i = 0..15: out[i] = (a[i] and b[i]) + */ + +`default_nettype none +module And16( + input [15:0] a, + input [15:0] b, + output [15:0] out +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/Buffer.v b/01_Boolean_Logic/Buffer.v new file mode 100644 index 0000000..4b4a7e9 --- /dev/null +++ b/01_Boolean_Logic/Buffer.v @@ -0,0 +1,14 @@ +/** + * Buffer: + * out = in + */ + +`default_nettype none +module Buffer( + input in, + output out +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/Buffer16.v b/01_Boolean_Logic/Buffer16.v new file mode 100644 index 0000000..911a9fd --- /dev/null +++ b/01_Boolean_Logic/Buffer16.v @@ -0,0 +1,14 @@ +/** + * 16-bit bitwise Buffer: + * for i = 0..15: out[i] = in[i] + */ + +`default_nettype none +module Buffer16( + input [15:0] in, + output [15:0] out +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/DMux.v b/01_Boolean_Logic/DMux.v new file mode 100644 index 0000000..01b68b5 --- /dev/null +++ b/01_Boolean_Logic/DMux.v @@ -0,0 +1,17 @@ +/** + * Demultiplexor: + * {a, b} = {in, 0} if sel == 0 + * {0, in} if sel == 1 + */ + +`default_nettype none +module DMux( + input in, + input sel, + output a, + output b +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/DMux4Way.v b/01_Boolean_Logic/DMux4Way.v new file mode 100644 index 0000000..495c851 --- /dev/null +++ b/01_Boolean_Logic/DMux4Way.v @@ -0,0 +1,21 @@ +/** + * 4-way demultiplexor: + * {a, b, c, d} = {in, 0, 0, 0} if sel == 00 + * {0, in, 0, 0} if sel == 01 + * {0, 0, in, 0} if sel == 10 + * {0, 0, 0, in} if sel == 11 + */ + +`default_nettype none +module DMux4Way( + input in, + input [1:0] sel, + output a, + output b, + output c, + output d +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/DMux8Way.v b/01_Boolean_Logic/DMux8Way.v new file mode 100644 index 0000000..3626055 --- /dev/null +++ b/01_Boolean_Logic/DMux8Way.v @@ -0,0 +1,25 @@ +/** + * 8-way demultiplexor: + * {a, b, c, d, e, f, g, h} = {in, 0, 0, 0, 0, 0, 0, 0} if sel == 000 + * {0, in, 0, 0, 0, 0, 0, 0} if sel == 001 + * etc. + * {0, 0, 0, 0, 0, 0, 0, in} if sel == 111 + */ + +`default_nettype none +module DMux8Way( + input in, + input [2:0] sel, + output a, + output b, + output c, + output d, + output e, + output f, + output g, + output h +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/Mux.v b/01_Boolean_Logic/Mux.v new file mode 100644 index 0000000..0b799e4 --- /dev/null +++ b/01_Boolean_Logic/Mux.v @@ -0,0 +1,17 @@ +/** + * Multiplexor: + * out = a if sel == 0 + * b otherwise + */ + +`default_nettype none +module Mux( + input a, + input b, + input sel, + output out +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/Mux16.v b/01_Boolean_Logic/Mux16.v new file mode 100644 index 0000000..2589a4e --- /dev/null +++ b/01_Boolean_Logic/Mux16.v @@ -0,0 +1,17 @@ +/** + * 16-bit multiplexor: + * for i = 0..15 out[i] = a[i] if sel == 0 + * b[i] if sel == 1 + */ + +`default_nettype none +module Mux16( + input [15:0] a, + input [15:0] b, + input sel, + output [15:0] out +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/Mux4Way16.v b/01_Boolean_Logic/Mux4Way16.v new file mode 100644 index 0000000..f5a1b3a --- /dev/null +++ b/01_Boolean_Logic/Mux4Way16.v @@ -0,0 +1,19 @@ +/** + * 16-bit multiplexor: + * for i = 0..15 out[i] = a[i] if sel == 0 + * b[i] if sel == 1 + */ + +`default_nettype none +module Mux4Way16( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input [1:0] sel, + output [15:0] out +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/Mux8Way16.v b/01_Boolean_Logic/Mux8Way16.v new file mode 100644 index 0000000..b2d2eb0 --- /dev/null +++ b/01_Boolean_Logic/Mux8Way16.v @@ -0,0 +1,23 @@ +/** + * 16-bit multiplexor: + * for i = 0..15 out[i] = a[i] if sel == 0 + * b[i] if sel == 1 + */ + +`default_nettype none +module Mux8Way16( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input [15:0] e, + input [15:0] f, + input [15:0] g, + input [15:0] h, + input [2:0] sel, + output [15:0] out +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/Nand.v b/01_Boolean_Logic/Nand.v new file mode 100644 index 0000000..3e22553 --- /dev/null +++ b/01_Boolean_Logic/Nand.v @@ -0,0 +1,18 @@ +/** + * Nand gate: + * out = 0 if (a == 1 and b == 1) + * 1 otherwise + */ + +`default_nettype none +module Nand( + input a, + input b, + output out +); + + // No need to implement this chip + // This chip is implemented using verilog primitives + nand(out,a,b); + +endmodule diff --git a/01_Boolean_Logic/Not.v b/01_Boolean_Logic/Not.v new file mode 100644 index 0000000..56117e0 --- /dev/null +++ b/01_Boolean_Logic/Not.v @@ -0,0 +1,14 @@ +/** + * Not gate: + * out = not in + */ + +`default_nettype none +module Not( + input in, + output out +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/Not16.v b/01_Boolean_Logic/Not16.v new file mode 100644 index 0000000..fd7e664 --- /dev/null +++ b/01_Boolean_Logic/Not16.v @@ -0,0 +1,14 @@ +/** + * 16-bit Not: + * for i=0..15: out[i] = not in[i] + */ + +`default_nettype none +module Not16( + input [15:0] in, + output [15:0] out +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/Or.v b/01_Boolean_Logic/Or.v new file mode 100644 index 0000000..577dbb2 --- /dev/null +++ b/01_Boolean_Logic/Or.v @@ -0,0 +1,16 @@ + /** + * Or gate: + * out = 1 if (a == 1 or b == 1) + * 0 otherwise + */ + +`default_nettype none +module Or( + input a, + input b, + output out +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/Or16.v b/01_Boolean_Logic/Or16.v new file mode 100644 index 0000000..946e864 --- /dev/null +++ b/01_Boolean_Logic/Or16.v @@ -0,0 +1,15 @@ +/** + * 16-bit bitwise And: + * for i = 0..15: out[i] = (a[i] and b[i]) + */ + +`default_nettype none +module Or16( + input [15:0] a, + input [15:0] b, + output [15:0] out +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/Or8Way.v b/01_Boolean_Logic/Or8Way.v new file mode 100644 index 0000000..2ad682b --- /dev/null +++ b/01_Boolean_Logic/Or8Way.v @@ -0,0 +1,14 @@ +/** + * 8-way Or: + * out = (in[0] or in[1] or ... or in[7]) + */ + +`default_nettype none +module Or8Way( + input [7:0] in, + output out +); + + // Put your code here: + +endmodule diff --git a/01_Boolean_Logic/Readme.md b/01_Boolean_Logic/Readme.md new file mode 100644 index 0000000..25c098c --- /dev/null +++ b/01_Boolean_Logic/Readme.md @@ -0,0 +1,135 @@ +# 01 Boolean Logic + +The hardware part of the project nand2tetris-fpga is implemented in verilog, a hardware description language similar to HDL used in the original nand2tetris course. There is no need to learn much verilog, as you can easily translate all your HDL-files into verilog following the given example for `Xor`. + +**Note:** +The following modules are considered primitive and thus there is no need to implement them. + +| module | description | +| ---------- | --------------------------------------------------------------------- | +| `Nand.v` | Nand-gate. Basic building block for combinatorial logic | +| `DFF.v` | Data Flip Flop. Basic building block for sequential logic | +| `RAM256.v` | uses Block Ram (BRAM) of iCE40 | +| `ROM.v` | uses Block Ram (BRAM) of iCE40 preloaded with HACK-code at startup | +| `InOut.v` | Tristate buffer, used to connect to the bidirectional databus of SRAM | + +*** + +## Example Xor + +### Xor.hdl + +Yout implementation of Xor in HDL (nand2tetris) should look something like: + +``` +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Xor.hdl + +/** +* Xor (exclusive or) gate: +* If a<>b out=1 else out=0. +*/ + +CHIP Xor { + IN a, b; + OUT out; + + PARTS: + Not(in=a, out=nota); + Not(in=b, out=notb); + And(a=a, b=notb, out=w1); + And(a=nota, b=b, out=w2); + Or(a=w1, b=w2, out=out); +} +``` + +### Xor.v + +`Xor.hdl` can easily be translated into `Xor.v` (verilog): + +``` +/** +* Xor (exclusive or) gate: +* If a<>b out=1 else out=0. +*/ + +module Xor( + input a, + input b, + output out +); + wire nota; //new wire must be declared (as wire) + wire notb; + Not NOT1(.in(a), .out(nota)); //Every chip has an instance name (NOT1) + Not NOT2(.in(b), .out(notb)); //this chip is named NOT2 + + wire w1; + wire w2; + And AND1(.a(a),.b(notb),.out(w1)); + And AND2(.a(nota),.b(b),.out(w2)); + + Or OR(.a(w1),.b(w2),.out(out)); +} +``` + +### Simulation + +For every chip wie provide a test folder e.g. `05_Xor`, in which you find a so called testbench (`Xor_tb.v`). To run the test bench cd into the test directory and run apio: + +``` +$ cd 05_Xor +$ apio clean (used to remove older implementation from cache) +$ apio sim +``` + +**Attention:** All used chips used in the verilog code must be already implemented and included in the `Include.v` file. + +The test bench will produce a graphical represantation `Xor.gtkw` of all signal lines, which can be viewed with gtkwave. + +![](05_Xor/Xor.png) + +You can see four sections: + +* `IN`: the input signals (generated by the test bench) +* `OUT`: the output signals (generated by YOUR chip implementation) +* `CMP`: the output signals (generated by the test bench) +* `Test`: the fail signal. Goes high, when the test fails. + +Your chip passes the test, when `out=out_cmp` and `fail=0` over the whole test time. + +### iCE40HX1K.pcf + +To upload the chip `Xor` onto your fpga board iCE40HX1K-EVB you need two additional files: `top.v` and `iCE40HX1K.pcf` (physical constraints file). The pyhiscal constraints file assigns every io-signal wire of the top level module `top.v` to physical pins of the fpga chip iCE40HX1K. Pin numbering can be checked by consulting the schematic [iCE40HX1K-EVB](../doc/iCE40HX1K-EVB_Rev_B.pdf) in `doc/iCE40HX1K-EVB_Rev_B.pdf`. + +``` +# physical constrain file +# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB +# compare to the schematic of the board and the datasheet of fpga + +set_io BUT1 41 # BUT1 +set_io BUT2 42 # BUT2 + +set_io LED1 40 # LED1 +set_io LED2 51    # LED2 +``` + +* Now you can build and upload the chip `Xor` to iCE40-HX1K-EVB with: + + ``` + $ apio clean + $ apio build + $ apio upload + ``` + +* Press buttons BUT1 and BUT2 and see the result of your `Xor` chip on LED1. + +**Attention:** Due to pull up resistors at the buttons, the signals appear inverted: + +| pin | function | +| ------ | ------------------------------------------------- | +| LED1/2 | 0 led is off, 1 led is on | +| BUT1/2 | 0 button is pressed down, 1 button is released up | + +Chips with note more than two in- and output signals can be uploaded and tested in real hardware: `Nand`, `Not`, `Buffer`, `And`, `Or`, `Xor` and `DMux`. \ No newline at end of file diff --git a/01_Boolean_Logic/Xor.v b/01_Boolean_Logic/Xor.v new file mode 100644 index 0000000..3c4789f --- /dev/null +++ b/01_Boolean_Logic/Xor.v @@ -0,0 +1,15 @@ +/** + * Exclusive-or gate: + * out = not (a == b) + */ + +`default_nettype none +module Xor( + input a, + input b, + output out +); + + // Put your code here: + +endmodule diff --git a/02_Boolean_Arithmetic/01_HalfAdder/HalfAdder_tb.gtkw b/02_Boolean_Arithmetic/01_HalfAdder/HalfAdder_tb.gtkw new file mode 100644 index 0000000..07ab4db --- /dev/null +++ b/02_Boolean_Arithmetic/01_HalfAdder/HalfAdder_tb.gtkw @@ -0,0 +1,37 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 17:31:37 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/01_HalfAdder/HalfAdder_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 17:31:23 2022" +[dumpfile_size] 1592 +[savefile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/01_HalfAdder/HalfAdder_tb.gtkw" +[timestart] 0 +[size] 1329 600 +[pos] -1 -1 +*-0.771027 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 150 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@200 +-IN +@28 +HalfAdder_tb.a +HalfAdder_tb.b +@200 +-OUT +@28 +HalfAdder_tb.sum +HalfAdder_tb.carry +@200 +-CMP +@28 +(1)HalfAdder_tb.out_cmp[1:0] +(0)HalfAdder_tb.out_cmp[1:0] +@200 +-Test +@28 +HalfAdder_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/02_Boolean_Arithmetic/01_HalfAdder/HalfAdder_tb.v b/02_Boolean_Arithmetic/01_HalfAdder/HalfAdder_tb.v new file mode 100644 index 0000000..d22e73d --- /dev/null +++ b/02_Boolean_Arithmetic/01_HalfAdder/HalfAdder_tb.v @@ -0,0 +1,47 @@ +`default_nettype none +module HalfAdder_tb(); + + // IN,OUT + reg a,b; + wire sum,carry; + + // Part + HalfAdder HALFADDER( + .a(a), + .b(b), + .sum(sum), + .carry(carry) + ); + + // Compare + wire [1:0] out_cmp; + assign out_cmp = a+b; + + reg fail = 0; + task check; + #1 + if ({carry,sum} != out_cmp) + begin + $display("FAIL: a=%1b, b=%1b, sum=%1b, carry=%1b",a,b,sum,carry); + fail=1; + end + endtask + + initial begin + $dumpfile("HalfAdder_tb.vcd"); + $dumpvars(0, HalfAdder_tb); + + $display("------------------------"); + $display("Testbench: HalfAdder"); + + a=0;b=0;check(); + a=0;b=1;check(); + a=1;b=0;check(); + a=1;b=1;check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/02_Boolean_Arithmetic/01_HalfAdder/Include.v b/02_Boolean_Arithmetic/01_HalfAdder/Include.v new file mode 100644 index 0000000..f4d746a --- /dev/null +++ b/02_Boolean_Arithmetic/01_HalfAdder/Include.v @@ -0,0 +1,9 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" + diff --git a/02_Boolean_Arithmetic/01_HalfAdder/apio.ini b/02_Boolean_Arithmetic/01_HalfAdder/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/02_Boolean_Arithmetic/01_HalfAdder/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/02_Boolean_Arithmetic/01_HalfAdder/iCE40HX1K.pcf b/02_Boolean_Arithmetic/01_HalfAdder/iCE40HX1K.pcf new file mode 100644 index 0000000..bd6b479 --- /dev/null +++ b/02_Boolean_Arithmetic/01_HalfAdder/iCE40HX1K.pcf @@ -0,0 +1,10 @@ +# physical constrain file +# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB +# compare to the schematic of the board and the datasheet of fpga + +set_io BUT1 41 # BUT1 +set_io BUT2 42 # BUT2 + +set_io LED1 40 # LED1 +set_io LED2 51 # LED2 + diff --git a/02_Boolean_Arithmetic/01_HalfAdder/top.v b/02_Boolean_Arithmetic/01_HalfAdder/top.v new file mode 100644 index 0000000..edf541e --- /dev/null +++ b/02_Boolean_Arithmetic/01_HalfAdder/top.v @@ -0,0 +1,11 @@ +`default_nettype none +module top( + input BUT1, + input BUT2, + output LED1, + output LED2 +); + + HalfAdder HA(.a(BUT1),.b(BUT2),.sum(LED1),.carry(LED2)); + +endmodule diff --git a/02_Boolean_Arithmetic/02_FullAdder/FullAdder_tb.gtkw b/02_Boolean_Arithmetic/02_FullAdder/FullAdder_tb.gtkw new file mode 100644 index 0000000..3935267 --- /dev/null +++ b/02_Boolean_Arithmetic/02_FullAdder/FullAdder_tb.gtkw @@ -0,0 +1,38 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 17:31:12 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/02_FullAdder/FullAdder_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 17:30:26 2022" +[dumpfile_size] 3773 +[savefile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/02_FullAdder/FullAdder_tb.gtkw" +[timestart] 0 +[size] 1000 600 +[pos] -1 -1 +*-1.619024 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 150 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@200 +-IN +@28 +FullAdder_tb.a +FullAdder_tb.b +FullAdder_tb.c +@200 +-OUT +@28 +FullAdder_tb.sum +FullAdder_tb.carry +@200 +-CMP +@28 +(1)FullAdder_tb.out_cmp[1:0] +(0)FullAdder_tb.out_cmp[1:0] +@200 +-Test +@28 +FullAdder_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/02_Boolean_Arithmetic/02_FullAdder/FullAdder_tb.v b/02_Boolean_Arithmetic/02_FullAdder/FullAdder_tb.v new file mode 100644 index 0000000..9882a65 --- /dev/null +++ b/02_Boolean_Arithmetic/02_FullAdder/FullAdder_tb.v @@ -0,0 +1,52 @@ +`default_nettype none +module FullAdder_tb(); + + // IN,OUT + reg a,b,c; + wire sum,carry; + + // Part + FullAdder FULLADDER( + .a(a), + .b(b), + .c(c), + .sum(sum), + .carry(carry) + ); + + // Compare + wire [1:0] out_cmp; + assign out_cmp = a+b+c; + + reg fail = 0; + task check; + #1 + if ({carry,sum} != out_cmp) + begin + $display("FAIL: a=%1b, b=%1b, c=%1b, sum=%1b, carry=%1b",a,b,c,sum,carry); + fail=1; + end + endtask + + initial begin + $dumpfile("FullAdder_tb.vcd"); + $dumpvars(0, FullAdder_tb); + + $display("------------------------"); + $display("Testbench: FullAdder"); + + a=0;b=0;c=0;check(); + a=0;b=0;c=1;check(); + a=0;b=1;c=0;check(); + a=0;b=1;c=1;check(); + a=1;b=0;c=0;check(); + a=1;b=0;c=1;check(); + a=1;b=1;c=0;check(); + a=1;b=1;c=1;check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/02_Boolean_Arithmetic/02_FullAdder/Include.v b/02_Boolean_Arithmetic/02_FullAdder/Include.v new file mode 100644 index 0000000..09fb359 --- /dev/null +++ b/02_Boolean_Arithmetic/02_FullAdder/Include.v @@ -0,0 +1,24 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + diff --git a/02_Boolean_Arithmetic/02_FullAdder/apio.ini b/02_Boolean_Arithmetic/02_FullAdder/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/02_Boolean_Arithmetic/02_FullAdder/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/02_Boolean_Arithmetic/03_Add16/Add16_tb.gtkw b/02_Boolean_Arithmetic/03_Add16/Add16_tb.gtkw new file mode 100644 index 0000000..4da98a6 --- /dev/null +++ b/02_Boolean_Arithmetic/03_Add16/Add16_tb.gtkw @@ -0,0 +1,35 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 17:32:11 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/03_Add16/Add16_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 17:31:52 2022" +[dumpfile_size] 678331 +[savefile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/03_Add16/Add16_tb.gtkw" +[timestart] 0 +[size] 1000 600 +[pos] -1 -1 +*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@200 +-IN +@22 +Add16_tb.a[15:0] +Add16_tb.b[15:0] +@200 +-OUT +@22 +Add16_tb.out[15:0] +@201 +-CMP +@22 +Add16_tb.out_cmp[15:0] +@200 +-Test +@28 +Add16_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/02_Boolean_Arithmetic/03_Add16/Add16_tb.v b/02_Boolean_Arithmetic/03_Add16/Add16_tb.v new file mode 100644 index 0000000..6d22dca --- /dev/null +++ b/02_Boolean_Arithmetic/03_Add16/Add16_tb.v @@ -0,0 +1,49 @@ +`default_nettype none +module Add16_tb(); + + // IN,OUT + reg [15:0] a,b; + wire [15:0] out; + + // Part + Add16 ADD16( + .a(a), + .b(b), + .out(out) + ); + + // Compare + wire [15:0] out_cmp; + assign out_cmp = a+b; + + reg fail = 0; + reg [15:0] n=0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: a=%16b, b=%16b, out=%16b",a,b,out); + fail=1; + end + endtask + + initial begin + $dumpfile("Add16_tb.vcd"); + $dumpvars(0, Add16_tb); + + $display("------------------------"); + $display("Testbench: Add16"); + + for (n=0; n<1000;n=n+1) + begin + a=$random; + b=$random; + check(); + end + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/02_Boolean_Arithmetic/03_Add16/Include.v b/02_Boolean_Arithmetic/03_Add16/Include.v new file mode 100644 index 0000000..09fb359 --- /dev/null +++ b/02_Boolean_Arithmetic/03_Add16/Include.v @@ -0,0 +1,24 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + diff --git a/02_Boolean_Arithmetic/03_Add16/apio.ini b/02_Boolean_Arithmetic/03_Add16/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/02_Boolean_Arithmetic/03_Add16/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/02_Boolean_Arithmetic/04_Inc16/Inc16_tb.gtkw b/02_Boolean_Arithmetic/04_Inc16/Inc16_tb.gtkw new file mode 100644 index 0000000..3742fa3 --- /dev/null +++ b/02_Boolean_Arithmetic/04_Inc16/Inc16_tb.gtkw @@ -0,0 +1,34 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 17:32:33 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/04_Inc16/Inc16_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 17:32:19 2022" +[dumpfile_size] 232467 +[savefile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/04_Inc16/Inc16_tb.gtkw" +[timestart] 0 +[size] 1000 600 +[pos] -1 -1 +*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@200 +-IN +@22 +Inc16_tb.in[15:0] +@200 +-OUT +@22 +Inc16_tb.out[15:0] +@201 +-CMP +@22 +Inc16_tb.out_cmp[15:0] +@200 +-Test +@28 +Inc16_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/02_Boolean_Arithmetic/04_Inc16/Inc16_tb.v b/02_Boolean_Arithmetic/04_Inc16/Inc16_tb.v new file mode 100644 index 0000000..feada61 --- /dev/null +++ b/02_Boolean_Arithmetic/04_Inc16/Inc16_tb.v @@ -0,0 +1,51 @@ +`default_nettype none +module Inc16_tb(); + + // IN,OUT + reg [15:0] in; + wire [15:0] out; + + // Part + Inc16 INC16( + .in(in), + .out(out) + ); + + // Compare + wire [15:0] out_cmp; + assign out_cmp = in+1; + + reg fail = 0; + reg [15:0] n=0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: in=%16b, out=%16b",in,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("Inc16_tb.vcd"); + $dumpvars(0, Inc16_tb); + + $display("------------------------"); + $display("Testbench: Inc16"); + + in=0;check(); + in=16'b1111111111111111;check(); + + for (n=0; n<1000;n=n+1) + begin + in=$random; + check(); + end + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/02_Boolean_Arithmetic/04_Inc16/Include.v b/02_Boolean_Arithmetic/04_Inc16/Include.v new file mode 100644 index 0000000..09fb359 --- /dev/null +++ b/02_Boolean_Arithmetic/04_Inc16/Include.v @@ -0,0 +1,24 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + diff --git a/02_Boolean_Arithmetic/04_Inc16/apio.ini b/02_Boolean_Arithmetic/04_Inc16/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/02_Boolean_Arithmetic/04_Inc16/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/02_Boolean_Arithmetic/05_ALU/ALU_tb.gtkw b/02_Boolean_Arithmetic/05_ALU/ALU_tb.gtkw new file mode 100644 index 0000000..8c651c5 --- /dev/null +++ b/02_Boolean_Arithmetic/05_ALU/ALU_tb.gtkw @@ -0,0 +1,48 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 17:33:08 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/05_ALU/ALU_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 17:32:45 2022" +[dumpfile_size] 6961131 +[savefile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/05_ALU/ALU_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -1 -1 +*-1.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 258 +@200 +-IN +@22 +ALU_tb.x[15:0] +ALU_tb.y[15:0] +@28 +ALU_tb.zx +ALU_tb.nx +ALU_tb.zy +ALU_tb.ny +ALU_tb.f +ALU_tb.no +@200 +-OUT +@22 +ALU_tb.out[15:0] +@28 +ALU_tb.zr +ALU_tb.ng +@200 +-CMP +@22 +ALU_tb.out_cmp[15:0] +@28 +ALU_tb.zr_cmp +ALU_tb.ng_cmp +@201 +-Test +@28 +ALU_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/02_Boolean_Arithmetic/05_ALU/ALU_tb.v b/02_Boolean_Arithmetic/05_ALU/ALU_tb.v new file mode 100644 index 0000000..8904aa1 --- /dev/null +++ b/02_Boolean_Arithmetic/05_ALU/ALU_tb.v @@ -0,0 +1,81 @@ +`default_nettype none +module ALU_tb(); + + // IN,OUT + reg [15:0] x,y; + reg zx,nx,zy,ny,f,no; + wire [15:0] out; + wire zr,ng; + + // Part + ALU ALU( + .x(x), + .y(y), + .zx(zx), + .nx(nx), + .zy(zy), + .ny(ny), + .f(f), + .no(no), + .out(out), + .zr(zr), + .ng(ng) + ); + + // Compare + wire [15:0] xx,yy,out_cmp; + wire zr_cmp,ng_cmp; + assign xx = nx?(zx?~0:~x):(zx?0:x); + assign yy = ny?(zy?~0:~y):(zy?0:y); + assign out_cmp= no?(f?~(xx+yy):~(xx&yy)):(f?(xx+yy):(xx&yy)); + assign zr_cmp = (out==0); + assign ng_cmp = out[15]; + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if ((out != out_cmp) || (zr != zr_cmp) || (ng != ng_cmp)) + begin + $display("FAIL: x=%16b, y=%16b, zx=%1b, nx=%1b, zy=%1b, ny=%1b, f=%1b, no=%1b, out=%16b, zr=%1b, ng=%1b",x,y,zx,nx,zy,ny,f,no,out,zr,ng); + fail=1; + end + endtask + + initial begin + $dumpfile("ALU_tb.vcd"); + $dumpvars(0, ALU_tb); + + $display("------------------------"); + $display("Testbench: ALU"); + + for (n=0; n<100;n=n+1) + begin + x=$random; + y=$random; + zx=1;nx=0;zy=1;ny=0;f=1;no=0;check();// 0 + zx=1;nx=1;zy=1;ny=1;f=1;no=1;check();// 1 + zx=1;nx=1;zy=1;ny=0;f=1;no=0;check();// -1 + zx=0;nx=0;zy=1;ny=1;f=0;no=0;check();// x + zx=1;nx=1;zy=0;ny=0;f=0;no=0;check();// y + zx=0;nx=0;zy=1;ny=1;f=0;no=1;check();// !x + zx=1;nx=1;zy=0;ny=0;f=0;no=1;check();// !y + zx=0;nx=0;zy=1;ny=1;f=1;no=1;check();// -x + zx=1;nx=1;zy=0;ny=0;f=1;no=1;check();// -y + zx=0;nx=1;zy=1;ny=1;f=1;no=1;check();// x+1 + zx=1;nx=1;zy=0;ny=1;f=1;no=1;check();// y+1 + zx=0;nx=0;zy=1;ny=1;f=1;no=0;check();// x-1 + zx=1;nx=1;zy=0;ny=0;f=1;no=0;check();// y-1 + zx=0;nx=0;zy=0;ny=0;f=1;no=0;check();// x+y + zx=0;nx=1;zy=0;ny=0;f=1;no=1;check();// x-y + zx=0;nx=0;zy=0;ny=1;f=1;no=1;check();// y-x + zx=0;nx=0;zy=0;ny=0;f=0;no=0;check();// x&y + zx=0;nx=1;zy=0;ny=1;f=0;no=1;check();// x|y + end + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/02_Boolean_Arithmetic/05_ALU/Include.v b/02_Boolean_Arithmetic/05_ALU/Include.v new file mode 100644 index 0000000..09fb359 --- /dev/null +++ b/02_Boolean_Arithmetic/05_ALU/Include.v @@ -0,0 +1,24 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + diff --git a/02_Boolean_Arithmetic/05_ALU/apio.ini b/02_Boolean_Arithmetic/05_ALU/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/02_Boolean_Arithmetic/05_ALU/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/02_Boolean_Arithmetic/ALU.v b/02_Boolean_Arithmetic/ALU.v new file mode 100644 index 0000000..844ae44 --- /dev/null +++ b/02_Boolean_Arithmetic/ALU.v @@ -0,0 +1,41 @@ +/** + * The ALU (Arithmetic Logic Unit). + * Computes one of the following functions: + * x+y, x-y, y-x, 0, 1, -1, x, y, -x, -y, !x, !y, + * x+1, y+1, x-1, y-1, x&y, x|y on two 16-bit inputs, + * according to 6 input bits denoted zx,nx,zy,ny,f,no. + * In addition, the ALU computes two 1-bit outputs: + * if the ALU output == 0, zr is set to 1; otherwise zr is set to 0; + * if the ALU output < 0, ng is set to 1; otherwise ng is set to 0. + */ + +// Implementation: the ALU logic manipulates the x and y inputs +// and operates on the resulting values, as follows: +// if (zx == 1) set x = 0 // 16-bit constant +// if (nx == 1) set x = !x // bitwise not +// if (zy == 1) set y = 0 // 16-bit constant +// if (ny == 1) set y = !y // bitwise not +// if (f == 1) set out = x + y // integer 2's complement addition +// if (f == 0) set out = x & y // bitwise and +// if (no == 1) set out = !out // bitwise not +// if (out == 0) set zr = 1 +// if (out < 0) set ng = 1 + +`default_nettype none +module ALU( + input [15:0] x, // input x (16 bit) + input [15:0] y, // input y (16 bit) + input zx, // zero the x input? + input nx, // negate the x input? + input zy, // zero the y input? + input ny, // negate the y input? + input f, // compute out = x + y (if 1) or x & y (if 0) + input no, // negate the out output? + output [15:0] out, // 16-bit output + output zr, // 1 if (out == 0), 0 otherwise + output ng // 1 if (out < 0), 0 otherwise +); + + // Put your code here: + +endmodule diff --git a/02_Boolean_Arithmetic/Add16.v b/02_Boolean_Arithmetic/Add16.v new file mode 100644 index 0000000..afa4243 --- /dev/null +++ b/02_Boolean_Arithmetic/Add16.v @@ -0,0 +1,16 @@ +/** + * Adds two 16-bit values. + * The most significant carry bit is ignored. + * out = a + b (16 bit) + */ + +`default_nettype none +module Add16( + input [15:0] a, + input [15:0] b, + output [15:0] out +); + + // Put your code here: + +endmodule diff --git a/02_Boolean_Arithmetic/FullAdder.v b/02_Boolean_Arithmetic/FullAdder.v new file mode 100644 index 0000000..3c91dff --- /dev/null +++ b/02_Boolean_Arithmetic/FullAdder.v @@ -0,0 +1,16 @@ +/** + * Computes the sum of three bits. + */ + +`default_nettype none +module FullAdder( + input a, //1-bit input + input b, //1-bit input + input c, //1-bit input + output sum, //Right bit of a + b + c + output carry //Left bit of a + b + c +); + + // Put your code here: + +endmodule diff --git a/02_Boolean_Arithmetic/HalfAdder.v b/02_Boolean_Arithmetic/HalfAdder.v new file mode 100644 index 0000000..c7e3d47 --- /dev/null +++ b/02_Boolean_Arithmetic/HalfAdder.v @@ -0,0 +1,15 @@ +/** + * Computes the sum of two bits. + */ + +`default_nettype none +module HalfAdder( + input a, //1-bit input + input b, //1-bit inpur + output sum, //Right bit of a + b + output carry //Lef bit of a + b +); + + // Put your code here: + +endmodule diff --git a/02_Boolean_Arithmetic/Inc16.v b/02_Boolean_Arithmetic/Inc16.v new file mode 100644 index 0000000..ea944b5 --- /dev/null +++ b/02_Boolean_Arithmetic/Inc16.v @@ -0,0 +1,14 @@ +/** + * 16-bit incrementer: + * out = in + 1 (arithmetic addition) + */ + +`default_nettype none +module Inc16( + input [15:0] in, + output [15:0] out +); + + // Put your code here: + +endmodule diff --git a/02_Boolean_Arithmetic/Readme.md b/02_Boolean_Arithmetic/Readme.md new file mode 100644 index 0000000..16edd62 --- /dev/null +++ b/02_Boolean_Arithmetic/Readme.md @@ -0,0 +1,26 @@ +# 02 Arithmetic Logic + +Proceed and implement the chips `HalfAdder`, `FullAdder`, `Add16`, `Inc16` and `ALU`. + +Keep in mind the following remarks: + +* in order to use the chips implemented in project `01_Boolean_Logic`, they must be listed in the file `Include.v`, which can be found in every subfolder. + +* you dan use a `Buffer` to split the signal wires. e.g. `ng` signal of ALU can be derived from out[15]. + +* clear cache every time you edit and change your implementation in the verilog file `.v`. + +* test your chip implementation with: + + ``` + $ cd + $ apio clean + $ apio sim + ``` + +* the chip `HalfAdder` can be uploaded to iCE40HX1K-EVB and tested using BUT1/2 and LED1/2. Keep in mind, that due to pull up resistors at the buttons, the signals appear inverted: + + | pin | function | + | ------ | --------------------------------------------------- | + | LED1/2 | =0 led is off, =1 led is on | + | BUT1/2 | =0 button is pressed down, =1 button is released up | \ No newline at end of file diff --git a/03_Sequential_Logic/00_DFF/DFF_tb.gtkw b/03_Sequential_Logic/00_DFF/DFF_tb.gtkw new file mode 100644 index 0000000..48bc620 --- /dev/null +++ b/03_Sequential_Logic/00_DFF/DFF_tb.gtkw @@ -0,0 +1,36 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 17:41:19 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/00_DFF/DFF_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 17:41:04 2022" +[dumpfile_size] 23490 +[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/00_DFF/DFF_tb.gtkw" +[timestart] 0 +[size] 1699 600 +[pos] -1 -1 +*-2.536562 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 100 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@28 +DFF_tb.clk +@200 +-IN +@28 +DFF_tb.in +@200 +-OUT +@28 +DFF_tb.out +@200 +-CMP +@28 +DFF_tb.out_cmp +@201 +-Test +@28 +DFF_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/03_Sequential_Logic/00_DFF/DFF_tb.v b/03_Sequential_Logic/00_DFF/DFF_tb.v new file mode 100644 index 0000000..7f4a618 --- /dev/null +++ b/03_Sequential_Logic/00_DFF/DFF_tb.v @@ -0,0 +1,52 @@ +`default_nettype none +module DFF_tb(); + + // IN,OUT + reg clk = 1; + reg in; + wire out; + + // Part + DFF DFF( + .clk(clk), + .in(in), + .out(out) + ); + + // Compare + always #1 clk=~clk; + always @(posedge clk) + in <= $random; + + reg out_cmp; + always @(posedge clk) + out_cmp <= in; + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: clk=%1b, in=%1b, out=%1b",clk,in,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("DFF_tb.vcd"); + $dumpvars(0, DFF_tb); + + $display("------------------------"); + $display("Testbench: DFF"); + + for (n=0; n<1000;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/03_Sequential_Logic/00_DFF/Include.v b/03_Sequential_Logic/00_DFF/Include.v new file mode 100644 index 0000000..7ecc449 --- /dev/null +++ b/03_Sequential_Logic/00_DFF/Include.v @@ -0,0 +1,31 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift8L.v" +`include "../../03_Sequential_Logic/BitShift9R.v" diff --git a/03_Sequential_Logic/00_DFF/apio.ini b/03_Sequential_Logic/00_DFF/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/03_Sequential_Logic/00_DFF/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/03_Sequential_Logic/01_Bit/Bit_tb.gtkw b/03_Sequential_Logic/01_Bit/Bit_tb.gtkw new file mode 100644 index 0000000..f8883dd --- /dev/null +++ b/03_Sequential_Logic/01_Bit/Bit_tb.gtkw @@ -0,0 +1,38 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 17:43:28 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/01_Bit/Bit_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 17:42:58 2022" +[dumpfile_size] 29689 +[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/01_Bit/Bit_tb.gtkw" +[timestart] 0 +[size] 1709 600 +[pos] -1 -1 +*-2.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] Bit_tb. +[sst_width] 281 +[signals_width] 100 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@28 +Bit_tb.clk +@200 +-IN +@28 +Bit_tb.in +Bit_tb.load +@200 +-OUT +@28 +Bit_tb.out +@200 +-CMP +@28 +Bit_tb.out_cmp +@201 +-Test +@28 +Bit_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/03_Sequential_Logic/01_Bit/Bit_tb.v b/03_Sequential_Logic/01_Bit/Bit_tb.v new file mode 100644 index 0000000..8d66522 --- /dev/null +++ b/03_Sequential_Logic/01_Bit/Bit_tb.v @@ -0,0 +1,53 @@ +`default_nettype none +module Bit_tb(); + + // IN,OUT + reg clk = 1; + reg in,load; + wire out; + + // Part + Bit BIT( + .clk(clk), + .in(in), + .load(load), + .out(out) + ); + + // Compare + always #1 clk=~clk; + always @(posedge clk) begin + in <= $random; + load <= $random; + end + reg out_cmp; + always @(posedge clk) + out_cmp <= (load?in:out); + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: clk=%1b, in=%1b, load=%1b, out=%1b",clk,in,load,out); + fail=1; + end + endtask + + initial begin + $dumpfile("Bit_tb.vcd"); + $dumpvars(0, Bit_tb); + + $display("------------------------"); + $display("Testbench: Bit"); + + for (n=0; n<1000;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/03_Sequential_Logic/01_Bit/Include.v b/03_Sequential_Logic/01_Bit/Include.v new file mode 100644 index 0000000..7ecc449 --- /dev/null +++ b/03_Sequential_Logic/01_Bit/Include.v @@ -0,0 +1,31 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift8L.v" +`include "../../03_Sequential_Logic/BitShift9R.v" diff --git a/03_Sequential_Logic/01_Bit/apio.ini b/03_Sequential_Logic/01_Bit/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/03_Sequential_Logic/01_Bit/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/03_Sequential_Logic/02_Register/Include.v b/03_Sequential_Logic/02_Register/Include.v new file mode 100644 index 0000000..7ecc449 --- /dev/null +++ b/03_Sequential_Logic/02_Register/Include.v @@ -0,0 +1,31 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift8L.v" +`include "../../03_Sequential_Logic/BitShift9R.v" diff --git a/03_Sequential_Logic/02_Register/Register_tb.gtkw b/03_Sequential_Logic/02_Register/Register_tb.gtkw new file mode 100644 index 0000000..76f23f3 --- /dev/null +++ b/03_Sequential_Logic/02_Register/Register_tb.gtkw @@ -0,0 +1,38 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 17:44:03 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/02_Register/Register_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 17:43:41 2022" +[dumpfile_size] 182432 +[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/02_Register/Register_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -1 -1 +*-1.000000 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 258 +@28 +Register_tb.clk +@200 +-IN +@22 +Register_tb.in[15:0] +@28 +Register_tb.load +@200 +-OUT +@22 +Register_tb.out[15:0] +@200 +-CMP +@22 +Register_tb.out_cmp[15:0] +@200 +-Test +@28 +Register_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/03_Sequential_Logic/02_Register/Register_tb.v b/03_Sequential_Logic/02_Register/Register_tb.v new file mode 100644 index 0000000..7bdd28e --- /dev/null +++ b/03_Sequential_Logic/02_Register/Register_tb.v @@ -0,0 +1,53 @@ +`default_nettype none +module Register_tb(); + + // IN,OUT + reg clk = 1; + reg [15:0] in; + reg load; + wire [15:0] out; + + // Part + Register REGISTER( + .clk(clk), + .in(in), + .load(load), + .out(out) + ); + + // Compare + always #1 clk=~clk; + always @(posedge clk) begin + in <= $random; + load <= $random; + end + reg [15:0] out_cmp; + always @(posedge clk) + out_cmp <= (load?in:out); + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: clk=%1b, in=%16b, load=%1b, out=%16b",clk,in,load,out); + fail=1; + end + endtask + + initial begin + $dumpfile("Register_tb.vcd"); + $dumpvars(0, Register_tb); + + $display("------------------------"); + $display("Testbench: Register"); + + for (n=0; n<1000;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/03_Sequential_Logic/02_Register/apio.ini b/03_Sequential_Logic/02_Register/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/03_Sequential_Logic/02_Register/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/03_Sequential_Logic/03_PC/Include.v b/03_Sequential_Logic/03_PC/Include.v new file mode 100644 index 0000000..7ecc449 --- /dev/null +++ b/03_Sequential_Logic/03_PC/Include.v @@ -0,0 +1,31 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift8L.v" +`include "../../03_Sequential_Logic/BitShift9R.v" diff --git a/03_Sequential_Logic/03_PC/PC_tb.gtkw b/03_Sequential_Logic/03_PC/PC_tb.gtkw new file mode 100644 index 0000000..3eb4763 --- /dev/null +++ b/03_Sequential_Logic/03_PC/PC_tb.gtkw @@ -0,0 +1,40 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 17:44:56 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 17:44:20 2022" +[dumpfile_size] 627445 +[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -1 -1 +*-3.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 258 +@28 +PC_tb.clk +@200 +-IN +@22 +PC_tb.in[15:0] +@28 +PC_tb.load +PC_tb.inc +PC_tb.reset +@200 +-OUT +@22 +PC_tb.out[15:0] +@200 +-CMP +@22 +PC_tb.out_cmp[15:0] +@200 +-Test +@29 +PC_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/03_Sequential_Logic/03_PC/PC_tb.v b/03_Sequential_Logic/03_PC/PC_tb.v new file mode 100644 index 0000000..fbf87d3 --- /dev/null +++ b/03_Sequential_Logic/03_PC/PC_tb.v @@ -0,0 +1,60 @@ +`default_nettype none +module PC_tb(); + + // IN,OUT + reg clk=1; + reg [15:0] in; + reg load,inc,reset; + wire [15:0] out; + + // Part + PC PC( + .clk(clk), + .in(in), + .load(load), + .inc(inc), + .reset(reset), + .out(out) + ); + + // Simulate + always #1 clk=~clk; + always @(posedge clk) begin + in <= $random; + reset <= (n==10) || (n==24) || (n==44); + inc <= $random; + load <= $random; + end + + // Compare + reg [15:0] out_cmp; + always @(posedge clk) + out_cmp <= (reset?0:(load?in:(inc?out+1:out))); + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: clk=%1b, in=%16b, load=%1b, inc=%1b, reset=%1b, out=%16b",clk,in,load,inc,reset,out); + fail=1; + end + endtask + + initial begin + $dumpfile("PC_tb.vcd"); + $dumpvars(0, PC_tb); + + $display("------------------------"); + $display("Testbench: PC"); + + for (n=0; n<1000;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/03_Sequential_Logic/03_PC/apio.ini b/03_Sequential_Logic/03_PC/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/03_Sequential_Logic/03_PC/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/03_Sequential_Logic/04_RAM512/Include.v b/03_Sequential_Logic/04_RAM512/Include.v new file mode 100644 index 0000000..7466ab1 --- /dev/null +++ b/03_Sequential_Logic/04_RAM512/Include.v @@ -0,0 +1,33 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/RAM256.v" +`include "../../03_Sequential_Logic/RAM512.v" +`include "../../03_Sequential_Logic/BitShift8L.v" +`include "../../03_Sequential_Logic/BitShift9R.v" diff --git a/03_Sequential_Logic/04_RAM512/PC_tb.gtkw b/03_Sequential_Logic/04_RAM512/PC_tb.gtkw new file mode 100644 index 0000000..3eb4763 --- /dev/null +++ b/03_Sequential_Logic/04_RAM512/PC_tb.gtkw @@ -0,0 +1,40 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 17:44:56 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 17:44:20 2022" +[dumpfile_size] 627445 +[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -1 -1 +*-3.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 258 +@28 +PC_tb.clk +@200 +-IN +@22 +PC_tb.in[15:0] +@28 +PC_tb.load +PC_tb.inc +PC_tb.reset +@200 +-OUT +@22 +PC_tb.out[15:0] +@200 +-CMP +@22 +PC_tb.out_cmp[15:0] +@200 +-Test +@29 +PC_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/03_Sequential_Logic/04_RAM512/RAM512_tb.gtkw b/03_Sequential_Logic/04_RAM512/RAM512_tb.gtkw new file mode 100644 index 0000000..91d5495 --- /dev/null +++ b/03_Sequential_Logic/04_RAM512/RAM512_tb.gtkw @@ -0,0 +1,39 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Sat Dec 31 10:22:59 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/04_RAM512/RAM512_tb.vcd" +[dumpfile_mtime] "Sat Dec 31 10:22:49 2022" +[dumpfile_size] 259286 +[savefile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/04_RAM512/RAM512_tb.gtkw" +[timestart] 0 +[size] 1700 626 +[pos] -1 -1 +*-8.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 142 +@200 +-IN +@28 +RAM512_tb.clk +@22 +RAM512_tb.address[8:0] +RAM512_tb.in[15:0] +@28 +RAM512_tb.load +@200 +-OUT +@22 +RAM512_tb.out[15:0] +@200 +-CMP +@22 +RAM512_tb.out_cmp[15:0] +@200 +-Test +@29 +RAM512_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/03_Sequential_Logic/04_RAM512/RAM512_tb.v b/03_Sequential_Logic/04_RAM512/RAM512_tb.v new file mode 100644 index 0000000..28c4453 --- /dev/null +++ b/03_Sequential_Logic/04_RAM512/RAM512_tb.v @@ -0,0 +1,60 @@ +`default_nettype none +module RAM512_tb(); + + // IN,OUT + reg clk=1; + reg [15:0] in; + reg [8:0] address; + reg load; + wire [15:0] out; + + // Part + RAM512 RAM512( + .clk(clk), + .address(address), + .in(in), + .load(load), + .out(out) + ); + + // Simulate + always #1 clk=~clk; + always @(posedge clk) begin + in <= $random; + address <= n; + load <= (n<512); + end + + // Compare + reg [15:0] regRAM [0:511]; + always @(posedge clk) + if (load) regRAM[address[8:0]] <= in; + wire[15:0] out_cmp = regRAM[address[8:0]]; + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: clk=%1b, address=%9b, in=%16b, load=%1b, out=%16b",clk,address,in,load,out); + fail=1; + end + endtask + + initial begin + $dumpfile("RAM512_tb.vcd"); + $dumpvars(0, RAM512_tb); + + $display("------------------------"); + $display("Testbench: RAM512"); + + for (n=0; n<1000;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/03_Sequential_Logic/04_RAM512/apio.ini b/03_Sequential_Logic/04_RAM512/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/03_Sequential_Logic/04_RAM512/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/03_Sequential_Logic/05_RAM3840/Include.v b/03_Sequential_Logic/05_RAM3840/Include.v new file mode 100644 index 0000000..8ce9be7 --- /dev/null +++ b/03_Sequential_Logic/05_RAM3840/Include.v @@ -0,0 +1,34 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/RAM256.v" +`include "../../03_Sequential_Logic/RAM512.v" +`include "../../03_Sequential_Logic/RAM3840.v" +`include "../../03_Sequential_Logic/BitShift8L.v" +`include "../../03_Sequential_Logic/BitShift9R.v" diff --git a/03_Sequential_Logic/05_RAM3840/PC_tb.gtkw b/03_Sequential_Logic/05_RAM3840/PC_tb.gtkw new file mode 100644 index 0000000..3eb4763 --- /dev/null +++ b/03_Sequential_Logic/05_RAM3840/PC_tb.gtkw @@ -0,0 +1,40 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 17:44:56 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 17:44:20 2022" +[dumpfile_size] 627445 +[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -1 -1 +*-3.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 258 +@28 +PC_tb.clk +@200 +-IN +@22 +PC_tb.in[15:0] +@28 +PC_tb.load +PC_tb.inc +PC_tb.reset +@200 +-OUT +@22 +PC_tb.out[15:0] +@200 +-CMP +@22 +PC_tb.out_cmp[15:0] +@200 +-Test +@29 +PC_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/03_Sequential_Logic/05_RAM3840/RAM3840_tb.gtkw b/03_Sequential_Logic/05_RAM3840/RAM3840_tb.gtkw new file mode 100644 index 0000000..bdb2bf2 --- /dev/null +++ b/03_Sequential_Logic/05_RAM3840/RAM3840_tb.gtkw @@ -0,0 +1,40 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Sat Dec 31 11:27:32 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/05_RAM3840/RAM3840_tb.vcd" +[dumpfile_mtime] "Sat Dec 31 11:26:49 2022" +[dumpfile_size] 19516827 +[savefile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/05_RAM3840/RAM3840_tb.gtkw" +[timestart] 0 +[size] 1616 559 +[pos] -1 -1 +*-11.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 117 +@28 +RAM3840_tb.clk +@200 +-IN +@22 +RAM3840_tb.address[11:0] +@29 +RAM3840_tb.load +@22 +RAM3840_tb.in[15:0] +@200 +-OUT +@22 +RAM3840_tb.out[15:0] +@200 +-CMP +@22 +RAM3840_tb.out_cmp[15:0] +@200 +-Test +@28 +RAM3840_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/03_Sequential_Logic/05_RAM3840/RAM3840_tb.v b/03_Sequential_Logic/05_RAM3840/RAM3840_tb.v new file mode 100644 index 0000000..182d0bb --- /dev/null +++ b/03_Sequential_Logic/05_RAM3840/RAM3840_tb.v @@ -0,0 +1,60 @@ +`default_nettype none +module RAM3840_tb(); + + // IN,OUT + reg clk=1; + reg [15:0] in; + reg [11:0] address; + reg load; + wire [15:0] out; + + // Part + RAM3840 RAM3840( + .clk(clk), + .address(address), + .in(in), + .load(load), + .out(out) + ); + + // Simulate + always #1 clk=~clk; + always @(posedge clk) begin + in <= $random; + address <= (n<3840)?n:n-3840; + load <= (n<3840); + end + + // Compare + reg [15:0] regRAM [0:3839]; + always @(posedge clk) + if (load) regRAM[address[11:0]] <= in; + wire[15:0] out_cmp = regRAM[address[11:0]]; + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: clk=%1b, address=%12b, in=%16b, load=%1b, out=%16b",clk,address,in,load,out); + fail=1; + end + endtask + + initial begin + $dumpfile("RAM3840_tb.vcd"); + $dumpvars(0, RAM3840_tb); + + $display("------------------------"); + $display("Testbench: RAM3840"); + + for (n=0; n<2*3840;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/03_Sequential_Logic/05_RAM3840/apio.ini b/03_Sequential_Logic/05_RAM3840/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/03_Sequential_Logic/05_RAM3840/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/03_Sequential_Logic/06_BitShift8L/BitShift8L_tb.gtkw b/03_Sequential_Logic/06_BitShift8L/BitShift8L_tb.gtkw new file mode 100644 index 0000000..1dc1557 --- /dev/null +++ b/03_Sequential_Logic/06_BitShift8L/BitShift8L_tb.gtkw @@ -0,0 +1,40 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 17:45:21 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/04_BitShift8L/BitShift8L_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 17:45:11 2022" +[dumpfile_size] 84704 +[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/04_BitShift8L/BitShift8L_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -1 -1 +*-3.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 150 +[sst_expanded] 1 +[sst_vpaned_height] 259 +@200 +-IN +@28 +BitShift8L_tb.clk +@22 +BitShift8L_tb.in[7:0] +@28 +BitShift8L_tb.inLSB +BitShift8L_tb.load +BitShift8L_tb.shift +@200 +-OUT +@22 +BitShift8L_tb.out[7:0] +@200 +-CMP +@22 +BitShift8L_tb.out_cmp[7:0] +@201 +-Test +@28 +BitShift8L_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/03_Sequential_Logic/06_BitShift8L/BitShift8L_tb.v b/03_Sequential_Logic/06_BitShift8L/BitShift8L_tb.v new file mode 100644 index 0000000..59c0346 --- /dev/null +++ b/03_Sequential_Logic/06_BitShift8L/BitShift8L_tb.v @@ -0,0 +1,61 @@ +`default_nettype none +module BitShift8L_tb(); + + // IN,OUT + reg clk=1; + reg [7:0] in; + reg load,shift,inLSB; + wire [7:0] out; + + // Part + BitShift8L BITSHIFT8L( + .clk(clk), + .in(in), + .inLSB(inLSB), + .load(load), + .shift(shift), + .out(out) + ); + + // Simulate + always #1 clk=~clk; + always @(posedge clk) begin + in <= $random; + shift <= (n==0) || ((n>20) && (n<50)); + inLSB <= $random; + load <= (n==10); + end + + // Compare + reg [7:0] out_cmp; + always @(posedge clk) + out_cmp <= load?in:(shift?(out_cmp<<1)|inLSB:out_cmp); + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: clk=%1b, in=%8b, load=%1b, shift=%1b, out=%8b",clk,in,inLSB,load,shift,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("BitShift8L_tb.vcd"); + $dumpvars(0, BitShift8L_tb); + + $display("------------------------"); + $display("Testbench: BitShift8L"); + + for (n=0; n<1000;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/03_Sequential_Logic/06_BitShift8L/Include.v b/03_Sequential_Logic/06_BitShift8L/Include.v new file mode 100644 index 0000000..7ecc449 --- /dev/null +++ b/03_Sequential_Logic/06_BitShift8L/Include.v @@ -0,0 +1,31 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift8L.v" +`include "../../03_Sequential_Logic/BitShift9R.v" diff --git a/03_Sequential_Logic/06_BitShift8L/apio.ini b/03_Sequential_Logic/06_BitShift8L/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/03_Sequential_Logic/06_BitShift8L/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/03_Sequential_Logic/07_BitShift9R/BitShift10R_tb.gtkw b/03_Sequential_Logic/07_BitShift9R/BitShift10R_tb.gtkw new file mode 100644 index 0000000..16ad57a --- /dev/null +++ b/03_Sequential_Logic/07_BitShift9R/BitShift10R_tb.gtkw @@ -0,0 +1,38 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Mon Nov 28 10:00:33 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/05_BitShift10R/BitShift10R_tb.vcd" +[dumpfile_mtime] "Mon Nov 28 09:59:44 2022" +[dumpfile_size] 98425 +[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/05_BitShift10R/BitShift10R_tb.gtkw" +[timestart] 0 +[size] 1000 600 +[pos] -1 -1 +*-5.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 150 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@200 +-IN +@28 +BitShift10R_tb.clk +@23 +BitShift10R_tb.in[9:0] +@28 +BitShift10R_tb.inMSB +BitShift10R_tb.load +BitShift10R_tb.shift +@200 +-OUT +@22 +BitShift10R_tb.out[9:0] +@200 +-CMP +@22 +BitShift10R_tb.out_cmp[9:0] +@28 +BitShift10R_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/03_Sequential_Logic/07_BitShift9R/BitShift9R_tb.gtkw b/03_Sequential_Logic/07_BitShift9R/BitShift9R_tb.gtkw new file mode 100644 index 0000000..1170bd0 --- /dev/null +++ b/03_Sequential_Logic/07_BitShift9R/BitShift9R_tb.gtkw @@ -0,0 +1,40 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 22 17:45:42 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/05_BitShift9R/BitShift9R_tb.vcd" +[dumpfile_mtime] "Thu Dec 22 17:45:34 2022" +[dumpfile_size] 91711 +[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/05_BitShift9R/BitShift9R_tb.gtkw" +[timestart] 0 +[size] 1712 730 +[pos] -1 -1 +*-4.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 150 +[sst_expanded] 1 +[sst_vpaned_height] 177 +@200 +-IN +@28 +BitShift9R_tb.clk +BitShift9R_tb.inMSB +@22 +BitShift9R_tb.in[8:0] +@28 +BitShift9R_tb.shift +BitShift9R_tb.load +@200 +-OUT +@22 +BitShift9R_tb.out[8:0] +@200 +-CMP +@22 +BitShift9R_tb.out_cmp[8:0] +@201 +-Test +@28 +BitShift9R_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/03_Sequential_Logic/07_BitShift9R/BitShift9R_tb.v b/03_Sequential_Logic/07_BitShift9R/BitShift9R_tb.v new file mode 100644 index 0000000..bfbfb8a --- /dev/null +++ b/03_Sequential_Logic/07_BitShift9R/BitShift9R_tb.v @@ -0,0 +1,61 @@ +`default_nettype none +module BitShift9R_tb(); + + // IN,OUT + reg clk=1; + reg [8:0] in; + reg load,shift,inMSB; + wire [8:0] out; + + // Part + BitShift9R BITSHIFT9R( + .clk(clk), + .in(in), + .inMSB(inMSB), + .load(load), + .shift(shift), + .out(out) + ); + + // Simulate + always #1 clk=~clk; + always @(posedge clk) begin + in <= $random; + shift <= (n==0) || ((n>20) && (n<50)); + inMSB <= $random; + load <= (n==10); + end + + // Compare + reg [8:0] out_cmp; + always @(posedge clk) + out_cmp <= load?in:(shift?(out_cmp>>1)|(inMSB<<8):out_cmp); + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if (out != out_cmp) + begin + $display("FAIL: clk=%1b, in=%9b, load=%1b, shift=%1b, out=%9b",clk,in,inMSB,load,shift,out); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("BitShift9R_tb.vcd"); + $dumpvars(0, BitShift9R_tb); + + $display("------------------------"); + $display("Testbench: BitShift9R"); + + for (n=0; n<1000;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/03_Sequential_Logic/07_BitShift9R/Include.v b/03_Sequential_Logic/07_BitShift9R/Include.v new file mode 100644 index 0000000..7ecc449 --- /dev/null +++ b/03_Sequential_Logic/07_BitShift9R/Include.v @@ -0,0 +1,31 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift8L.v" +`include "../../03_Sequential_Logic/BitShift9R.v" diff --git a/03_Sequential_Logic/07_BitShift9R/ShifterR_tb.gtkw b/03_Sequential_Logic/07_BitShift9R/ShifterR_tb.gtkw new file mode 100644 index 0000000..de7d4f5 --- /dev/null +++ b/03_Sequential_Logic/07_BitShift9R/ShifterR_tb.gtkw @@ -0,0 +1,38 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Nov 24 12:29:38 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/07_ShifterR/ShifterR_tb.vcd" +[dumpfile_mtime] "Thu Nov 24 12:28:59 2022" +[dumpfile_size] 67820 +[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/07_ShifterR/ShifterR_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -1 -1 +*-3.000000 14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 150 +[sst_expanded] 1 +[sst_vpaned_height] 259 +@28 +ShifterR_tb.clk +@200 +-IN +@22 +ShifterR_tb.in[9:0] +@28 +ShifterR_tb.inMSB +ShifterR_tb.load +ShifterR_tb.shift +@200 +-OUT +@22 +ShifterR_tb.out[9:0] +@200 +-CMP +@23 +ShifterR_tb.out_cmp[9:0] +@28 +ShifterR_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/03_Sequential_Logic/07_BitShift9R/apio.ini b/03_Sequential_Logic/07_BitShift9R/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/03_Sequential_Logic/07_BitShift9R/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/03_Sequential_Logic/08_blinky/Include.v b/03_Sequential_Logic/08_blinky/Include.v new file mode 100644 index 0000000..10ffa32 --- /dev/null +++ b/03_Sequential_Logic/08_blinky/Include.v @@ -0,0 +1,24 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" diff --git a/03_Sequential_Logic/08_blinky/apio.ini b/03_Sequential_Logic/08_blinky/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/03_Sequential_Logic/08_blinky/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/03_Sequential_Logic/08_blinky/blinky.v b/03_Sequential_Logic/08_blinky/blinky.v new file mode 100644 index 0000000..81379d4 --- /dev/null +++ b/03_Sequential_Logic/08_blinky/blinky.v @@ -0,0 +1,19 @@ +// Test to run on fpga with 100 MHz + +`default_nettype none +module blinky( + input CLK, + output [1:0] LED +); + + wire [15:0] prescaler; + wire clk; + PC PRESCALER(.clk(CLK),.load(1'b0),.in(16'b0),.reset(1'b0),.inc(1'b1),.out(prescaler)); + Buffer CLOCK(.in(prescaler[12]),.out(clk)); + + wire [15:0] counter; + PC COUNTER(.clk(clk),.load(1'b0),.in(16'b0),.reset(1'b0),.inc(1'b1),.out(counter)); + Buffer BUF1(.in(counter[15]),.out(LED[1])); + Buffer BUF2(.in(counter[14]),.out(LED[0])); + +endmodule diff --git a/03_Sequential_Logic/08_blinky/blinky_tb.gtkw b/03_Sequential_Logic/08_blinky/blinky_tb.gtkw new file mode 100644 index 0000000..f4f1f53 --- /dev/null +++ b/03_Sequential_Logic/08_blinky/blinky_tb.gtkw @@ -0,0 +1,26 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Fri Dec 30 09:21:12 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/06_Blinky/blinky_tb.vcd" +[dumpfile_mtime] "Fri Dec 30 09:19:51 2022" +[dumpfile_size] 30570990 +[savefile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/06_Blinky/blinky_tb.gtkw" +[timestart] 0 +[size] 1746 387 +[pos] 46 72 +*-2.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] blinky_tb. +[sst_width] 281 +[signals_width] 180 +[sst_expanded] 1 +[sst_vpaned_height] 58 +@28 +blinky_tb.CLK +@22 +blinky_tb.blinky.prescaler[15:0] +blinky_tb.blinky.counter[15:0] +@29 +blinky_tb.LED[1:0] +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/03_Sequential_Logic/08_blinky/blinky_tb.v b/03_Sequential_Logic/08_blinky/blinky_tb.v new file mode 100644 index 0000000..289d292 --- /dev/null +++ b/03_Sequential_Logic/08_blinky/blinky_tb.v @@ -0,0 +1,24 @@ +`default_nettype none +module blinky_tb(); + + // IN,OUT + reg CLK=1; + wire[1:0] LED; + + // Part + blinky blinky( + .CLK(CLK), + .LED(LED) + ); + + // Simulate + always #1 CLK=~CLK; + + initial begin + $dumpfile("blinky_tb.vcd"); + $dumpvars(0, blinky_tb); + #100000 + $finish; + end + +endmodule diff --git a/03_Sequential_Logic/08_blinky/counter.png b/03_Sequential_Logic/08_blinky/counter.png new file mode 100644 index 0000000..e67aeb9 Binary files /dev/null and b/03_Sequential_Logic/08_blinky/counter.png differ diff --git a/03_Sequential_Logic/08_blinky/iCE40HX1K.pcf b/03_Sequential_Logic/08_blinky/iCE40HX1K.pcf new file mode 100644 index 0000000..4a6f47d --- /dev/null +++ b/03_Sequential_Logic/08_blinky/iCE40HX1K.pcf @@ -0,0 +1,12 @@ +# physical constrain file +# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB +# compare to the schematic of the board and the datasheet of fpga + +set_io CLK 15 # CLK (100 Mhz) + +set_io BUT[0] 41 # BUT1 +set_io BUT[1] 42 # BUT2 + +set_io LED[0] 40 # LED1 +set_io LED[1] 51 # LED2 + diff --git a/03_Sequential_Logic/08_blinky/prescaler.png b/03_Sequential_Logic/08_blinky/prescaler.png new file mode 100644 index 0000000..6f2b320 Binary files /dev/null and b/03_Sequential_Logic/08_blinky/prescaler.png differ diff --git a/03_Sequential_Logic/Bit.v b/03_Sequential_Logic/Bit.v new file mode 100644 index 0000000..17befc5 --- /dev/null +++ b/03_Sequential_Logic/Bit.v @@ -0,0 +1,17 @@ +/** + * 1-bit register: + * If load[t] == 1 then out[t+1] = in[t] + * else out does not change (out[t+1] = out[t]) + */ + +`default_nettype none +module Bit( + input clk, + input in, + input load, + output out +); + + // Put your code here: + +endmodule diff --git a/03_Sequential_Logic/BitShift8L.v b/03_Sequential_Logic/BitShift8L.v new file mode 100644 index 0000000..c79d81d --- /dev/null +++ b/03_Sequential_Logic/BitShift8L.v @@ -0,0 +1,20 @@ +/** +* 8-bit Shiftregister (shifts to left) +* if (load == 1) out[t+1] = in[t] +* else if (shift == 1) out[t+1] = out[t]<<1 | inLSB +* (shift one position to left and insert inLSB as least significant bit) +*/ + +`default_nettype none +module BitShift8L( + input clk, + input [7:0] in, + input inLSB, + input load, + input shift, + output [7:0] out +); + + // Put your code here: + +endmodule diff --git a/03_Sequential_Logic/BitShift9R.v b/03_Sequential_Logic/BitShift9R.v new file mode 100644 index 0000000..a3f71c7 --- /dev/null +++ b/03_Sequential_Logic/BitShift9R.v @@ -0,0 +1,20 @@ +/** +* 10 bit Shiftregister (shifts to right) +* if (load == 1) out[t+1] = in[t] +* else if (shift == 1) out[t+1] = out[t]>>1 | (inMSB<<9) +* (shift one position to right and insert inMSB as most significant bit) +*/ + +`default_nettype none +module BitShift9R( + input clk, + input [8:0] in, + input inMSB, + input load, + input shift, + output [8:0] out +); + + // Put your code here: + +endmodule diff --git a/03_Sequential_Logic/DFF.v b/03_Sequential_Logic/DFF.v new file mode 100644 index 0000000..d2f6a6b --- /dev/null +++ b/03_Sequential_Logic/DFF.v @@ -0,0 +1,20 @@ +/** +* Data-Flip-Flop +* out[t+1] = in[t] +*/ + +`default_nettype none +module DFF( + input clk, + input in, + output out +); + + // No need to implement this chip + // This chip is implemented in verilog using reg-variables + reg out; + always @(posedge clk) + if (in) out <= 1'b1; + else out <= 1'b0; + +endmodule diff --git a/03_Sequential_Logic/PC.v b/03_Sequential_Logic/PC.v new file mode 100644 index 0000000..34a7d54 --- /dev/null +++ b/03_Sequential_Logic/PC.v @@ -0,0 +1,21 @@ +/** + * A 16-bit counter with load and reset control bits. + * if (reset[t] == 1) out[t+1] = 0 + * else if (load[t] == 1) out[t+1] = in[t] + * else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition) + * else out[t+1] = out[t] + */ + +`default_nettype none +module PC( + input clk, + input [15:0] in, + input load, + input inc, + input reset, + output [15:0] out +); + + // Put your code here: + +endmodule diff --git a/03_Sequential_Logic/RAM256.v b/03_Sequential_Logic/RAM256.v new file mode 100644 index 0000000..25431f0 --- /dev/null +++ b/03_Sequential_Logic/RAM256.v @@ -0,0 +1,24 @@ +/** +* RAM256 implements 256 Bytes of RAM addressed from 0 - 255 +* out = M[address] +* if (load =i= 1) M[address][t+1] = in[t] +*/ + +`default_nettype none +module RAM256( + input clk, + input [7:0] address, + input [15:0] in, + input load, + output [15:0] out +); + + // No need to implement this chip + // RAM is implemented using BRAM of iCE40 + reg [15:0] regRAM [0:255]; + always @(posedge clk) + if (load) regRAM[address[7:0]] <= in; + + assign out = regRAM[address[7:0]]; + +endmodule diff --git a/03_Sequential_Logic/RAM3840.v b/03_Sequential_Logic/RAM3840.v new file mode 100644 index 0000000..9eb4f4f --- /dev/null +++ b/03_Sequential_Logic/RAM3840.v @@ -0,0 +1,18 @@ +/** +* RAM3840 implements 3840 Bytes of RAM addressed from 0 - 3839 +* out = M[address] +* if (load =i= 1) M[address][t+1] = in[t] +*/ + +`default_nettype none +module RAM3840( + input clk, + input [11:0] address, + input [15:0] in, + input load, + output [15:0] out +); + + // Put your code here: + +endmodule diff --git a/03_Sequential_Logic/RAM512.v b/03_Sequential_Logic/RAM512.v new file mode 100644 index 0000000..6e2eacb --- /dev/null +++ b/03_Sequential_Logic/RAM512.v @@ -0,0 +1,18 @@ +/** +* RAM512 implements 512 Bytes of RAM addressed from 0 - 511 +* out = M[address] +* if (load =i= 1) M[address][t+1] = in[t] +*/ + +`default_nettype none +module RAM512( + input clk, + input [8:0] address, + input [15:0] in, + input load, + output [15:0] out +); + + // Put your code here: + +endmodule diff --git a/03_Sequential_Logic/Readme.md b/03_Sequential_Logic/Readme.md new file mode 100644 index 0000000..b6bfaed --- /dev/null +++ b/03_Sequential_Logic/Readme.md @@ -0,0 +1,51 @@ +# 03 Sequential Logic + +Build sequential chips `Bit` , `Register` and `PC`, that make use of the data flip flop (DFF) to store the state. `DFF` is considered primitive, so it's not necessary to implement it. The memory chips `RAM512` and `RAM3840` are based on the primitive `RAM256`, which uses block ram structures integrated in iCE40HX1K. `BitShift9R` and `BitShift8L` are new chips not explained in the original nand2tetris course. They serve to connect HACK to different IO-Devices, which are connected using a serial protocol, where data is transmitted bitwise. + + + +## blinky + +The folder `08_blinky` contains a project to test the counter `PC` in real hardware. Blinky uses counters `PC` to scale down the frequency of 100MHz provided by the clock oscillator on iCE40HX1K-EVB and finally drives the LED1/2. + +*** + +### Project + +* Implement the chips `Bit`, `Register`, `PC`, `RAM512`, `RAM3840`, `BitShift9R` and `BitShift8L` using `DFF` as primitive building block. + +* Implement the chips `RAM512` and `RAM3840` using `RAM256` as primitive building block. + +* for every chip we provide a test bench in the dedicated folder. + + ```shell + $ cd + $ apio clean + $ apio sim + ``` + +* Run blinky in simulation + + ``` + $ cd 06_blinky + $ apio clean + $ apio sim + ``` + +* Zoom in to check the prescaler: + + ![](08_blinky/prescaler.png) + +* Zoom out to check the counter: + + ![](08_blinky/counter.png) + +* Upload the project to iCE40HX1K-EVB end test in real hardware: + + ``` + $ cd 06_blinky + $ apio clean + $ apio upload + ``` + +* Look at LED1/2 and see if they blink. \ No newline at end of file diff --git a/03_Sequential_Logic/Register.v b/03_Sequential_Logic/Register.v new file mode 100644 index 0000000..384dc9b --- /dev/null +++ b/03_Sequential_Logic/Register.v @@ -0,0 +1,18 @@ +/** + * 16-bit register: + * If load[t] == 1 then out[t+1] = in[t] + * else out does not change + */ + +`default_nettype none + +module Register( + input clk, + input [15:0] in, + input load, + output [15:0] out +); + + // Put your code here: + +endmodule diff --git a/04_Machine_Language/Makefile b/04_Machine_Language/Makefile new file mode 100644 index 0000000..34aa8bd --- /dev/null +++ b/04_Machine_Language/Makefile @@ -0,0 +1,14 @@ +leds: + ../tools/Assembler/assembler.pyc leds.asm + cp leds.hack ../05_Computer_Architecture/04_HACK/ROM.hack +mult: + ../tools/Assembler/assembler.pyc mult.asm + cp mult.hack ../05_Computer_Architecture/04_HACK/ROM.hack +upload: + ../tools/Assembler/assembler.pyc leds.asm + ../tools/AsciiToBin.py leds.hack + iceprogduino -o 64k -w leds.bin +clean: + rm -f *.hack *~ *.bin + +.PHONY: clean diff --git a/04_Machine_Language/Readme.md b/04_Machine_Language/Readme.md new file mode 100644 index 0000000..f937589 --- /dev/null +++ b/04_Machine_Language/Readme.md @@ -0,0 +1,83 @@ +# 04 Machine Language + +### leds.asm + +To test input and output capability of HACK we will write an endless loop, in which HACK reads the state of the buttons BUT[1:0] and writes the result to LED[1:0]. All devices for input and output are mapped to memory addresses starting from 0x1000. The state of BUT[1:0] can be read at memory address 4097 and the two leds LED[1:0] can be switched on and of by writing to memory address 4096. The Assembler in `tools` already knows the following predefined symbols. + +| symbol | value | function | +| --------------- | ----------- | ---------------------------------------- | +| SP | 0 | stack pointer of VM | +| LCL | 1 | local segment of VM | +| ARG | 2 | argument of function/method call | +| THIS | 3 | pointer to object in heap | +| THAT | 4 | pointer to object in heap | +| R0--R15 | 0-15 | register 0-15 | +| LED | 4096 | 0 LED is off,1 LED is on | +| BUT | 4097 | 0 BUT pushed down, 1 BUT released up | +| UART_TX | 4098 | send byte over UART | +| UART_RX | 4099 | receive byte from UART | +| SPI | 4100 | read/write to SPI flash rom | +| SRAM_A | 4101 | address of SRAM chip for next read/write | +| SRAM_D | 4102 | read/write data from/to SRAM chip | +| GO | 4103 | switch from BOOT to RUN | +| LCD8 | 4104 | write 8bit to LCD | +| LCD16 | 4105 | write 16bit to LCD | +| RTP | 4106 | read/write 8bit to RTP | +| DEBUG0 - DEBUG4 | 4107 - 4111 | reserved for debugging | + +## mult.asm + +To test the ALU of HACK we will write a little assembler program, that calculates the multiplication of two integers stored in R0 and R1. The result shoud be stored into R2. + +To Test the result we have to load some test values into R0,R1 and R2. After the multiplication is finished we will check the result in R2. To show if the multiplication is correct, we use two strategies: + +#### Use LED to debug + +To test `mult.asm` in real hardware, we can use the LED[1:0] to display if the result is correct or wrong according to: + +| LED[1:0] | output | +| -------- | -------------------- | +| 00 | nothing happened yet | +| 01 | start multiplication | +| 10 | correct result | +| 11 | wrong result | + +### Use DEBUG0-4 register + +To test `mult.asm` in simulation, we can use the DEBUG registers. Every time we change the value of R0--R2 we store the new values also to the corresponding register DEBUG0--DEBUG2. This is done by replacing every instance of a code snippet that changes R1 (and R0,R2 accordingly): + +``` +@R1 +M= +``` + +with the code that additionally writes the new value to the DEBUG1 register: + +``` +@R1 +DM= +@DEBUG1 +M=D +``` + +--- + +### Project + +- Implement `leds.asm` and `mult.asm`. + +- Put your code in the skeleton file `.asm`. To build the `.hack` binary file, which can than be preloaded to the instruction ROM of HACK in `05_Computer_Architecture/04_HACK`, just type: + + ``` + $ make leds + ``` + + or + + ``` + $ make mult + ``` + + This will invoke the assembler and copy the produced binary file `ROM.hack` in the appropriate folder `05_Computer_Architecture/04_HACK`. + +- To run the programms you first have to build a HACK computer. This is done in `05_Computer_Architecture`. diff --git a/04_Machine_Language/leds.asm b/04_Machine_Language/leds.asm new file mode 100644 index 0000000..8c55125 --- /dev/null +++ b/04_Machine_Language/leds.asm @@ -0,0 +1,5 @@ +// led.asm +// execute an infinite loop to +// read the button state and output to led + +// Put your code here: diff --git a/04_Machine_Language/mult.asm b/04_Machine_Language/mult.asm new file mode 100644 index 0000000..0a74dad --- /dev/null +++ b/04_Machine_Language/mult.asm @@ -0,0 +1,67 @@ +// mult.asm +// calculate R2 = R0 * R1 +// and check the result. + +// Load test data: R0 = 13, R1 = 55, R2 = 42 +// and set LED to 01 (nothing calculated yet!) +@13 +D=A +@R0 +MD=D +@DEBUG0 +M=D + +@55 +D=A +@R1 +MD=D +@DEBUG1 +M=D + +@42 +D=A +@R2 +MD=D +@DEBUG2 +M=D + +@LED +M=1 + +// Put your code here: + + + + + +// till here! + +// Check result according to +// LED = 2 (correct result) +// LED = 3 (wrong result) +// and HALT +(END) +@R2 +D=M +@715 +D=D-A +@OK +D;JEQ + +(NOK) +@3 +D=A +@LED +M=D +@HALT +0;JMP + +(OK) +@2 +D=A +@LED +M=D + +(HALT) +@HALT +0;JMP diff --git a/05_Computer_Architecture/01_CPU/CPU.dia b/05_Computer_Architecture/01_CPU/CPU.dia new file mode 100644 index 0000000..41064b3 Binary files /dev/null and b/05_Computer_Architecture/01_CPU/CPU.dia differ diff --git a/05_Computer_Architecture/01_CPU/CPU.png b/05_Computer_Architecture/01_CPU/CPU.png new file mode 100644 index 0000000..9634708 Binary files /dev/null and b/05_Computer_Architecture/01_CPU/CPU.png differ diff --git a/05_Computer_Architecture/01_CPU/CPU_tb.gtkw b/05_Computer_Architecture/01_CPU/CPU_tb.gtkw new file mode 100644 index 0000000..6417ae1 --- /dev/null +++ b/05_Computer_Architecture/01_CPU/CPU_tb.gtkw @@ -0,0 +1,48 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Fri Dec 23 09:59:16 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/05_Computer_Architecture/01_CPU/CPU_tb.vcd" +[dumpfile_mtime] "Fri Dec 23 09:58:03 2022" +[dumpfile_size] 3204741 +[savefile] "/home/micha/gitlab/nand2tetris/05_Computer_Architecture/01_CPU/CPU_tb.gtkw" +[timestart] 0 +[size] 1866 600 +[pos] -1 -1 +*-3.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] CPU_tb. +[sst_width] 281 +[signals_width] 210 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@28 +CPU_tb.clk +@200 +-IN +@22 +CPU_tb.inM[15:0] +CPU_tb.instruction[15:0] +@28 +CPU_tb.reset +@200 +-OUT +@22 +CPU_tb.addressM[15:0] +CPU_tb.outM[15:0] +CPU_tb.pc[15:0] +@28 +CPU_tb.writeM +@200 +-CMP +@22 +CPU_tb.addressM_cmp[15:0] +CPU_tb.out_cmp[15:0] +CPU_tb.pc_cmp[15:0] +@28 +CPU_tb.writeM_cmp +@200 +-Test +@28 +CPU_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/05_Computer_Architecture/01_CPU/CPU_tb.v b/05_Computer_Architecture/01_CPU/CPU_tb.v new file mode 100644 index 0000000..a9be45d --- /dev/null +++ b/05_Computer_Architecture/01_CPU/CPU_tb.v @@ -0,0 +1,86 @@ +`default_nettype none +module CPU_tb(); + + // IN,OUT + reg clk=1; + reg [15:0] inM=0; + reg [15:0] instruction=0; + reg reset=1; + wire [15:0] outM; + wire writeM; + wire [15:0] addressM; + wire [15:0] pc; + + // Part + CPU CPU( + .clk(clk), + .inM(inM), + .instruction(instruction), + .reset(reset), + .outM(outM), + .writeM(writeM), + .addressM(addressM), + .pc(pc) + ); + + // Simulation + always #1 clk=~clk; + always @(posedge clk) begin + inM <= $random; + reset <= (n<=10) || ((n>20) && (n<40)); + instruction <= $random; + end + + // Compare + reg [15:0] addressM_cmp=0; + reg [15:0] regD=0; + reg [15:0] pc_cmp=0; + reg zx,nx,zy,ny,f,no; + wire [15:0] out_cmp; + wire [15:0] x,y; + wire zr,ng; + assign x = instruction[10]?(instruction[11]?~0:~regD):(instruction[11]?0:regD); + assign y = instruction[8]?(instruction[9]?~0:~(instruction[12]?inM:addressM_cmp)):(instruction[9]?0:(instruction[12]?inM:addressM_cmp)); + assign out_cmp = instruction[6]?(instruction[7]?~(x+y):~(x&y)):(instruction[7]?(x+y):(x&y)); + wire comp; + wire jmp; + assign comp = instruction[15] && instruction[14] && instruction[13]; + assign zr = (out_cmp==0); + assign ng = out_cmp[15]; + assign jmp = comp && ((ng&&instruction[2])||(zr&&instruction[1])||(~(ng|zr)&&instruction[0])); + always @(posedge clk) begin + addressM_cmp <= comp?(instruction[5]?out_cmp:addressM_cmp) : instruction; + regD <= comp?(instruction[4]?out_cmp:regD) : regD; + pc_cmp <= reset?0 : (jmp?addressM_cmp:pc_cmp+1); + end + wire writeM_cmp; + assign writeM_cmp = comp?instruction[3]:0; + + reg fail = 0; + reg [15:0] n = 0; + task check; + #1 + if ((pc != pc_cmp) || (addressM != addressM_cmp) || (outM != out_cmp) || (writeM != writeM_cmp)) + begin + $display("FAIL: clk=%1b, inM=%16b, instruction=%16b, reset=%1b, outM=%16b, writeM=%1b, addressM=%16b, pc=%16b",clk,inM,instruction,reset,outM,writeM,addressM,pc); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("CPU_tb.vcd"); + $dumpvars(0, CPU_tb); + + $display("------------------------"); + $display("Testbench: CPU"); + + for (n=0; n<1000;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/05_Computer_Architecture/01_CPU/Include.v b/05_Computer_Architecture/01_CPU/Include.v new file mode 100644 index 0000000..d10bbab --- /dev/null +++ b/05_Computer_Architecture/01_CPU/Include.v @@ -0,0 +1,33 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift9R.v" +`include "../../03_Sequential_Logic/BitShift8L.v" + +`include "../../05_Computer_Architecture/CPU.v" diff --git a/05_Computer_Architecture/01_CPU/apio.ini b/05_Computer_Architecture/01_CPU/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/05_Computer_Architecture/01_CPU/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/05_Computer_Architecture/02_Memory/Include.v b/05_Computer_Architecture/02_Memory/Include.v new file mode 100644 index 0000000..f7e39ae --- /dev/null +++ b/05_Computer_Architecture/02_Memory/Include.v @@ -0,0 +1,34 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift9R.v" +`include "../../03_Sequential_Logic/BitShift8L.v" + +`include "../../05_Computer_Architecture/CPU.v" +`include "../../05_Computer_Architecture/Memory.v" diff --git a/05_Computer_Architecture/02_Memory/Memory_tb.gtkw b/05_Computer_Architecture/02_Memory/Memory_tb.gtkw new file mode 100644 index 0000000..1fca98b --- /dev/null +++ b/05_Computer_Architecture/02_Memory/Memory_tb.gtkw @@ -0,0 +1,67 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Tue Nov 22 10:53:14 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/05_Computer_Architecture/02_Memory/Memory_tb.vcd" +[dumpfile_mtime] "Tue Nov 22 10:50:29 2022" +[dumpfile_size] 15133403 +[savefile] "/home/micha/gitlab/nand2tetris/05_Computer_Architecture/02_Memory/Memory_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -1 -1 +*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 258 +@200 +-IN +@22 +Memory_tb.address[15:0] +Memory_tb.inRAM[15:0] +Memory_tb.inIO0[15:0] +Memory_tb.inIO1[15:0] +Memory_tb.inIO2[15:0] +Memory_tb.inIO3[15:0] +Memory_tb.inIO4[15:0] +Memory_tb.inIO5[15:0] +Memory_tb.inIO6[15:0] +Memory_tb.inIO7[15:0] +Memory_tb.inIO8[15:0] +Memory_tb.inIO9[15:0] +Memory_tb.inIOA[15:0] +Memory_tb.inIOB[15:0] +Memory_tb.inIOC[15:0] +Memory_tb.inIOD[15:0] +Memory_tb.inIOE[15:0] +Memory_tb.inIOF[15:0] +@28 +Memory_tb.load +@200 +-OUT +@22 +Memory_tb.out[15:0] +@28 +Memory_tb.loadRAM +Memory_tb.loadIO0 +Memory_tb.loadIO1 +Memory_tb.loadIO2 +Memory_tb.loadIO3 +Memory_tb.loadIO4 +Memory_tb.loadIO5 +Memory_tb.loadIO6 +Memory_tb.loadIO7 +Memory_tb.loadIO8 +Memory_tb.loadIO9 +Memory_tb.loadIOA +Memory_tb.loadIOB +Memory_tb.loadIOC +Memory_tb.loadIOD +Memory_tb.loadIOE +Memory_tb.loadIOF +@200 +-Test +@29 +Memory_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/05_Computer_Architecture/02_Memory/Memory_tb.v b/05_Computer_Architecture/02_Memory/Memory_tb.v new file mode 100644 index 0000000..782751c --- /dev/null +++ b/05_Computer_Architecture/02_Memory/Memory_tb.v @@ -0,0 +1,180 @@ +`default_nettype none +module Memory_tb(); + + // IN,OUT + reg [15:0] address; + reg load; + wire [15:0] out; + wire loadRAM; + wire loadIO0; + wire loadIO1; + wire loadIO2; + wire loadIO3; + wire loadIO4; + wire loadIO5; + wire loadIO6; + wire loadIO7; + wire loadIO8; + wire loadIO9; + wire loadIOA; + wire loadIOB; + wire loadIOC; + wire loadIOD; + wire loadIOE; + wire loadIOF; + reg [15:0] inRAM; + reg [15:0] inIO0; + reg [15:0] inIO1; + reg [15:0] inIO2; + reg [15:0] inIO3; + reg [15:0] inIO4; + reg [15:0] inIO5; + reg [15:0] inIO6; + reg [15:0] inIO7; + reg [15:0] inIO8; + reg [15:0] inIO9; + reg [15:0] inIOA; + reg [15:0] inIOB; + reg [15:0] inIOC; + reg [15:0] inIOD; + reg [15:0] inIOE; + reg [15:0] inIOF; + + // Part + Memory MEMORY( + .address(address), + .load(load), + .out(out), + .loadRAM(loadRAM), + .loadIO0(loadIO0), + .loadIO1(loadIO1), + .loadIO2(loadIO2), + .loadIO3(loadIO3), + .loadIO4(loadIO4), + .loadIO5(loadIO5), + .loadIO6(loadIO6), + .loadIO7(loadIO7), + .loadIO8(loadIO8), + .loadIO9(loadIO9), + .loadIOA(loadIOA), + .loadIOB(loadIOB), + .loadIOC(loadIOC), + .loadIOD(loadIOD), + .loadIOE(loadIOE), + .loadIOF(loadIOF), + .inRAM(inRAM), + .inIO0(inIO0), + .inIO1(inIO1), + .inIO2(inIO2), + .inIO3(inIO3), + .inIO4(inIO4), + .inIO5(inIO5), + .inIO6(inIO6), + .inIO7(inIO7), + .inIO8(inIO8), + .inIO9(inIO9), + .inIOA(inIOA), + .inIOB(inIOB), + .inIOC(inIOC), + .inIOD(inIOD), + .inIOE(inIOE), + .inIOF(inIOF) + ); + + // Compare + reg fail = 0; + wire [15:0] out_cmp; + assign out_cmp = ((address==4096)?inIO0: + (address==4097)?inIO1: + (address==4098)?inIO2: + (address==4099)?inIO3: + (address==4100)?inIO4: + (address==4101)?inIO5: + (address==4102)?inIO6: + (address==4103)?inIO7: + (address==4104)?inIO8: + (address==4105)?inIO9: + (address==4106)?inIOA: + (address==4107)?inIOB: + (address==4108)?inIOC: + (address==4109)?inIOD: + (address==4110)?inIOE: + (address==4111)?inIOF: + inRAM); + wire loadRAM_cmp,loadIO0_cmp,loadIO1_cmp,loadIO2_cmp,loadIO3_cmp,loadIO4_cmp,loadIO5_cmp,loadIO6_cmp,loadIO7_cmp, + loadIO8_cmp,loadIO9_cmp,loadIOA_cmp,loadIOB_cmp,loadIOC_cmp,loadIOD_cmp,loadIOE_cmp,loadIOF_cmp; + assign loadRAM_cmp = (address<=3839)?load:0; + assign loadIO0_cmp = (address==4096)?load:0; + assign loadIO1_cmp = (address==4097)?load:0; + assign loadIO2_cmp = (address==4098)?load:0; + assign loadIO3_cmp = (address==4099)?load:0; + assign loadIO4_cmp = (address==4100)?load:0; + assign loadIO5_cmp = (address==4101)?load:0; + assign loadIO6_cmp = (address==4102)?load:0; + assign loadIO7_cmp = (address==4103)?load:0; + assign loadIO8_cmp = (address==4104)?load:0; + assign loadIO9_cmp = (address==4105)?load:0; + assign loadIOA_cmp = (address==4106)?load:0; + assign loadIOB_cmp = (address==4107)?load:0; + assign loadIOC_cmp = (address==4108)?load:0; + assign loadIOD_cmp = (address==4109)?load:0; + assign loadIOE_cmp = (address==4110)?load:0; + assign loadIOF_cmp = (address==4111)?load:0; + + task check; + #1 + if ((out!=out_cmp)||(loadRAM!=loadRAM_cmp)|| + (loadIO0!=loadIO0_cmp)||(loadIO1!=loadIO1_cmp)||(loadIO2!=loadIO2_cmp)||(loadIO3!=loadIO3_cmp)|| + (loadIO4!=loadIO4_cmp)||(loadIO5!=loadIO5_cmp)||(loadIO6!=loadIO6_cmp)||(loadIO7!=loadIO7_cmp)|| + (loadIO8!=loadIO8_cmp)||(loadIO9!=loadIO9_cmp)||(loadIOA!=loadIOA_cmp)||(loadIOB!=loadIOB_cmp)|| + (loadIOC!=loadIOC_cmp)||(loadIOD!=loadIOD_cmp)||(loadIOE!=loadIOE_cmp)||(loadIOF!=loadIOF_cmp)) + begin + $display("FAIL: address=%16b, load=%1b, out=%16b, loadRAM=%1b, loadIO0=%1b, loadIO1=%1b, ... ",address,load,out,loadRAM,loadIO0,loadIO1); + fail=1; + end + endtask + + // Test + initial begin + $dumpfile("Memory_tb.vcd"); + $dumpvars(0, Memory_tb); + + $display("------------------------"); + $display("Testbench: Memory"); + + inRAM=$random; + inIO0=$random; + inIO1=$random; + inIO2=$random; + inIO3=$random; + inIO4=$random; + inIO5=$random; + inIO6=$random; + inIO7=$random; + inIO8=$random; + inIO9=$random; + inIOA=$random; + inIOB=$random; + inIOC=$random; + inIOD=$random; + inIOE=$random; + inIOF=$random; + for (address=4096; address<4112;address=address+1) + begin + load=0;check(); + load=1;check(); + end + for (address=0; address<3840;address=address+1) + begin + inRAM=$random; + load=0;check(); + load=1;check(); + end + + if (fail==0) $display("passed"); + $display("------------------------"); + + $finish; + end + +endmodule diff --git a/05_Computer_Architecture/02_Memory/apio.ini b/05_Computer_Architecture/02_Memory/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/05_Computer_Architecture/02_Memory/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/05_Computer_Architecture/03_Clock25_Reset20/Clock25_Reset20_tb.gtkw b/05_Computer_Architecture/03_Clock25_Reset20/Clock25_Reset20_tb.gtkw new file mode 100644 index 0000000..a2ee9f0 --- /dev/null +++ b/05_Computer_Architecture/03_Clock25_Reset20/Clock25_Reset20_tb.gtkw @@ -0,0 +1,23 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 29 21:52:20 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/05_Computer_Architecture/03_Clock_Reset/Clock25_Reset20_tb.vcd" +[dumpfile_mtime] "Thu Dec 29 21:51:50 2022" +[dumpfile_size] 2320447 +[savefile] "/home/micha/gitlab/nand2tetris-fpga/05_Computer_Architecture/03_Clock_Reset/Clock25_Reset20_tb.gtkw" +[timestart] 0 +[size] 1636 438 +[pos] -1 -1 +*-17.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 80 +[sst_expanded] 1 +[sst_vpaned_height] 76 +@28 +Clock25_Reset20_tb.CLK +Clock25_Reset20_tb.clk +@29 +Clock25_Reset20_tb.reset +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/05_Computer_Architecture/03_Clock25_Reset20/Clock25_Reset20_tb.v b/05_Computer_Architecture/03_Clock25_Reset20/Clock25_Reset20_tb.v new file mode 100644 index 0000000..60caa49 --- /dev/null +++ b/05_Computer_Architecture/03_Clock25_Reset20/Clock25_Reset20_tb.v @@ -0,0 +1,32 @@ +`timescale 10ns/1ns +`default_nettype none +module Clock25_Reset20_tb(); + + // IN,OUT + reg CLK=1; + wire clk; + wire reset; + + // Part + Clock25_Reset20 CLOCK25_RESET20( + .CLK(CLK), + .clk(clk), + .reset(reset) + ); + + // Simulation + always #0.5 CLK=~CLK; + + // Test + initial begin + $dumpfile("Clock25_Reset20_tb.vcd"); + $dumpvars(0, Clock25_Reset20_tb); + + $display("------------------------"); + $display("Testbench: Clock25_Reset10"); + + #4000 + $finish; + end + +endmodule diff --git a/05_Computer_Architecture/03_Clock25_Reset20/Include.v b/05_Computer_Architecture/03_Clock25_Reset20/Include.v new file mode 100644 index 0000000..95c511f --- /dev/null +++ b/05_Computer_Architecture/03_Clock25_Reset20/Include.v @@ -0,0 +1,33 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift9R.v" +`include "../../03_Sequential_Logic/BitShift8L.v" + +`include "../../05_Computer_Architecture/Clock25_Reset20.v" diff --git a/05_Computer_Architecture/03_Clock25_Reset20/apio.ini b/05_Computer_Architecture/03_Clock25_Reset20/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/05_Computer_Architecture/03_Clock25_Reset20/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/05_Computer_Architecture/03_Clock25_Reset20/clock.png b/05_Computer_Architecture/03_Clock25_Reset20/clock.png new file mode 100644 index 0000000..4c66180 Binary files /dev/null and b/05_Computer_Architecture/03_Clock25_Reset20/clock.png differ diff --git a/05_Computer_Architecture/03_Clock25_Reset20/reset.png b/05_Computer_Architecture/03_Clock25_Reset20/reset.png new file mode 100644 index 0000000..7c65ea5 Binary files /dev/null and b/05_Computer_Architecture/03_Clock25_Reset20/reset.png differ diff --git a/05_Computer_Architecture/04_HACK/CPU.png b/05_Computer_Architecture/04_HACK/CPU.png new file mode 100644 index 0000000..4e9a84b Binary files /dev/null and b/05_Computer_Architecture/04_HACK/CPU.png differ diff --git a/05_Computer_Architecture/04_HACK/HACK.dia b/05_Computer_Architecture/04_HACK/HACK.dia new file mode 100644 index 0000000..48297ef Binary files /dev/null and b/05_Computer_Architecture/04_HACK/HACK.dia differ diff --git a/05_Computer_Architecture/04_HACK/HACK.png b/05_Computer_Architecture/04_HACK/HACK.png new file mode 100644 index 0000000..d2376b9 Binary files /dev/null and b/05_Computer_Architecture/04_HACK/HACK.png differ diff --git a/05_Computer_Architecture/04_HACK/HACK_tb.gtkw b/05_Computer_Architecture/04_HACK/HACK_tb.gtkw new file mode 100644 index 0000000..9ceba17 --- /dev/null +++ b/05_Computer_Architecture/04_HACK/HACK_tb.gtkw @@ -0,0 +1,42 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Mon Dec 12 16:41:42 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/05_Computer_Architecture/04_HACK/HACK_tb.vcd" +[dumpfile_mtime] "Mon Dec 12 16:41:24 2022" +[dumpfile_size] 5432004 +[savefile] "/home/micha/gitlab/nand2tetris/05_Computer_Architecture/04_HACK/HACK_tb.gtkw" +[timestart] 0 +[size] 1673 487 +[pos] 118 133 +*-23.000000 50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] HACK_tb. +[sst_width] 281 +[signals_width] 180 +[sst_expanded] 1 +[sst_vpaned_height] 98 +@200 +-IN +@28 +HACK_tb.CLK +HACK_tb.BUT[1:0] +@200 +-OUT +@28 +HACK_tb.LED[1:0] +@200 +-DEBUG +@28 +HACK_tb.HACK.loadDEBUG0 +@24 +HACK_tb.HACK.outDEBUG0[15:0] +@28 +HACK_tb.HACK.loadDEBUG1 +@24 +HACK_tb.HACK.outDEBUG1[15:0] +@28 +HACK_tb.HACK.loadDEBUG2 +@24 +HACK_tb.HACK.outDEBUG2[15:0] +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/05_Computer_Architecture/04_HACK/HACK_tb.v b/05_Computer_Architecture/04_HACK/HACK_tb.v new file mode 100644 index 0000000..161dda4 --- /dev/null +++ b/05_Computer_Architecture/04_HACK/HACK_tb.v @@ -0,0 +1,30 @@ +`timescale 10ns/1ns +`default_nettype none +module HACK_tb(); + + // IN,OUT + reg CLK = 1; + reg [1:0] BUT = 0; + wire [1:0] LED; + + // Part + HACK HACK( + .CLK(CLK), + .BUT(BUT), + .LED(LED) + ); + + // Simulate + always #500 BUT <= BUT+1; + + // Test + always #0.5 CLK = ~CLK; + initial begin + $dumpfile("HACK_tb.vcd"); + $dumpvars(0, HACK_tb); + + #4000 + $finish; + end + +endmodule diff --git a/05_Computer_Architecture/04_HACK/Hack_tb.gtkw b/05_Computer_Architecture/04_HACK/Hack_tb.gtkw new file mode 100644 index 0000000..2d04d5a --- /dev/null +++ b/05_Computer_Architecture/04_HACK/Hack_tb.gtkw @@ -0,0 +1,68 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Mon Nov 28 10:58:53 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/05_Computer_Architecture/03_HACK/Hack_tb.vcd" +[dumpfile_mtime] "Mon Nov 28 10:58:25 2022" +[dumpfile_size] 3140780 +[savefile] "/home/micha/gitlab/nand2tetris/05_Computer_Architecture/03_HACK/Hack_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -1 -1 +*-8.420643 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] Hack_tb. +[treeopen] Hack_tb.HACK. +[sst_width] 281 +[signals_width] 200 +[sst_expanded] 1 +[sst_vpaned_height] 261 +@28 +Hack_tb.HACK.clk +@200 +-IN +@28 +Hack_tb.RST +Hack_tb.BUT +@200 +-CPU +@22 +Hack_tb.HACK.pc[15:0] +Hack_tb.HACK.instruction[15:0] +Hack_tb.HACK.CPU.regA[15:0] +Hack_tb.HACK.CPU.regD[15:0] +@200 +-MEM +@22 +Hack_tb.HACK.MEMORY.address[15:0] +@28 +Hack_tb.HACK.MEMORY.load +@22 +Hack_tb.HACK.MEMORY.out[15:0] +@200 +-OUT +@28 +Hack_tb.LED[1:0] +@200 +-DEBUG +@28 +Hack_tb.HACK.loadDEBUG0 +@24 +Hack_tb.HACK.outDEBUG0[15:0] +@28 +Hack_tb.HACK.loadDEBUG1 +@24 +Hack_tb.HACK.outDEBUG1[15:0] +@28 +Hack_tb.HACK.loadDEBUG2 +@25 +Hack_tb.HACK.outDEBUG2[15:0] +@28 +Hack_tb.HACK.loadDEBUG3 +@22 +Hack_tb.HACK.outDEBUG3[15:0] +@28 +Hack_tb.HACK.loadDEBUG4 +@22 +Hack_tb.HACK.outDEBUG4[15:0] +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/05_Computer_Architecture/04_HACK/Include.v b/05_Computer_Architecture/04_HACK/Include.v new file mode 100644 index 0000000..53f3655 --- /dev/null +++ b/05_Computer_Architecture/04_HACK/Include.v @@ -0,0 +1,40 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/RAM256.v" +`include "../../03_Sequential_Logic/RAM512.v" +`include "../../03_Sequential_Logic/RAM3840.v" +`include "../../03_Sequential_Logic/BitShift9R.v" +`include "../../03_Sequential_Logic/BitShift8L.v" + +`include "../../05_Computer_Architecture/CPU.v" +`include "../../05_Computer_Architecture/Memory.v" +`include "../../05_Computer_Architecture/ROM.v" +`include "../../05_Computer_Architecture/Clock25_Reset20.v" +`include "../../05_Computer_Architecture/HACK.v" diff --git a/05_Computer_Architecture/04_HACK/apio.ini b/05_Computer_Architecture/04_HACK/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/05_Computer_Architecture/04_HACK/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/05_Computer_Architecture/04_HACK/iCE40HX1K.pcf b/05_Computer_Architecture/04_HACK/iCE40HX1K.pcf new file mode 100644 index 0000000..cf8865a --- /dev/null +++ b/05_Computer_Architecture/04_HACK/iCE40HX1K.pcf @@ -0,0 +1,11 @@ +# physical constrain file +# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB +# compare to the schematic of the board and the datasheet of fpga + +set_io CLK 15 +set_io BUT[0] 41 +set_io BUT[1] 42 + +set_io LED[0] 40 +set_io LED[1] 51 + diff --git a/05_Computer_Architecture/04_HACK/leds.png b/05_Computer_Architecture/04_HACK/leds.png new file mode 100644 index 0000000..78e150f Binary files /dev/null and b/05_Computer_Architecture/04_HACK/leds.png differ diff --git a/05_Computer_Architecture/04_HACK/mult.png b/05_Computer_Architecture/04_HACK/mult.png new file mode 100644 index 0000000..2da83b0 Binary files /dev/null and b/05_Computer_Architecture/04_HACK/mult.png differ diff --git a/05_Computer_Architecture/CPU.v b/05_Computer_Architecture/CPU.v new file mode 100644 index 0000000..23f4bdb --- /dev/null +++ b/05_Computer_Architecture/CPU.v @@ -0,0 +1,40 @@ +/** + * The Hack CPU (Central Processing unit), consisting of an ALU, + * two registers named A and D, and a program counter named PC. + * The CPU is designed to fetch and execute instructions written in + * the Hack machine language. In particular, functions as follows: + * Executes the inputted instruction according to the Hack machine + * language specification. The D and A in the language specification + * refer to CPU-resident registers, while M refers to the external + * memory location addressed by A, i.e. to Memory[A]. The inM input + * holds the value of this location. If the current instruction needs + * to write a value to M, the value is placed in outM, the address + * of the target location is placed in the addressM output, and the + * writeM control bit is asserted. (When writeM==0, any value may + * appear in outM). The outM and writeM outputs are combinational: + * they are affected instantaneously by the execution of the current + * instruction. The addressM and pc outputs are clocked: although they + * are affected by the execution of the current instruction, they commit + * to their new values only in the next time step. If reset==1 then the + * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather + * than to the address resulting from executing the current instruction. + */ + +`default_nettype none +module CPU( + input clk, + input [15:0] inM, // M value input (M = contents of RAM[A]) + input [15:0] instruction, // Instruction for execution + input reset, // Signals whether to re-start the current + // program (reset==1) or continue executing + // the current program (reset==0). + + output [15:0] outM, // M value output + output writeM, // Write to M? + output [15:0] addressM, // Address in data memory (of M) to read + output [15:0] pc // address of next instruction +); + + // Put your code here: + +endmodule diff --git a/05_Computer_Architecture/Clock25_Reset20.v b/05_Computer_Architecture/Clock25_Reset20.v new file mode 100644 index 0000000..ad8a746 --- /dev/null +++ b/05_Computer_Architecture/Clock25_Reset20.v @@ -0,0 +1,15 @@ +/** +* Uses CLK of 100MHz to generate: +* internal clock signal clk with 25MHz and +* a reset signal of approx. 20us length +*/ +`default_nettype none +module Clock25_Reset20( + input CLK, // external clock 100 MHz + output clk, // internal clock 25 Mhz + output reset // reset signal approx. 20us +); + + // Put your code here: + +endmodule diff --git a/05_Computer_Architecture/HACK.v b/05_Computer_Architecture/HACK.v new file mode 100644 index 0000000..dfae7f6 --- /dev/null +++ b/05_Computer_Architecture/HACK.v @@ -0,0 +1,19 @@ +/** + * The HACK computer, including CPU, ROM, RAM and the generator for + * reset and clk (25MHz) signal. For approx. 20us HACK CPU resets. + * From this point onward the user is at the mercy of the software. + * In particular, depending on the program's code, the LED may show + * some output and the user may be able to interact with the computer + * via the BUT. + */ + +`default_nettype none +module HACK( + input CLK, // external clock 100 MHz + input [1:0] BUT, // user button (0 if pressed, 1 if released) + output [1:0] LED // leds (0 off, 1 on) +); + + // Put your code here: + +endmodule diff --git a/05_Computer_Architecture/Memory.v b/05_Computer_Architecture/Memory.v new file mode 100644 index 0000000..59207da --- /dev/null +++ b/05_Computer_Architecture/Memory.v @@ -0,0 +1,60 @@ +/** + * The complete address space of the Hack computer's memory, + * including RAM and memory-mapped I/O. + * The chip facilitates read and write operations, as follows: + * Read: out(t) = Memory[address(t)](t) + * Write: if load(t-1) then Memory[address(t-1)](t) = in(t-1) + * In words: the chip always outputs the value stored at the memory + * location specified by address. If load==1, the in value is loaded + * into the memory location specified by address. This value becomes + * available through the out output from the next time step onward. + * Address space rules: + * RAM 0x0000 - 0x0EFF (3840 words) + * IO 0x1000 - 0x100F (maps to 16 different devices) + * The behavior of IO addresses is described in 06_IO-Devices + */ + +`default_nettype none +module Memory( + input [15:0] address, + input load, + output [15:0] out, + output loadRAM, + output loadIO0, + output loadIO1, + output loadIO2, + output loadIO3, + output loadIO4, + output loadIO5, + output loadIO6, + output loadIO7, + output loadIO8, + output loadIO9, + output loadIOA, + output loadIOB, + output loadIOC, + output loadIOD, + output loadIOE, + output loadIOF, + input [15:0] inRAM, + input [15:0] inIO0, + input [15:0] inIO1, + input [15:0] inIO2, + input [15:0] inIO3, + input [15:0] inIO4, + input [15:0] inIO5, + input [15:0] inIO6, + input [15:0] inIO7, + input [15:0] inIO8, + input [15:0] inIO9, + input [15:0] inIOA, + input [15:0] inIOB, + input [15:0] inIOC, + input [15:0] inIOD, + input [15:0] inIOE, + input [15:0] inIOF +); + + // Put your code here: + +endmodule diff --git a/05_Computer_Architecture/ROM.v b/05_Computer_Architecture/ROM.v new file mode 100644 index 0000000..aa5b88a --- /dev/null +++ b/05_Computer_Architecture/ROM.v @@ -0,0 +1,26 @@ +/** + * instruction memory at boot time + * The instruction memory is read only (ROM) and + * preloaded with 256 x 16bit of Hackcode holding the bootloader. + * + * instruction = ROM[pc] + */ + +`default_nettype none +module ROM( + input [15:0] pc, + output [15:0] instruction +); + + // No need to implement this chip + // The file ROM.BIN holds the hack code + parameter ROMFILE = "ROM.hack"; + + reg [15:0] mem [0:255]; + assign instruction = mem[pc[7:0]]; + + initial begin + $readmemb(ROMFILE,mem); + end + +endmodule diff --git a/05_Computer_Architecture/Readme.md b/05_Computer_Architecture/Readme.md new file mode 100644 index 0000000..16bd745 --- /dev/null +++ b/05_Computer_Architecture/Readme.md @@ -0,0 +1,122 @@ +# 05 Computer Architecture + +Build the `HACK` computer system consisting of the chips `CPU`, `Memory`, `Clock25_Reset20`, `RAM` and `ROM`. `ROM` uses a block ram structure (256 words) of iCE40HX1K and can be considered primitive. It can be preloaded with the instructions of the assembler programs implemented in `04_Machine_Language` . + +### 01 CPU + +The `CPU` corresponds to the proposed implementation of nand2tetris course. + +![](01_CPU/CPU.png)**Attention:** In the original specification of HACK all C instruction have the binary form: 111xxxxxxxxxxxxx and A instruction have the form 0xxxxxxxxxxxxxxx. In order to use HACK with instruction memory ROM >32K (to play tetris), we will also interpret the machine language instructions starting with 000-110 as A-instructions, allowing the following jumps for all labels up to 56K! + +``` +@label +0;JMP +``` + +### 02 Memory + +The chip `Memory.v` maps all addresses 0 - 0x0FFF to RAM and the addresses 0x1000-0x100F to the 16 special function registers used for memory mapped IO-Devices and debugging. + +### 03 Clock25_Reset20 + +The 100 MHz (CLK) of the clock generator on the iCE40HX1K-EVB is to fast to drive our HACK design. Therefore we must scale down the external clock (CLK) of 100 MHz to the internal clock (clk) of 25Mhz using a counter `PC` . + +HACK CPU needs a reset signal to have a proper start of the complete computer system. The fpga chip nees some time delay to preload the ROM with ROM.hack code. Therefore the reset signal at startup should have a minimal length of approximately 20us. + +### 04 HACK + +The chip `HACK.v` is the top level module, that connects to the outer world. + +![](04_HACK/HACK.png) + +The signals wires `CLK`, `RST`, `BUT[1:0]` and `LED[1:0]` (by convention written in capital letters) connect to the outer pins of the fpga chip iCE40HX1K according to the file `iCE40HX1K.pcf`. The board iCE40-HX1K-EVB comes with a clock generator of 100 MHz, two buttons and two leds connected to FPGA (refer to [datasheets/iCE40HX1K-EVB](../datasheets/iCE40HX1K-EVB_Rev_B.pdf)). + +| wire | iCE40HX1K (FPGA) | board iCE40HX1K-EVB | +| ------ | ---------------- | ----------------------- | +| CLK | 15 | 100 Mhz clock generator | +| BUT[0] | 41 | BUT1 | +| BUT[1] | 42 | BUT2 | +| LED[0] | 40 | LED1 | +| LED[1] | 51 | LED2 | + +To add IO capability we add 7 more special function registers mapped to the following addresses: + +| address | I/O dev | function | +| ----------- | ------- | ---------------------------------------------------- | +| 0 - 3839 | RAM | | +| 4096 | LED | 0 = led off, 1 = led on | +| 4097 | BUT | 0 = button pressed "down", 1 = button released | +| 4098 - 4106 | | reserved for IO devices (see. project 06_IO_Devices) | +| 4107 - 4111 | DEBUG | used for debugging | + +The HACK simulation needs a valid file `ROM.hack` (created in project `04_Machine_Language`) with the machine language instructions to perform. + +The test bench of `04_HACK` will: + +1. occasionally press the user buttons BUT1/2 +2. show the result of LED1/2 +3. show the content of DEBUG0-DEBUG5 + +*** + +### Project + +- Implement the chips `CPU` , `Memory` and `Clock25__Reset20` and simulate with the corresponding test benches: + + ``` + $ cd 0X_ + $ apio clean + $ apio sim + ``` + +- Check the frequency of the internal clk signal to be 25MHz. So one clock cylce takes 40us. + + ![](03_Clock25_Reset20/clock.png) + +- Check the reset signal of HACK. You should see a reset signal of approximately 20 us. + + ![](03_Clock25_Reset20/reset.png) +* Implement `HACK` and test with `leds.asm`: + + ``` + $ cd ../04_Machine_Language + $ make leds + $ cd ../05_Computer_Architecture/04_HACK + $ apio clean + $ apio sim + ``` + +* Check, if LEDs change state accoring to BUT: + + ![](04_HACK/leds.png) + +* Test `HACK` with `mult.asm`. + + ``` + $ cd ../04_Machine_Language + $ make mult + $ cd ../05_Computer_Architecture/04_HACK + $ apio clean + $ apio sim + ``` + +* You should see the result 715 of the multiplication 13*55 in the debug register `DEBUG2`! You can change the number format to decimal. + + ![](04_HACK/mult.png) + +* finally upload the complete HACK design with `leds.asm` preloaded into instruction ROM and run in real hardware! + + ``` + $ cd ../04_Machine_Language/01_leds + $ make + $ cd ../05_Computer_Architecture/04_HACK + $ apio clean + $ apio build + $ apio upload + ``` + +* press the user buttons BUT1/BUT2 and see if the LED change pattern accordingly. + +* Repeat the test with the second machine language programm `mult.asm`. + +**Attention:** remember to run `apio clean`, after changing the file `ROM.hack`! \ No newline at end of file diff --git a/06_IO_Devices/00_HACK/HACK.dia b/06_IO_Devices/00_HACK/HACK.dia new file mode 100644 index 0000000..22981f1 Binary files /dev/null and b/06_IO_Devices/00_HACK/HACK.dia differ diff --git a/06_IO_Devices/00_HACK/HACK.png b/06_IO_Devices/00_HACK/HACK.png new file mode 100644 index 0000000..1206a9b Binary files /dev/null and b/06_IO_Devices/00_HACK/HACK.png differ diff --git a/06_IO_Devices/00_HACK/HACK_tb.gtkw b/06_IO_Devices/00_HACK/HACK_tb.gtkw new file mode 100644 index 0000000..8c6c422 --- /dev/null +++ b/06_IO_Devices/00_HACK/HACK_tb.gtkw @@ -0,0 +1,72 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 29 16:29:18 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/00_HACK/HACK_tb.vcd" +[dumpfile_mtime] "Thu Dec 29 16:28:24 2022" +[dumpfile_size] 83632917 +[savefile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/00_HACK/HACK_tb.gtkw" +[timestart] 281880000 +[size] 1920 963 +[pos] -1 -1 +*-24.000000 40600000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] HACK_tb. +[sst_width] 281 +[signals_width] 180 +[sst_expanded] 1 +[sst_vpaned_height] 259 +@200 +-GPIO +@28 +HACK_tb.BUT[1:0] +HACK_tb.LED[1:0] +@200 +-UART +@28 +HACK_tb.UART_TX +HACK_tb.UART_RX +@200 +-SPI +@28 +HACK_tb.SPI_CSX +HACK_tb.SPI_SDI +HACK_tb.SPI_SDO +HACK_tb.SPI_SCK +@200 +-SRAM +@22 +HACK_tb.SRAM_ADDR[17:0] +@28 +HACK_tb.SRAM_CSX +HACK_tb.SRAM_OEX +HACK_tb.SRAM_WEX +@22 +HACK_tb.SRAM_DATA[15:0] +@200 +-GO +@28 +HACK_tb.HACK.loadGO +@200 +-DEBUG +@28 +HACK_tb.HACK.loadDEBUG0 +@820 +HACK_tb.HACK.outDEBUG0[15:0] +@28 +HACK_tb.HACK.loadDEBUG1 +@24 +HACK_tb.HACK.outDEBUG1[15:0] +@28 +HACK_tb.HACK.loadDEBUG2 +@24 +HACK_tb.HACK.outDEBUG2[15:0] +@28 +HACK_tb.HACK.loadDEBUG3 +@24 +HACK_tb.HACK.outDEBUG3[15:0] +@28 +HACK_tb.HACK.loadDEBUG4 +@24 +HACK_tb.HACK.outDEBUG4[15:0] +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/06_IO_Devices/00_HACK/HACK_tb.v b/06_IO_Devices/00_HACK/HACK_tb.v new file mode 100644 index 0000000..65394f6 --- /dev/null +++ b/06_IO_Devices/00_HACK/HACK_tb.v @@ -0,0 +1,121 @@ +`timescale 10ns/1ns +`default_nettype none +module HACK_tb(); + + // IN,OUT + reg CLK = 1; + reg [1:0] BUT = 3; + wire [1:0] LED; + wire UART_TX; + wire UART_RX; + wire SPI_SDO; + wire SPI_SDI; + wire SPI_SCK; + wire SPI_CSX; + wire [17:0] SRAM_ADDR; + wire [15:0] SRAM_DATA; + wire SRAM_WEX; + wire SRAM_OEX; + wire SRAM_CSX; + wire LCD_DCX; + wire LCD_SDO; + wire LCD_SCK; + wire LCD_CSX; + reg RTP_SDI; + wire RTP_SDO; + wire RTP_SCK; + + // Part + HACK HACK( + .CLK(CLK), // external clock 100 MHz + .BUT(BUT), // user button ("pushed down" == 0) ("up" == 1) + .LED(LED), // leds (0 off, 1 on) + .UART_RX(UART_RX), // UART receive + .UART_TX(UART_TX), // UART transmit + .SPI_SDO(SPI_SDO), // SPI serial data out + .SPI_SDI(SPI_SDI), // SPI serial data in + .SPI_SCK(SPI_SCK), // SPI serial clock + .SPI_CSX(SPI_CSX), // SPI chip select not + .SRAM_ADDR(SRAM_ADDR), // SRAM address 18 Bit = 256K + .SRAM_DATA(SRAM_DATA), // SRAM data 16 Bit + .SRAM_WEX(SRAM_WEX), // SRAM write_enable_not + .SRAM_OEX(SRAM_OEX), // SRAM output_enable_not + .SRAM_CSX(SRAM_CSX), // SRAM chip_select_not + .LCD_DCX(LCD_DCX), // LCD data/command not + .LCD_SDO(LCD_SDO), // LCD serial data out + .LCD_SCK(LCD_SCK), // LCD serial clock + .LCD_CSX(LCD_CSX), // LCD chip select not + .RTP_SDI(RTP_SDI), // RTP serial data in + .RTP_SDO(RTP_SDO), // RTP serial data out in + .RTP_SCK(RTP_SCK) // RTP serial clock + ); + + // Simulate + always #0.5 CLK = ~CLK; + integer n=0; + always @(posedge CLK) n=n+1; + + // Compare + reg [9:0] uart=10'b1111111111; + reg [15:0] baudrate = 0; + always @(posedge CLK) + baudrate <= ((baudrate==866)?0:baudrate+1); + always @(posedge CLK) begin + uart <= (n==5000)?((82<<2)+1):(n==15000)?((88<<2)+1):((baudrate==866)?{1'b1,uart[9:1]}:uart); + end + wire shift = (baudrate==866); + assign UART_RX = uart[0]; + + //Simulate SPI + reg spi_sleep=1; + reg [31:0] spi_cmd=0; + reg [95:0] spi=0; + assign SPI_SDI = (SPI_CSX | spi_sleep) ? 1'bz:spi[95]; + always @(posedge (SPI_SCK)) + spi <= {spi[95:0],1'b0}; + always @(posedge (SPI_SCK)) + spi_cmd <= {spi_cmd[30:0],SPI_SDO}; + always @(negedge (SPI_CSX)) + spi_cmd <= 0; + always @(spi_cmd) begin + if (spi_cmd==32'h000000AB) spi_sleep <= 0; + if (spi_cmd==32'h000000B9) spi_sleep <= 1; + if (spi_cmd==32'h03040000) spi <= "SPI! 123"; + if (spi_cmd==32'h03010000) spi <= 96'h1001_FC10_1000_E308_0000_EA87; + end + + //Simulate SRAM + reg [16:0] sram[0:7]; + always @(posedge CLK) + if (~SRAM_WEX&&SRAM_OEX&&~SRAM_CSX) sram[SRAM_ADDR] <= SRAM_DATA; + assign SRAM_DATA = (~SRAM_CSX&&~SRAM_OEX)?sram[SRAM_ADDR]:16'bzzzzzzzzzzzzzzzz; + //Simulate LCD + reg [7:0] lcd_c; + reg [15:0] lcd_d; + always @(posedge LCD_SCK) begin + lcd_c <= (~LCD_DCX)?{lcd_c[6:0],LCD_SDO}:lcd_c; + lcd_d <= (LCD_DCX)?{lcd_d[6:0],LCD_SDO}:lcd_d; + end + always @(negedge LCD_CSX) begin + lcd_c <= 0; + lcd_d <= 0; + end + //simulate BUT + always @(posedge CLK) begin + if (n==10000) BUT<=0; + if (n==20000) BUT<=1; + if (n==30000) BUT<=2; + end + + initial begin + $dumpfile("HACK_tb.vcd"); + $dumpvars(0, HACK_tb); + + $display("------------------------"); + $display("Testbench: Hack"); + + #40000 + $finish; + end + +endmodule diff --git a/06_IO_Devices/00_HACK/Include.v b/06_IO_Devices/00_HACK/Include.v new file mode 100644 index 0000000..60adf60 --- /dev/null +++ b/06_IO_Devices/00_HACK/Include.v @@ -0,0 +1,49 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/RAM256.v" +`include "../../03_Sequential_Logic/RAM512.v" +`include "../../03_Sequential_Logic/RAM3840.v" +`include "../../03_Sequential_Logic/BitShift9R.v" +`include "../../03_Sequential_Logic/BitShift8L.v" + +`include "../../05_Computer_Architecture/CPU.v" +`include "../../05_Computer_Architecture/Memory.v" +`include "../../05_Computer_Architecture/ROM.v" +`include "../../05_Computer_Architecture/Clock25_Reset20.v" + +`include "../../06_IO_Devices/HACK.v" +`include "../../06_IO_Devices/UartTX.v" +`include "../../06_IO_Devices/UartRX.v" +`include "../../06_IO_Devices/SPI.v" +`include "../../06_IO_Devices/InOut.v" +`include "../../06_IO_Devices/SRAM_D.v" +`include "../../06_IO_Devices/GO.v" +`include "../../06_IO_Devices/LCD.v" +`include "../../06_IO_Devices/RTP.v" diff --git a/06_IO_Devices/00_HACK/apio.ini b/06_IO_Devices/00_HACK/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/06_IO_Devices/00_HACK/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/06_IO_Devices/00_HACK/iCE40HX1K-EVB.pcf b/06_IO_Devices/00_HACK/iCE40HX1K-EVB.pcf new file mode 100644 index 0000000..78c9fed --- /dev/null +++ b/06_IO_Devices/00_HACK/iCE40HX1K-EVB.pcf @@ -0,0 +1,68 @@ +# physical constrain file +# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40HX1K-EVB +# compare to the schematic of the board and the datasheet of fpga + +set_io CLK 15 # SYSCLOCK 100 MHz + +set_io BUT[0] 41 # BUT1 +set_io BUT[1] 42 # BUT2 + +set_io LED[0] 40 # LED1 +set_io LED[1] 51 # LED2 + +set_io UART_RX 36 # PIO2_8/RxD connected to pin 3 of UEXT (PGM) +set_io UART_TX 37 # PIO2_9/TxD connected to pin 4 of UEXT (PGM) + +set_io SPI_SDO 45 # iCE40-SDO +set_io SPI_SDI 46 # iCE40-SDI +set_io SPI_SCK 48 # iCE40-SCK +set_io SPI_CSX 49 # iCE40-SS_B + +set_io SRAM_ADDR[0] 79 # SA0 +set_io SRAM_ADDR[1] 80 # SA1 +set_io SRAM_ADDR[2] 81 # SA2 +set_io SRAM_ADDR[3] 82 # SA3 +set_io SRAM_ADDR[4] 83 # SA4 +set_io SRAM_ADDR[5] 85 # SA5 +set_io SRAM_ADDR[6] 86 # SA6 +set_io SRAM_ADDR[7] 87 # SA7 +set_io SRAM_ADDR[8] 89 # SA8 +set_io SRAM_ADDR[9] 90 # SA9 +set_io SRAM_ADDR[10] 91 # SA10 +set_io SRAM_ADDR[11] 93 # SA11 +set_io SRAM_ADDR[12] 94 # SA12 +set_io SRAM_ADDR[13] 95 # SA13 +set_io SRAM_ADDR[14] 96 # SA14 +set_io SRAM_ADDR[15] 97 # SA15 +set_io SRAM_ADDR[16] 99 # SA16 +set_io SRAM_ADDR[17] 100 # SA17 + +set_io SRAM_CSX 78 # SRAM_#CS +set_io SRAM_OEX 74 # SRAM_#OE +set_io SRAM_WEX 73 # SRAM_#WE + +set_io SRAM_DATA[0] 62 # SD0 +set_io SRAM_DATA[1] 63 # SD1 +set_io SRAM_DATA[2] 64 # SD2 +set_io SRAM_DATA[3] 65 # SD3 +set_io SRAM_DATA[4] 66 # SD4 +set_io SRAM_DATA[5] 68 # SD5 +set_io SRAM_DATA[6] 69 # SD6 +set_io SRAM_DATA[7] 71 # SD7 +set_io SRAM_DATA[8] 72 # SD8 +set_io SRAM_DATA[9] 60 # SD9 +set_io SRAM_DATA[10] 59 # SD10 +set_io SRAM_DATA[11] 57 # SD11 +set_io SRAM_DATA[12] 56 # SD12 +set_io SRAM_DATA[13] 54 # SD13 +set_io SRAM_DATA[14] 53 # SD14 +set_io SRAM_DATA[15] 52 # SD15 + +set_io LCD_DCX 1 # PIO3_1A connected to pin 5 of GPIO1 +set_io LCD_SDO 2 # PIO3_1B connected to pin 7 of GPIO1 +set_io LCD_SCK 3 # PIO3_2A connected to pin 9 of GPIO1 +set_io LCD_CSX 4 # PIO3_2B connected to pin 11 of GPIO1 + +set_io RTP_SDI 7 # PIO3_3A connected to pin 13 of GPIO1 +set_io RTP_SDO 8 # PIO3_3B connected to pin 15 of GPIO1 +set_io RTP_SCK 9 # PIO3_5A connected to pin 17 of GPIO1 diff --git a/06_IO_Devices/01_UartTX/ICE40PGM.jpg b/06_IO_Devices/01_UartTX/ICE40PGM.jpg new file mode 100644 index 0000000..816a283 Binary files /dev/null and b/06_IO_Devices/01_UartTX/ICE40PGM.jpg differ diff --git a/06_IO_Devices/01_UartTX/Include.v b/06_IO_Devices/01_UartTX/Include.v new file mode 100644 index 0000000..8efe6d3 --- /dev/null +++ b/06_IO_Devices/01_UartTX/Include.v @@ -0,0 +1,40 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift9R.v" +`include "../../03_Sequential_Logic/BitShift8L.v" + +`include "../../06_IO_Devices/UartTX.v" +`include "../../06_IO_Devices/UartRX.v" +`include "../../06_IO_Devices/SPI.v" +`include "../../06_IO_Devices/InOut.v" +`include "../../06_IO_Devices/SRAM_D.v" +`include "../../06_IO_Devices/GO.v" +`include "../../06_IO_Devices/LCD.v" +`include "../../06_IO_Devices/RTP.v" diff --git a/06_IO_Devices/01_UartTX/Makefile b/06_IO_Devices/01_UartTX/Makefile new file mode 100644 index 0000000..9a48181 --- /dev/null +++ b/06_IO_Devices/01_UartTX/Makefile @@ -0,0 +1,12 @@ +NAME = hello + +all: asm install + +asm: + ../../tools/Assembler/assembler.pyc $(NAME).asm +install: + cp $(NAME).hack ../00_HACK/ROM.hack +clean: + rm -f *.hack *~ + +.PHONY: all clean diff --git a/06_IO_Devices/01_UartTX/Readme.md b/06_IO_Devices/01_UartTX/Readme.md new file mode 100644 index 0000000..d2d1306 --- /dev/null +++ b/06_IO_Devices/01_UartTX/Readme.md @@ -0,0 +1,111 @@ +## 01 UartTX + +The special function register `UartTX` mapped to memory address 4098 enables HACK to send chars to the outer world over UART with 115200 baud 8N1. The timing diagramm for the TX wire should look like: + +![](timing.jpg) + +During idle TX line is high (logic 1). Transmission of a byte (8 bits) is initiated by the so called start bit, which always is low (logic 0), followed by the 8 data bits, starting with the least significant bit. The transmission is finished by sending the stop bit, which always is high (logic 1). +This protocoll is refered as 8N1 meaning (8 data bits, no parity bit, 1 stop bit). We use a transmission speed of 115200 baud (bits per second), meaning that each bit takes 1s/115200 = 8.68us or 217 cycles of the internal 25MHz clock clk. + +### Chip specification + +| IN/OUT | wire | function | +| ------ | ------- | --------------------------------------------------- | +| IN | in[7:0] | byte to be sent. | +| IN | load | =1 initiates the transmission | +| OUT | out[15] | =1 chip is busy, =0 chip is ready to send next byte | +| OUT | TX | transmission wire | + +When load = 1 the chip starts serial transmission of the byte in[7:0] to the TX line according to the protocoll 8N1 with 115200 baud. During transmission out[15] is set to high (busy). The transmission is finished after 2170 clock cycles (10 byte a 217 cycle each). When transmission completes out[15] goes low again (ready). + +### Proposed Implementation + +Use a `Bit` to store the state (0 = ready, 1 = busy). Use a counter `PC` to count from 0 to 216. When clocked at 25MHz, this counter will produce the baudrate of 115200 bits per second. A second counter `PC` counts from 0 to 9 (the 10 bits to send). Finally we need a `BitShift9R`. This will be loaded with the bit pattern to be send (startbit, 8 data bits). + +![](UartTX.png) + +### memory map + +The special function register `UartTX` is mapped to memory map of HACK according to: + +| address | I/O device | R/W | function | +| ------- | ---------- | --- | ------------------------------------- | +| 4098 | UART_TX | R | out[15]=1 if busy, out[15]=0 if ready | +| 4098 | UART_TX | W | send char in[7:0] to TX | + +### hello.asm + +To test HACK with `UartTX` we need a little machine language programm `hello.asm`, which sends the String "Hi" to UART. + +**Attention:** Use a loop to wait until UartTX is ready to send the next byte. + +### UartTX in real hardware + +The programmer Olimexino 32u4 can also be used as bridge to connect the PC to iCE40HX1K-EVB over UART. This can be done with the 10 wire UEXT cable which goes into the PGM1 connector of iCE40HX1K-EVB. + +![](ICE40PGM.jpg) + +**Note:** To connect RX and TX lines of UEXT-connector with iCE40-chip on iCE40-HX1K-EVB find the solder-jumper-pads RxD_E1 and TxD_E1 near the UEXT connector (refer to [datasheets/iCE40HX1K-EVB](../datasheets/iCE40HX1K-EVB_Rev_B.pdf)) and solder them together as in the foto below. + +![](UARTJumper.jpg) + +The programmer olimexino 32u4 works in two different mode: + +- Mode 1 (yellow led on): programmer of iCE40-board. Used with iceprogduino. +- Mode 2 (green led on): UART Bridge to iCE40 chip. Use with terminal programm (e.g. tio or screen on linux). + +To switch between the modes press the hardware button on olimexino 32u4 (HWB). + +Now iCE40HX1K is connected to RX,TX of olimexino 32u4 according to `iCE40HX1K-EVB.pcf`. (Check by comparing the schematic of iCE40HX1K-EVB). + +``` +set_io UART_RX 36 # PIO2_8/RxD connected to pin 3 of UEXT (PGM) +set_io UART_TX 37 # PIO2_9/TxD connected to pin 4 of UEXT (PGM) +``` + +*** + +### Project + +* Implement `UartTX` and simulate with testbench. + + ``` + $ cd 01_UartTX + $ apio clean + $ apio sim + ``` + +* Compare with CMP: + + ![](UartTX_tb.png) + +* Edit `HACK` and add the special function register `UartTX` to the memory address 4098. + +* Implement `hello.asm` and run in simulation: + + ``` + $ cd 01_UartTX + $ make + $ cd ../00_HACK + $ apio clean + $ apio sim + ``` + +* Check the TX wire of the simulation and look for the transmission of "Hi". + + ![](hi.png) + +* build and upload HACK with `hello.asm` in ROM.BIN to iCE40HX1K-EVB. + +* switch olimexino 32u4 to UART-Bridge + +* open Terminal on your computer + +* press reset button on iCE40HX1K-EVB and see if wou can recieve "Hi" on your Computer. + + ``` + $ cd 00_HACK + $ apio clean + $ apio upload + $ tio /dev/ttyACM0 + ``` diff --git a/06_IO_Devices/01_UartTX/UARTJumper.jpg b/06_IO_Devices/01_UartTX/UARTJumper.jpg new file mode 100644 index 0000000..7088e56 Binary files /dev/null and b/06_IO_Devices/01_UartTX/UARTJumper.jpg differ diff --git a/06_IO_Devices/01_UartTX/UartTX.dia b/06_IO_Devices/01_UartTX/UartTX.dia new file mode 100644 index 0000000..205d4a3 Binary files /dev/null and b/06_IO_Devices/01_UartTX/UartTX.dia differ diff --git a/06_IO_Devices/01_UartTX/UartTX.png b/06_IO_Devices/01_UartTX/UartTX.png new file mode 100644 index 0000000..0c98e36 Binary files /dev/null and b/06_IO_Devices/01_UartTX/UartTX.png differ diff --git a/06_IO_Devices/01_UartTX/UartTX_tb.gtkw b/06_IO_Devices/01_UartTX/UartTX_tb.gtkw new file mode 100644 index 0000000..74aeca0 --- /dev/null +++ b/06_IO_Devices/01_UartTX/UartTX_tb.gtkw @@ -0,0 +1,43 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Fri Dec 23 15:04:28 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/06_IO_Devices/01_UartTX/UartTX_tb.vcd" +[dumpfile_mtime] "Fri Dec 23 15:03:47 2022" +[dumpfile_size] 3855989 +[savefile] "/home/micha/gitlab/nand2tetris/06_IO_Devices/01_UartTX/UartTX_tb.gtkw" +[timestart] 0 +[size] 1659 507 +[pos] 165 50 +*-26.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] UartTX_tb. +[sst_width] 281 +[signals_width] 170 +[sst_expanded] 1 +[sst_vpaned_height] 108 +@28 +UartTX_tb.clk +@200 +-IN +@28 +UartTX_tb.load +@22 +UartTX_tb.in[15:0] +@200 +-OUT +@22 +UartTX_tb.out[15:0] +@28 +UartTX_tb.TX +@200 +-CMP +@23 +UartTX_tb.out_cmp[15:0] +@28 +UartTX_tb.TX_cmp +@200 +-Test +@28 +UartTX_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/06_IO_Devices/01_UartTX/UartTX_tb.png b/06_IO_Devices/01_UartTX/UartTX_tb.png new file mode 100644 index 0000000..27cf98a Binary files /dev/null and b/06_IO_Devices/01_UartTX/UartTX_tb.png differ diff --git a/06_IO_Devices/01_UartTX/UartTX_tb.v b/06_IO_Devices/01_UartTX/UartTX_tb.v new file mode 100644 index 0000000..9aa3f96 --- /dev/null +++ b/06_IO_Devices/01_UartTX/UartTX_tb.v @@ -0,0 +1,74 @@ +`timescale 10ns/1ns +`default_nettype none + +module UartTX_tb(); + + // IN,OUT + reg clk = 0; + reg load = 0; + reg [15:0] in = 0; + wire TX; + wire [15:0] out; + + // Part + UartTX UartTX( + .clk(clk), + .load(load), + .in(in), + .TX(TX), + .out(out) + ); + + // Simulate + always #2 clk=~clk; + wire trigger; + assign trigger = (n==1000) || (n==5000) || (n==9000); + always @(posedge clk) begin + in <= trigger?$random:in; + load <= trigger; + end + + // Compare + reg [9:0] uart=10'b1111111111; + reg [15:0] baudrate = 0; + reg [15:0] bits = 0; + wire is216=(baudrate==216); + reg [15:0] out_cmp=0; + always @(posedge clk) + out_cmp <=load?16'h8000:(bits==9)&is216?16'd0:out_cmp; + always @(posedge clk) + bits <= (load)?0:is216?bits+1:bits; + always @(posedge clk) + baudrate <= (is216?0:out_cmp?baudrate+1:baudrate); + always @(posedge clk) + uart <= (load)?((in<<2)|1):(is216?{1'b1,uart[9:1]}:uart); + wire TX_cmp; + assign TX_cmp = uart[1]; + + reg fail = 0; + reg [31:0] n = 0; + task check; + #4 + if ((TX != TX_cmp) ||(out != out_cmp)) + begin + $display("FAIL: clk=%1b, load=%1b, in=%16b, out=%16b, TX=%1b",clk,load,in,out,TX); + fail=1; + end + endtask + + initial begin + $dumpfile("UartTX_tb.vcd"); + $dumpvars(0, UartTX_tb); + + $display("------------------------"); + $display("Testbench: UartTX"); + + for (n=0; n<13000;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/06_IO_Devices/01_UartTX/apio.ini b/06_IO_Devices/01_UartTX/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/06_IO_Devices/01_UartTX/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/06_IO_Devices/01_UartTX/hello.asm b/06_IO_Devices/01_UartTX/hello.asm new file mode 100644 index 0000000..cbec374 --- /dev/null +++ b/06_IO_Devices/01_UartTX/hello.asm @@ -0,0 +1,4 @@ +// hello.asm +// this little assembler programm outputs "Hi" on UART_TX +// +// Put your code here: diff --git a/06_IO_Devices/01_UartTX/hi.png b/06_IO_Devices/01_UartTX/hi.png new file mode 100644 index 0000000..d2cbd1d Binary files /dev/null and b/06_IO_Devices/01_UartTX/hi.png differ diff --git a/06_IO_Devices/01_UartTX/timing.jpg b/06_IO_Devices/01_UartTX/timing.jpg new file mode 100644 index 0000000..08ecf44 Binary files /dev/null and b/06_IO_Devices/01_UartTX/timing.jpg differ diff --git a/06_IO_Devices/02_UartRX/Include.v b/06_IO_Devices/02_UartRX/Include.v new file mode 100644 index 0000000..8efe6d3 --- /dev/null +++ b/06_IO_Devices/02_UartRX/Include.v @@ -0,0 +1,40 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift9R.v" +`include "../../03_Sequential_Logic/BitShift8L.v" + +`include "../../06_IO_Devices/UartTX.v" +`include "../../06_IO_Devices/UartRX.v" +`include "../../06_IO_Devices/SPI.v" +`include "../../06_IO_Devices/InOut.v" +`include "../../06_IO_Devices/SRAM_D.v" +`include "../../06_IO_Devices/GO.v" +`include "../../06_IO_Devices/LCD.v" +`include "../../06_IO_Devices/RTP.v" diff --git a/06_IO_Devices/02_UartRX/Makefile b/06_IO_Devices/02_UartRX/Makefile new file mode 100644 index 0000000..0a47836 --- /dev/null +++ b/06_IO_Devices/02_UartRX/Makefile @@ -0,0 +1,12 @@ +NAME = echo + +all: asm install + +asm: + ../../tools/Assembler/assembler.pyc $(NAME).asm +install: + cp $(NAME).hack ../00_HACK/ROM.hack +clean: + rm -f *.hack *~ + +.PHONY: all clean diff --git a/06_IO_Devices/02_UartRX/Readme.md b/06_IO_Devices/02_UartRX/Readme.md new file mode 100644 index 0000000..f092af5 --- /dev/null +++ b/06_IO_Devices/02_UartRX/Readme.md @@ -0,0 +1,85 @@ +## 02 UartRX + +The special functino register `UartRX` receives bytes over UART with 8N1 at 115200 baud. When RX line goes low, the sampling process is initiated. Sampling of the individual bits is done in the middle of each bit. + +![](timing.jpg) + +### Chip specification + +| IN/OUT | wire | function | +| ------ | -------- | ----------------------------------------------------------------------- | +| IN | clear | =1 clears the data register, chip is now ready to receive the next byte | +| IN | RX | receive wire | +| OUT | out[15] | =1 waiting for next byte, =0 byte completed | +| OUT | out[7:0] | last received byte (when out[15]=0) | + +When clear = 1 the chip clears the data register and is ready to receive next byte. out[15] is set to 1 to show, that chip is ready to receive next byte. When RX goes low the chip starts sampling the RX line. After reading of byte completes, chip ouputs the received byte to out[7:0] with out[15]=0. The sampling of a complete byte takes 2170 clock cycles. Sampling is done in the middle of each bit at clock count number108. + +### Proposed Implementation + +Use a `Bit` to store run state. run goes high, when rx=0 and run=0. run stops, when last bit is received. When run=1 a Counter increments every clock cycle. After 217 clock cycles the Counter resets. A second counter increments every 217 cycles to count the bits. At count number 108 the rx is shifted into a `BitShift9R`. When transmission of the byte completes (10-bit sampled), the content of the shiftregister is loaded into the data register with out[15] set to 0 (valid byte). The data register can be cleared by software (clear) at any time by setting the highest bit of data register to 1 (byte not ready yet). + +**Attention:** RX must pass a `DFF` to be registered in the clock domain of clk. + +![](UartRX.png) + +### Memory map + +The special function register `UartRX` is mapped to memory map of HACK according to: + +| address | I/O device | R/W | function | +| ------- | ---------- | --- | ----------------------------------------------------------------------------------------------- | +| 4099 | UART_RX | R | when out[15]=1 data register is not valid, when out[15]=0 out[7:0] holds the last received byte | +| 4099 | UART_RX | W | clear data register | + +### echo.asm + +To test HACK with `UartRX` we need a little machine language programm `echo.asm`, which reads bytes from UartRX and sends them to UART_TX. + +**Attention:** Use a loop to wait until UartRX is ready before reading the next byte. Clear data register of UartRX after reading a byte. + +*** + +### Project + +* Implement `UartRX.v` and simulate with test bench: + + ``` + $ cd 02_UartRX + $ apio clean + $ apio sim + ``` + +* Compare with CMP: + + ![](UartRX_tb.png) + +* Edit `HACK.v` and add special function register `UartRX` to memory address 4099. +- Implement `echo.asm` and run in simulation: + + ``` + $ cd 02_UartRX + $ make + $ cd ../00_HACK + $ apio clean + $ apio sim + ``` + +- Check the TX wire of the simulation and compare with the received bytes at RX. + + ![](echo.png) + +- build and upload HACK with `echo.asm` preloaded into ROM to iCE40HX1K-EVB. + +- switch olimexino 32u4 to UART-Bridge (yellow led) + +- open terminal on your computer + +- type chars in the terminal and see if they are echoed by HACK. + + ``` + $ cd 00_HACK + $ apio clean + $ apio upload + $ tio /dev/ttyACM0 + ``` diff --git a/06_IO_Devices/02_UartRX/UartRX.dia b/06_IO_Devices/02_UartRX/UartRX.dia new file mode 100644 index 0000000..84332d1 Binary files /dev/null and b/06_IO_Devices/02_UartRX/UartRX.dia differ diff --git a/06_IO_Devices/02_UartRX/UartRX.png b/06_IO_Devices/02_UartRX/UartRX.png new file mode 100644 index 0000000..45e8421 Binary files /dev/null and b/06_IO_Devices/02_UartRX/UartRX.png differ diff --git a/06_IO_Devices/02_UartRX/UartRX_tb.gtkw b/06_IO_Devices/02_UartRX/UartRX_tb.gtkw new file mode 100644 index 0000000..eafe9d4 --- /dev/null +++ b/06_IO_Devices/02_UartRX/UartRX_tb.gtkw @@ -0,0 +1,34 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Fri Dec 30 13:36:50 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/02_UartRX/UartRX_tb.vcd" +[dumpfile_mtime] "Fri Dec 30 13:36:33 2022" +[dumpfile_size] 3203743 +[savefile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/02_UartRX/UartRX_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -1 -1 +*-26.000000 162700000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] UartRX_tb. +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 259 +@28 +UartRX_tb.clk +@200 +-IN +@28 +UartRX_tb.clear +UartRX_tb.rx +@200 +-OUT +@22 +UartRX_tb.out[15:0] +@200 +-CMP +@22 +UartRX_tb.out_cmp[15:0] +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/06_IO_Devices/02_UartRX/UartRX_tb.png b/06_IO_Devices/02_UartRX/UartRX_tb.png new file mode 100644 index 0000000..f748c86 Binary files /dev/null and b/06_IO_Devices/02_UartRX/UartRX_tb.png differ diff --git a/06_IO_Devices/02_UartRX/UartRX_tb.v b/06_IO_Devices/02_UartRX/UartRX_tb.v new file mode 100644 index 0000000..cd2d637 --- /dev/null +++ b/06_IO_Devices/02_UartRX/UartRX_tb.v @@ -0,0 +1,76 @@ +`timescale 10ns/1ns +`default_nettype none + +module UartRX_tb(); + + // IN,OUT + reg clk = 0; + reg clear = 0; + wire RX; + wire [15:0] out; + + // Part + UartRX UARTRX( + .clk(clk), + .clear(clear), + .RX(RX), + .out(out) + ); + + // Simulate + always #2 clk=~clk; + wire trigger; + reg load=0; + assign trigger = (n==1000) || (n==5000) || (n==9000); + reg [15:0] in=0; + always @(posedge clk) begin + in <= trigger?$random:in; + load <= trigger; + clear <= (n==200); + end + + // Compare + reg [9:0] uart=10'b1111111111; + reg [15:0] baudrate = 0; + reg [15:0] bits = 0; + always @(posedge clk) + bits <= (load&~out_tx)?0:((baudrate==216)?bits+1:bits); + always @(posedge clk) + baudrate <= (load&~out_tx)?0:((baudrate==216)?0:(out_tx)?baudrate+1:baudrate); + always @(posedge clk) + uart <= (load&~out_tx)?((in<<2)|1):((baudrate==216)?{1'b1,uart[9:1]}:uart); + reg out_tx = 0; + always @(posedge clk) + out_tx <= load?1:((bits==10)?0:out_tx); + assign RX = uart[1]; + + reg [15:0] out_cmp =0; + always @(posedge clk) + out_cmp <= clear?16'b1000000000000000:((baudrate==216)&(bits==9)?in& 16'h00ff:out_cmp); + reg fail = 0; + reg [31:0] n = 0; + task check; + #4 + if (out_cmp != out) + begin + $display("FAIL: clk=%1b, out=%16b",clk,out); + fail=1; + end + endtask + + initial begin + $dumpfile("UartRX_tb.vcd"); + $dumpvars(0, UartRX_tb); + + $display("------------------------"); + $display("Testbench: UartRX"); + + for (n=0; n<10000;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/06_IO_Devices/02_UartRX/apio.ini b/06_IO_Devices/02_UartRX/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/06_IO_Devices/02_UartRX/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/06_IO_Devices/02_UartRX/echo.asm b/06_IO_Devices/02_UartRX/echo.asm new file mode 100644 index 0000000..6f13196 --- /dev/null +++ b/06_IO_Devices/02_UartRX/echo.asm @@ -0,0 +1,6 @@ +// echo.asm +// +// receive byte over UART_RX and transmit the received byte to UART_TX +// repeat in an endless loop +// +// Put your code here: diff --git a/06_IO_Devices/02_UartRX/echo.png b/06_IO_Devices/02_UartRX/echo.png new file mode 100644 index 0000000..c07e31a Binary files /dev/null and b/06_IO_Devices/02_UartRX/echo.png differ diff --git a/06_IO_Devices/02_UartRX/timing.jpg b/06_IO_Devices/02_UartRX/timing.jpg new file mode 100644 index 0000000..3319469 Binary files /dev/null and b/06_IO_Devices/02_UartRX/timing.jpg differ diff --git a/06_IO_Devices/03_SPI/Include.v b/06_IO_Devices/03_SPI/Include.v new file mode 100644 index 0000000..8efe6d3 --- /dev/null +++ b/06_IO_Devices/03_SPI/Include.v @@ -0,0 +1,40 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift9R.v" +`include "../../03_Sequential_Logic/BitShift8L.v" + +`include "../../06_IO_Devices/UartTX.v" +`include "../../06_IO_Devices/UartRX.v" +`include "../../06_IO_Devices/SPI.v" +`include "../../06_IO_Devices/InOut.v" +`include "../../06_IO_Devices/SRAM_D.v" +`include "../../06_IO_Devices/GO.v" +`include "../../06_IO_Devices/LCD.v" +`include "../../06_IO_Devices/RTP.v" diff --git a/06_IO_Devices/03_SPI/Makefile b/06_IO_Devices/03_SPI/Makefile new file mode 100644 index 0000000..2f8c32f --- /dev/null +++ b/06_IO_Devices/03_SPI/Makefile @@ -0,0 +1,12 @@ +NAME = cat + +all: asm install + +asm: + ../../tools/Assembler/assembler.pyc $(NAME).asm +install: + cp $(NAME).hack ../00_HACK/ROM.hack +clean: + rm -f *.hack *~ + +.PHONY: all clean diff --git a/06_IO_Devices/03_SPI/Readme.md b/06_IO_Devices/03_SPI/Readme.md new file mode 100644 index 0000000..aee0ccd --- /dev/null +++ b/06_IO_Devices/03_SPI/Readme.md @@ -0,0 +1,119 @@ +## 03 SPI + +The special function register `SPI` memory mapped to address 4100 enables HACK to read/write bytes from the spi flash memory chip W25Q16BV situated on iCE40HX1K-EVB. The timing diagramm for SPI communication looks like the following diagram (we use CPOL=0 and CPHA=0). + +![](spi-timing.png) + +### Chip specification + +| IN/OUT | wire | function | +| ------ | -------- | ------------------------------------------- | +| IN | in[7:0] | byte to be sent. | +| IN | in[8] | =1 send byte and set CSX low | +| IN | in[8] | =0 pull CSX high without sending byte | +| IN | load | =1 initiates the transmission, when in[8]=1 | +| OUT | out[15] | =0 chip is busy, =0 chip is ready | +| OUT | out[7:0] | received byte (when out[15]=0) | +| OUT | CSX | chip select not | +| OUT | SDO | serial data out | +| OUT | SCK | serial clock | +| IN | SDI | serial data in | + +When load=1 and in[8]=0 transmission of byte in[7:0] is initiated. CSX is goes low (and stays low even when transmission is completed). The byte is send to SDO bitwise together with 8 clock signals on SCK. At the same time the SPI receives a byte at SDI. During transmission out[15] is 1. After 16 clock cycles the transmission of one byte is completed. out[15] goes low and SPI outputs the received byte to out[7:0]. + +When load=1 and in[8]=1 CSX goes high without transmission of any bit. + +**Attention:** Sampling of SDO is done at rising edge of SCK and shifting is done at falling edge of SCK. + +### Proposed Implementation + +Use a `Bit` to store the state (0 = ready, 1 = busy) which is output to out[15]. Use a counter `PC` to count from 0 to 15. Finally we need a `BitShift8L`. This will be loaded with the byte in[7:0] to be send. Another `Bit` will sample the SDI wire when SCK=0 and shift the stored bit into the `BitShift8L` when SCK=1. After 8 bits are transmitted the module cleares out[15] and outputs the received byte to out[7:0]. + +![](SPI.png) + +### Memory map + +The special function register `SPI` is mapped to memory map of HACK according to: + +| address | I/O device | R/W | function | +| ------- | ---------- | --- | ----------------------------------------- | +| 4100 | SPI | R | out[15]=1 if busy, out[7:0] received byte | +| 4100 | SPI | W | start transmittion of byte in[7:0] | + +### cat.asm + +To test HACK with SPI we need a little machine language programm `cat.asm`, which reads 4 consecutive bytes of SPI flash memory chip W25Q16BV of iCE40HX1K-EVB, starting at address 0x040000 (256k) and sends them to UART_TX. + +According to the datasheet of spi flash rom chip W25Q16BV the commands needed to read the flash rom chip are: + +| command | function | +| ------------------- | ---------------------------------------------------------------------- | +| 0xAB | wake up from deep power down (wait 3us) before launching next command. | +| 0x03 0x04 0x00 0x00 | read data (command 0x03) starting at address 0x040000 (256k) | +| 0xB9 | go in power down | + +### SPI in real hardware + +The board iCE40HX1K-EVB comes with a SPI flash rom chip W25Q16BV. The chip is already connected to iCE40HX1K according `iCE40HX1K-EVB.pcf` (Compare with schematic [iCE40HX1K_EVB](../../doc/iCE40HX1K-EVB_Rev_B.pdf). + +``` +set_io SPI_SDO 45 # iCE40-SDO +set_io SPI_SDI 46 # iCE40-SDI +set_io SPI_SCK 48 # iCE40-SCK +set_io SPI_CSX 49 # iCE40-SS_B +``` + +*** + +### Project + +* Implement `SPI.v` and test with testbench: + + ``` + $ cd 03_SPI + $ apio clean + $ apio sim + ``` + +* Compare output `OUT` of special function tregister `SPI` with `CMP`. + + ![](spi_tb.png) + +* Add special function register`SPI` to `HACK.v` at memory address 4100. + +* Implement `cat.asm` and test in simulation: + + ``` + $ cd 03_SPI + $ make + $ cd ../00_HACK + $ apio clean + $ apio sim + ``` + +* Check the wake up command 0xAB: + + ![](spi_wakeup.png) + +* Check command 0x03040000 (read from address 0x040000) + + ![](spi_read040000.png) + +* Check reading of string "SPI!" output to UartTX. + + ![](echo.png) + +* preload the SPI memory chip with some text file at address 0x040000. + +* build and upload HACK with `cat.asm` in ROM.BIN to iCE40HX1K-EVB. + + ``` + $ echo SPI! > spi.txt + $ iceprogduino -o 256k -w spi.txt + $ cd 00_HACK + $ apio clean + $ apio upload + $ tio /dev/ttyACM0 + ``` + +* Check if you see "SPI!" in your terminal. diff --git a/06_IO_Devices/03_SPI/SPI.dia b/06_IO_Devices/03_SPI/SPI.dia new file mode 100644 index 0000000..6073848 Binary files /dev/null and b/06_IO_Devices/03_SPI/SPI.dia differ diff --git a/06_IO_Devices/03_SPI/SPI.png b/06_IO_Devices/03_SPI/SPI.png new file mode 100644 index 0000000..edf3a7b Binary files /dev/null and b/06_IO_Devices/03_SPI/SPI.png differ diff --git a/06_IO_Devices/03_SPI/SPI_tb.gtkw b/06_IO_Devices/03_SPI/SPI_tb.gtkw new file mode 100644 index 0000000..2607257 --- /dev/null +++ b/06_IO_Devices/03_SPI/SPI_tb.gtkw @@ -0,0 +1,48 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Fri Dec 30 13:39:55 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/03_SPI/SPI_tb.vcd" +[dumpfile_mtime] "Fri Dec 30 13:39:20 2022" +[dumpfile_size] 238580 +[savefile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/03_SPI/SPI_tb.gtkw" +[timestart] 0 +[size] 1606 597 +[pos] 88 59 +*-19.000000 107000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 132 +@28 +SPI_tb.clk +@200 +-IN +@28 +SPI_tb.load +@22 +SPI_tb.in[15:0] +@28 +SPI_tb.SDI +@200 +-OUT +@28 +SPI_tb.CSX +SPI_tb.SDO +SPI_tb.SCK +@22 +SPI_tb.out[15:0] +@200 +-CMP +@28 +SPI_tb.CSX_cmp +SPI_tb.SDO_cmp +SPI_tb.SCK_cmp +@22 +SPI_tb.out_cmp[15:0] +@200 +-Test +@29 +SPI_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/06_IO_Devices/03_SPI/SPI_tb.v b/06_IO_Devices/03_SPI/SPI_tb.v new file mode 100644 index 0000000..86bc884 --- /dev/null +++ b/06_IO_Devices/03_SPI/SPI_tb.v @@ -0,0 +1,81 @@ +`timescale 10ns/1ns +`default_nettype none + +module SPI_tb(); + + // IN,OUT + reg clk = 0; + reg load = 0; + reg [15:0] in = 0; + wire [15:0] out; + wire CSX; + wire SDO; + reg SDI=0; + wire SCK; + + // Part + SPI SPI( + .clk(clk), + .load(load), + .in(in), + .out(out), + .CSX(CSX), + .SDO(SDO), + .SDI(SDI), + .SCK(SCK) + ); + + // Simulate + always #2 clk=~clk; + wire trigger; + assign trigger = (n==20) || (n==40) || (n==60) || (n==80) || (n==100); + always @(posedge clk) begin + in <= $random; + load <= trigger; + SDI <= $random; + end + + // Compare + reg[4:0] bits=0; + always @(posedge clk) + bits <= (load&~in[8])?1:((bits==16)?0:(busy?bits+1:0)); + wire busy=|bits; + wire [15:0] out_cmp = {busy,7'd0,shift}; + reg [7:0] shift=0; + reg miso_s; + always @(posedge clk) + miso_s <= SDI; + always @(posedge clk) + shift <= load?in[7:0]:(~SCK_cmp?shift:{shift[6:0],miso_s}); + wire SCK_cmp=busy&~bits[0]; + reg CSX_cmp=1; + always @(posedge clk) + CSX_cmp<=load?in[8]:CSX_cmp; + wire SDO_cmp=shift[7]; + reg fail = 0; + reg [31:0] n = 0; + task check; + #4 + if ((out!=out_cmp)||(SCK!=SCK_cmp)||(SDO!=SDO_cmp)||(CSX!=CSX_cmp)) + begin + $display("FAIL: clk=%1b, load=%1b, in=%16b, out=%16b, CSX=%1b, SDO=%1b, SDI=%1b, SCK=%1b",clk,load,in,out,CSX,SDO,SDI,SCK); + fail=1; + end + endtask + + initial begin + $dumpfile("SPI_tb.vcd"); + $dumpvars(0, SPI_tb); + + $display("------------------------"); + $display("Testbench: SPI"); + + for (n=0; n<400;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/06_IO_Devices/03_SPI/apio.ini b/06_IO_Devices/03_SPI/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/06_IO_Devices/03_SPI/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/06_IO_Devices/03_SPI/cat.asm b/06_IO_Devices/03_SPI/cat.asm new file mode 100644 index 0000000..eb8747a --- /dev/null +++ b/06_IO_Devices/03_SPI/cat.asm @@ -0,0 +1,6 @@ +// cat.asm +// +// load spi flash rom starting at address 0x040000 and write the +// data to UART_TX +// +// Put your code here: diff --git a/06_IO_Devices/03_SPI/echo.png b/06_IO_Devices/03_SPI/echo.png new file mode 100644 index 0000000..525f1f9 Binary files /dev/null and b/06_IO_Devices/03_SPI/echo.png differ diff --git a/06_IO_Devices/03_SPI/spi-timing.png b/06_IO_Devices/03_SPI/spi-timing.png new file mode 100644 index 0000000..083882a Binary files /dev/null and b/06_IO_Devices/03_SPI/spi-timing.png differ diff --git a/06_IO_Devices/03_SPI/spi_read040000.png b/06_IO_Devices/03_SPI/spi_read040000.png new file mode 100644 index 0000000..d600006 Binary files /dev/null and b/06_IO_Devices/03_SPI/spi_read040000.png differ diff --git a/06_IO_Devices/03_SPI/spi_tb.png b/06_IO_Devices/03_SPI/spi_tb.png new file mode 100644 index 0000000..6e9b9a5 Binary files /dev/null and b/06_IO_Devices/03_SPI/spi_tb.png differ diff --git a/06_IO_Devices/03_SPI/spi_wakeup.png b/06_IO_Devices/03_SPI/spi_wakeup.png new file mode 100644 index 0000000..b4d0ec1 Binary files /dev/null and b/06_IO_Devices/03_SPI/spi_wakeup.png differ diff --git a/06_IO_Devices/04_SRAM/Include.v b/06_IO_Devices/04_SRAM/Include.v new file mode 100644 index 0000000..8efe6d3 --- /dev/null +++ b/06_IO_Devices/04_SRAM/Include.v @@ -0,0 +1,40 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift9R.v" +`include "../../03_Sequential_Logic/BitShift8L.v" + +`include "../../06_IO_Devices/UartTX.v" +`include "../../06_IO_Devices/UartRX.v" +`include "../../06_IO_Devices/SPI.v" +`include "../../06_IO_Devices/InOut.v" +`include "../../06_IO_Devices/SRAM_D.v" +`include "../../06_IO_Devices/GO.v" +`include "../../06_IO_Devices/LCD.v" +`include "../../06_IO_Devices/RTP.v" diff --git a/06_IO_Devices/04_SRAM/Makefile b/06_IO_Devices/04_SRAM/Makefile new file mode 100644 index 0000000..a75d001 --- /dev/null +++ b/06_IO_Devices/04_SRAM/Makefile @@ -0,0 +1,12 @@ +NAME = buffer + +all: asm install + +asm: + ../../tools/Assembler/assembler.pyc $(NAME).asm +install: + cp $(NAME).hack ../00_HACK/ROM.hack +clean: + rm -f *.hack *~ + +.PHONY: all clean diff --git a/06_IO_Devices/04_SRAM/Readme.md b/06_IO_Devices/04_SRAM/Readme.md new file mode 100644 index 0000000..1d8e9d2 --- /dev/null +++ b/06_IO_Devices/04_SRAM/Readme.md @@ -0,0 +1,168 @@ +## 04 SRAM + +The evaluation board iCE40HX1K-EVB includes an 512kbyte static ram chip K6R4016V1D. The SRAM chip connects to iCE40HX1K with 37 wires; + +- SRAM_ADDR 18 bit +- SRAM_DATA 16 bit (bidiretional inout) +- SRAM_CSX (chip select not) +- SRAM_OEX (output enable not) +- SRAM_WEX (write enable not) + +To read and write to the SRAM chip we will add two special function register to HACK: + +1. SRAM_A is a 16 bit register mapped at memory location 4104. SRAM_ADDR controls the 16 lower bits of the 18 bit address bus. The two most significant bits are allways 0, so we can only access 64k x 16 bit words of SRAM chip. + +2. SRAM_D is a special function register mapped at memory location 4105. SRAM_D controls the bidirectional data bus and the control wires CSX, OEX and WEX. + +**Note:** the 16 bit data bus is bidirectional and has therefore to be connected over a tristate buffer. This is done with `InOut.v` which is considered primitive and must not be implemented. + +### Chip specification SRAM_A + +SRAM_A is a simple `Register` that stores the lower 16 bit of the 18 bit address of the SRAM chip. + +### Chip specification SRAM_D + +| IN/OUT | wire | function | +| ------ | --------------- | -------------------------- | +| IN | clk | system clock (25MHz) | +| IN | load | initiate a write operation | +| IN | in[15:0] | data to write to SRAM | +| OUT | out[15:0] | data read from SRAM | +| INOUT | SRAM_DATA[15:0] | bidirectional data bus | +| OUT | SRAM_CSX | chip select not | +| OUT | SRAM_OEX | output enable not | +| OUT | SRAM_WEX | write enable not | + +When load[t]=1 transmission of word in[15:0] is initiated. The word is send to SRAM over the bidirectional wires SRAM_DATA (direction out) and a write pulse will be triggered for one cycle at t+1: + +* SRAM_OEX=1 + +* SRAM_WEX=0 + +When load=0 SRAM_DATA will be used as input and the data of the SRAM chip will be presented at out[15:0] + +- SRAM_OEX=0 + +- SRAM_WEX=1 + +SRAM_CSX can be set to low all the time. + +### Proposed Implementation ADDR_A + +Use a `Register` to store the lower 16 bit of SRAM_ADDR (The two most significant bits are hardwired to 0). + +### Proposed Implementation ADDR_D + +Use a `DFF` to delay the load signal. Use a `Register` to store the data in[15:0] to be stored. Use a tristate buffer `InOut.v` to control the direction of the bidirectional SRAM_DATA data bus. + +### Memory map + +The special function register `SRAM_A` and `SRAM_D` are mapped to memory map of HACK according to: + +| address | I/O device | R/W | function | +| ------- | ---------- | --- | ------------------------------ | +| 4101 | SRAM_A | R | address of SRAM | +| 4102 | SRAM_D | R | read data from SRAM | +| 4102 | SRAM_D | W | initiate a write cylce to SRAM | + +### buffer.asm + +To test HACK with SRAM we need a little machine language programm `buffer.asm`, which reads the first four bytes of an ASCII file previosuly stored to the SPI flash memory chip W25Q16BV of iCE40HX1K-EVB, starting at address 0x040000 (256k) and stores the four bytes to SRAM. Finally we read the four bytes from SRAM and write them to UART. + +### SRAM in real hardware + +The board iCE40HX1K-EVB comes with a static ram chip K6R4016V1D. The chip is already connected to iCE40HX1K according `iCE40HX1K-EVB.pcf` (Compare with schematic [iCE40HX1K_EVB](../../doc/iCE40HX1K-EVB_Rev_B.pdf). + +``` +set_io SRAM_ADDR[0] 79 # SA0 +set_io SRAM_ADDR[1] 80 # SA1 +set_io SRAM_ADDR[2] 81 # SA2 +set_io SRAM_ADDR[3] 82 # SA3 +set_io SRAM_ADDR[4] 83 # SA4 +set_io SRAM_ADDR[5] 85 # SA5 +set_io SRAM_ADDR[6] 86 # SA6 +set_io SRAM_ADDR[7] 87 # SA7 +set_io SRAM_ADDR[8] 89 # SA8 +set_io SRAM_ADDR[9] 90 # SA9 +set_io SRAM_ADDR[10] 91 # SA10 +set_io SRAM_ADDR[11] 93 # SA11 +set_io SRAM_ADDR[12] 94 # SA12 +set_io SRAM_ADDR[13] 95 # SA13 +set_io SRAM_ADDR[14] 96 # SA14 +set_io SRAM_ADDR[15] 97 # SA15 +set_io SRAM_ADDR[16] 99 # SA16 +set_io SRAM_ADDR[17] 100 # SA17 +set_io SRAM_CSX 78 # SRAM_#CS +set_io SRAM_OEX 74 # SRAM_#OE +set_io SRAM_WEX 73 # SRAM_#WE +set_io SRAM_DATA[0] 62 # SD0 +set_io SRAM_DATA[1] 63 # SD1 +set_io SRAM_DATA[2] 64 # SD2 +set_io SRAM_DATA[3] 65 # SD3 +set_io SRAM_DATA[4] 66 # SD4 +set_io SRAM_DATA[5] 68 # SD5 +set_io SRAM_DATA[6] 69 # SD6 +set_io SRAM_DATA[7] 71 # SD7 +set_io SRAM_DATA[8] 72 # SD8 +set_io SRAM_DATA[9] 60 # SD9 +set_io SRAM_DATA[10] 59 # SD10 +set_io SRAM_DATA[11] 57 # SD11 +set_io SRAM_DATA[12] 56 # SD12 +set_io SRAM_DATA[13] 54 # SD13 +set_io SRAM_DATA[14] 53 # SD14 +set_io SRAM_DATA[15] 52 # SD15 +``` + +*** + +### Project + +* Implement `SRAM_D.v` and simulate with testbench: + + ``` + $ cd 04_SRAM_D + $ apio clean + $ apio sim + ``` + +* Compare output of your chip `OUT` with `CMP`. + + ![](sram_tb.png) + +* Edit `HACK.v` and add a `Register` for SRAM_A memory mapped to 4101. + +* Edit `HACK.v` and add a special function register `SRAM_D` to memory address 4102. + +* Implement `buffer.asm` and test with the testbench: + + ``` + $ cd 04_SRAM_D + $ make + $ cd ../00_HACK + $ apio clean + $ apio sim + ``` + +* Check the SRAM wires of the simulation and look for the storing of "SPI!" (which was preloaded in SPI chip at memory address 0x040000 of the testbench). + + ![](buffer1.png) + +* Check the output at UART_TX in the long run. You should see the string "SPI!" output to UART_TX: + + ![](buffer.png) + +* preload the SPI memory chip with some text file at address 0x040000. + +* build and upload HACK with `buffer.asm` in ROM.BIN to iCE40HX1K-EVB. +- press reset button on iCE40HX1K-EVB and see if wou can receive the preloaded text file on your Computer. + + ``` + $ echo SPI! > spi.txt + $ iceprogduino -o 256k -w spi.txt + $ cd 04_SRAM_D + $ make + $ cd ../00_HACK + $ apio clean + $ apio upload + $ tio /dev/ttyACM0 + ``` diff --git a/06_IO_Devices/04_SRAM/SRAM_D_tb.gtkw b/06_IO_Devices/04_SRAM/SRAM_D_tb.gtkw new file mode 100644 index 0000000..55b9473 --- /dev/null +++ b/06_IO_Devices/04_SRAM/SRAM_D_tb.gtkw @@ -0,0 +1,44 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Wed Dec 28 09:52:04 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/04_SRAM/SRAM_D_tb.vcd" +[dumpfile_mtime] "Wed Dec 28 09:50:13 2022" +[dumpfile_size] 42940 +[savefile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/04_SRAM/SRAM_D_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -51 -51 +*-18.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 259 +@200 +-IN +@28 +SRAM_D_tb.load +@22 +SRAM_D_tb.in[15:0] +@200 +-OUT +@28 +SRAM_D_tb.CSX +SRAM_D_tb.OEX +SRAM_D_tb.WEX +@22 +SRAM_D_tb.out[15:0] +@200 +-CMP +@28 +SRAM_D_tb.CSX_cmp +SRAM_D_tb.OEX_cmp +SRAM_D_tb.WEX_cmp +@22 +SRAM_D_tb.out_cmp[15:0] +@200 +-Test +@29 +SRAM_D_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/06_IO_Devices/04_SRAM/SRAM_D_tb.v b/06_IO_Devices/04_SRAM/SRAM_D_tb.v new file mode 100644 index 0000000..c1b90c1 --- /dev/null +++ b/06_IO_Devices/04_SRAM/SRAM_D_tb.v @@ -0,0 +1,72 @@ +`timescale 10ns/1ns +`default_nettype none + +module SRAM_D_tb(); + + // IN,OUT + reg clk = 0; + reg load = 0; + reg [15:0] in=0; + wire [15:0] out; + wire CSX; + wire OEX; + wire WEX; + wire [15:0] DATA; + + // Part + SRAM_D SRAM_D( + .clk(clk), + .load(load), + .in(in), + .out(out), + .CSX(CSX), + .OEX(OEX), + .WEX(WEX), + .DATA(DATA) + ); + + // Simulate + always #2 clk=~clk; + wire trigger; + reg write; + assign trigger = (n==4) || (n==8) || (n==12) || (n==16) || (n==20); + always @(posedge clk) begin + in <= $random; + load <= trigger; + write <= load; + end + reg [15:0] data; + always @(posedge clk) + if (load) data <= in; + // Compare + wire CSX_cmp = 0; + wire OEX_cmp = write; + wire WEX_cmp = ~write; + wire [15:0] out_cmp = (~CSX_cmp&~OEX_cmp)?16'bzzzzzzzzzzzzzzzz:data; + reg fail = 0; + reg [31:0] n = 0; + task check; + #4 + if ((out!=out_cmp)||(CSX!=CSX_cmp)||(OEX!=OEX_cmp)||(WEX!=WEX_cmp)) + begin + $display("FAIL: clk=%1b, load=%1b, in=%16b, out=%16b, CSX=%1b, OEX=%1b, SEX=%1b, DATA=%16b",clk,load,in,out,CSX,OEX,WEX,DATA); + fail=1; + end + endtask + + initial begin + $dumpfile("SRAM_D_tb.vcd"); + $dumpvars(0, SRAM_D_tb); + + $display("------------------------"); + $display("Testbench: SRAM_D"); + + for (n=0; n<24;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/06_IO_Devices/04_SRAM/apio.ini b/06_IO_Devices/04_SRAM/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/06_IO_Devices/04_SRAM/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/06_IO_Devices/04_SRAM/buffer.asm b/06_IO_Devices/04_SRAM/buffer.asm new file mode 100644 index 0000000..5fbdf07 --- /dev/null +++ b/06_IO_Devices/04_SRAM/buffer.asm @@ -0,0 +1,7 @@ +// buffer.asm +// +// read 4 bytes of textfile from SPI starting at address 0x040000 and write +// the string to SRAM. Finally read the string from SRAM and send +// the string to UART_TX +// +// Put your code here: diff --git a/06_IO_Devices/04_SRAM/buffer.png b/06_IO_Devices/04_SRAM/buffer.png new file mode 100644 index 0000000..7f2502a Binary files /dev/null and b/06_IO_Devices/04_SRAM/buffer.png differ diff --git a/06_IO_Devices/04_SRAM/buffer1.png b/06_IO_Devices/04_SRAM/buffer1.png new file mode 100644 index 0000000..697fd51 Binary files /dev/null and b/06_IO_Devices/04_SRAM/buffer1.png differ diff --git a/06_IO_Devices/04_SRAM/sram_tb.png b/06_IO_Devices/04_SRAM/sram_tb.png new file mode 100644 index 0000000..444f5e1 Binary files /dev/null and b/06_IO_Devices/04_SRAM/sram_tb.png differ diff --git a/06_IO_Devices/05_GO/GO_tb.gtkw b/06_IO_Devices/05_GO/GO_tb.gtkw new file mode 100644 index 0000000..d1b3e12 --- /dev/null +++ b/06_IO_Devices/05_GO/GO_tb.gtkw @@ -0,0 +1,42 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu Dec 29 18:09:36 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/05_GO/GO_tb.vcd" +[dumpfile_mtime] "Thu Dec 29 18:09:26 2022" +[dumpfile_size] 80439 +[savefile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/05_GO/GO_tb.gtkw" +[timestart] 0 +[size] 1440 713 +[pos] 34 87 +*-17.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 281 +[signals_width] 240 +[sst_expanded] 1 +[sst_vpaned_height] 172 +@200 +-IN +@28 +GO_tb.clk +GO_tb.load +@22 +GO_tb.pc[15:0] +GO_tb.sram_addr[15:0] +GO_tb.ROM_data[15:0] +GO_tb.sram_data[15:0] +@200 +-OUT +@22 +GO_tb.SRAM_ADDR[15:0] +GO_tb.instruction[15:0] +@200 +-CMP +@22 +GO_tb.SRAM_ADDR_cmp[15:0] +GO_tb.instruction_cmp[15:0] +@200 +-Test +@28 +GO_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/06_IO_Devices/05_GO/GO_tb.v b/06_IO_Devices/05_GO/GO_tb.v new file mode 100644 index 0000000..a78e1f0 --- /dev/null +++ b/06_IO_Devices/05_GO/GO_tb.v @@ -0,0 +1,73 @@ +`timescale 10ns/1ns +`default_nettype none + +module GO_tb(); + + // IN,OUT + reg clk = 0; + reg load = 0; + reg [15:0] sram_addr=0; + reg [15:0] pc=0; + wire [15:0] SRAM_ADDR; + reg [15:0] ROM_data=0; + reg [15:0] sram_data=0; + wire [15:0] instruction; + + // Part + GO GO( + .clk(clk), + .load(load), + .sram_addr(sram_addr), + .pc(pc), + .SRAM_ADDR(SRAM_ADDR), + .ROM_data(ROM_data), + .sram_data(sram_data), + .instruction(instruction) + ); + + // Simulate + always #2 clk=~clk; + wire trigger; + reg write; + assign trigger = (n==10); + always @(posedge clk) begin + sram_addr <= $random; + pc <= $random; + ROM_data <= $random; + sram_data <= $random; + load <= trigger; + end + + // Compare + reg fail = 0; + reg [31:0] n = 0; + reg run=0; + always @(posedge clk) + if (load) run <=1; + wire [15:0] SRAM_ADDR_cmp=run?pc:sram_addr; + wire [15:0] instruction_cmp=run?sram_data:ROM_data; + task check; + #4 + if ((SRAM_ADDR!=SRAM_ADDR_cmp) || (instruction!=instruction_cmp)) + begin + $display("FAIL: clk=%1b, load=%1b",clk,load); + fail=1; + end + endtask + + initial begin + $dumpfile("GO_tb.vcd"); + $dumpvars(0, GO_tb); + + $display("------------------------"); + $display("Testbench: GO"); + + for (n=0; n<20;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/06_IO_Devices/05_GO/Include.v b/06_IO_Devices/05_GO/Include.v new file mode 100644 index 0000000..8efe6d3 --- /dev/null +++ b/06_IO_Devices/05_GO/Include.v @@ -0,0 +1,40 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift9R.v" +`include "../../03_Sequential_Logic/BitShift8L.v" + +`include "../../06_IO_Devices/UartTX.v" +`include "../../06_IO_Devices/UartRX.v" +`include "../../06_IO_Devices/SPI.v" +`include "../../06_IO_Devices/InOut.v" +`include "../../06_IO_Devices/SRAM_D.v" +`include "../../06_IO_Devices/GO.v" +`include "../../06_IO_Devices/LCD.v" +`include "../../06_IO_Devices/RTP.v" diff --git a/06_IO_Devices/05_GO/Makefile b/06_IO_Devices/05_GO/Makefile new file mode 100644 index 0000000..465dad0 --- /dev/null +++ b/06_IO_Devices/05_GO/Makefile @@ -0,0 +1,12 @@ +NAME = boot + +all: asm install + +asm: + ../../tools/Assembler/assembler.pyc $(NAME).asm +install: + cp $(NAME).hack ../00_HACK/ROM.hack +clean: + rm -f *.hack *~ + +.PHONY: all clean diff --git a/06_IO_Devices/05_GO/Readme.md b/06_IO_Devices/05_GO/Readme.md new file mode 100644 index 0000000..047367f --- /dev/null +++ b/06_IO_Devices/05_GO/Readme.md @@ -0,0 +1,82 @@ +## 05 GO + +The instrucition memory ROM of HACK is limited to 256 words. In order to run bigger programs written in JACK (e.g. tetris) we will store the program to SRAM and use the SRAM memory chip as instruction memory. For this we need: + +1. A bootloader program written in assembler (which is stored in the 256 words of ROM), that reads a (bigger) hack binary program previously stored on SPI memory chip starting at address 0x010000 and stores it to SRAM. + +2. A multiplexer, that switches instruction memory from ROM to SRAM. + +### Chip specification + +When load=1 `GO` switches HACK operation from boot mode to run mode. In boot mode instruction=ROM_data and SRAM_ADDR=sram_a. In run mode instruction=sram_data and SRAM_ADDR=pc. + +### Memory map + +The special function register `GO` is memory mapped to address 4103 + +| addr | R/W | function | +| ---- | --- | ----------------------------------------------------------------------------------------------------------- | +| 4103 | W | a write resets the HACK CPU and switches instrucion memory from ROM (bootloader) to SRAM (JACK application) | + +### boot.asm + +bootloader that reads 64k words from SPI flash memory starting from address 0x010000 and writes them to SRAM. FInally it resets the CPU and starts program execution from SRAM. + +To run the testbench it's sufficient to read only the first 6 words. The SPI in the testbench is preloaded with the following 6 assembler instructions of the program `leds.asm` translated into HACK machine language: + +``` +@BUT +D=M +@LED +M=D +@0 +0;JMP +``` + +*** + +### Project + +* Implement `boot.asm` (read only the first 6 words) and run the testbench: + + ``` + $ cd 05_GO + $ make + $ cd ../00_HACK + $ apio + $ apio sim + ``` + + ![](go.png) + + + +* Check, if HACK reads 6 instrucions from SPI and writes them to SRAM. + +* Check, if HACK can switch from instruction memory ROM (bootloader= to instruction memory SRAM (application) when loadGO=1. + +* Check, if HACK runs `leds.asm` after switching from boot to run. + +### Run in real hardware + +* preload SPI flash rom with the hack programm `leds.asm.` + + ``` + $ cd ../../04_Machine_Language + $ make leds + $ make upload + ``` + +* upload HACK with bootloader to iCE40HX1K-EVB + + ``` + $ cd 05_GO + $ make + $ cd ../00HACK + $ apio clean + $ apio upload + ``` + +* Check if iCE40HX1K-EVB runs the bootloader, which loads `leds.asm` from SPI and starts execution of leds.asm. + +If `leds.asm` is working, you are ready to start implementing the operating system JACK-OS. Proceed to project `07_Operating_System` and come back later to implement the last to IO-Devices `LCD` and `RTP` to connect the screen with resitive touch panel MOD-LCD2.8RTP. \ No newline at end of file diff --git a/06_IO_Devices/05_GO/apio.ini b/06_IO_Devices/05_GO/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/06_IO_Devices/05_GO/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/06_IO_Devices/05_GO/boot.asm b/06_IO_Devices/05_GO/boot.asm new file mode 100644 index 0000000..5fc5705 --- /dev/null +++ b/06_IO_Devices/05_GO/boot.asm @@ -0,0 +1,5 @@ +//***************************************************************************** +// Boot loader. Load HACK code from SPI address 0x010000 (64k) into SRAM and GO +//***************************************************************************** +// +// Put your code here: diff --git a/06_IO_Devices/05_GO/go.png b/06_IO_Devices/05_GO/go.png new file mode 100644 index 0000000..5cdbf52 Binary files /dev/null and b/06_IO_Devices/05_GO/go.png differ diff --git a/06_IO_Devices/06_LCD/Include.v b/06_IO_Devices/06_LCD/Include.v new file mode 100644 index 0000000..8efe6d3 --- /dev/null +++ b/06_IO_Devices/06_LCD/Include.v @@ -0,0 +1,40 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift9R.v" +`include "../../03_Sequential_Logic/BitShift8L.v" + +`include "../../06_IO_Devices/UartTX.v" +`include "../../06_IO_Devices/UartRX.v" +`include "../../06_IO_Devices/SPI.v" +`include "../../06_IO_Devices/InOut.v" +`include "../../06_IO_Devices/SRAM_D.v" +`include "../../06_IO_Devices/GO.v" +`include "../../06_IO_Devices/LCD.v" +`include "../../06_IO_Devices/RTP.v" diff --git a/06_IO_Devices/06_LCD/LCD.dia b/06_IO_Devices/06_LCD/LCD.dia new file mode 100644 index 0000000..806e11b Binary files /dev/null and b/06_IO_Devices/06_LCD/LCD.dia differ diff --git a/06_IO_Devices/06_LCD/LCD.png b/06_IO_Devices/06_LCD/LCD.png new file mode 100644 index 0000000..8ca892c Binary files /dev/null and b/06_IO_Devices/06_LCD/LCD.png differ diff --git a/06_IO_Devices/06_LCD/LCD_tb.gtkw b/06_IO_Devices/06_LCD/LCD_tb.gtkw new file mode 100644 index 0000000..7b849be --- /dev/null +++ b/06_IO_Devices/06_LCD/LCD_tb.gtkw @@ -0,0 +1,50 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Fri Dec 30 13:59:38 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/06_LCD/LCD_tb.vcd" +[dumpfile_mtime] "Fri Dec 30 13:59:22 2022" +[dumpfile_size] 258098 +[savefile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/06_LCD/LCD_tb.gtkw" +[timestart] 0 +[size] 1634 636 +[pos] -1 -1 +*-19.886099 213000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] LCD_tb. +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 137 +@28 +LCD_tb.clk +@200 +-INPUT +@28 +LCD_tb.load +LCD_tb.load16 +@22 +LCD_tb.in[15:0] +@200 +-OUTPUT +@28 +LCD_tb.CSX +LCD_tb.DCX +LCD_tb.SDO +LCD_tb.SCK +(0)LCD_tb.out[15:0] +@200 +-CMP +@28 +LCD_tb.CSX_cmp +LCD_tb.DCX_cmp +LCD_tb.SDO_cmp +@29 +LCD_tb.SCK_cmp +@28 +LCD_tb.out_cmp +@200 +-Test +@28 +LCD_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/06_IO_Devices/06_LCD/LCD_tb.png b/06_IO_Devices/06_LCD/LCD_tb.png new file mode 100644 index 0000000..299eb84 Binary files /dev/null and b/06_IO_Devices/06_LCD/LCD_tb.png differ diff --git a/06_IO_Devices/06_LCD/LCD_tb.v b/06_IO_Devices/06_LCD/LCD_tb.v new file mode 100644 index 0000000..4226dd9 --- /dev/null +++ b/06_IO_Devices/06_LCD/LCD_tb.v @@ -0,0 +1,89 @@ +`timescale 10ns/1ns +`default_nettype none + +module LCD_tb(); + + // IN,OUT + reg clk = 0; + reg load = 0; + reg load16 = 0; + reg [15:0] in = 0; + wire [15:0] out; + wire DCX; + wire CSX; + wire SDO; + wire SCK; + + // Part + LCD LCD( + .clk(clk), + .load(load), + .load16(load16), + .in(in), + .out(out), + .DCX(DCX), //SPI-line data/command not + .CSX(CSX), //SPI-line chip enabled not + .SDO(SDO), //SPI-Line master out slave in + .SCK(SCK) //SPI-clock + ); + + // Simulate + always #2 clk=~clk; + wire trigger; + assign trigger = (n==20) || (n==40) || (n==60) || (n==80) || (n==100); + reg [1:0] xx=0; + always @(posedge clk) begin + in <= trigger?$random&16'h02ff:in; + if (trigger) xx<=xx+1; + load <= trigger&&(~xx[1]); + load16 <= trigger&&(xx==2); + end + + // Compare + reg[5:0] bits=0; + reg d16=0; + always @(posedge clk) + d16 <= load16?1:(load)?0:d16; + always @(posedge clk) + bits <= (load&~in[8]|load16)?1:(((bits[4]&~d16)|bits[5])?0:(busy?bits+1:0)); + wire busy=|bits; + wire out_cmp = busy; + reg [15:0] shift=0; + always @(posedge clk) + shift <= (load|load16)?in:(~SCK_cmp?shift:{shift[14:0],1'b0}); + wire SCK_cmp=busy&~bits[0]; + reg ce_cmp=0; + always @(posedge clk) + ce_cmp<=(load|load16)?(load16|load&~in[8]):ce_cmp; + wire CSX_cmp=~ce_cmp; + reg DCX_cmp=0; + always @(posedge clk) + DCX_cmp<=load?in[9]:(load16)?1:DCX_cmp; + wire SDO_cmp=(d16&shift[15])|(~d16&shift[7]); + reg fail = 0; + reg [31:0] n = 0; + task check; + #4 + if ((out[15]!=out_cmp)||(SDO!=SDO_cmp)||(CSX!=CSX_cmp)||(SCK!=SCK_cmp)||(DCX!=DCX_cmp)) + begin + $display("FAIL: clk=%1b, load=%1b, in=%16b, out=%16b, DCX=%1b, CSX=%1b, SDO=%1b, SCK=%1b",clk,load,in,out,DCX,CSX,SDO,SCK); + fail=1; + end + endtask + + initial begin + $dumpfile("LCD_tb.vcd"); + $dumpvars(0, LCD_tb); + + $display("------------------------"); + $display("Testbench: LCD"); + + for (n=0; n<400;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/06_IO_Devices/06_LCD/Readme.md b/06_IO_Devices/06_LCD/Readme.md new file mode 100644 index 0000000..19718dc --- /dev/null +++ b/06_IO_Devices/06_LCD/Readme.md @@ -0,0 +1,91 @@ +## 06 LCD + +The special function register `LCD` memory mapped to addresses 4104 and 4105 enables HACK to write bytes to the LCD controller chip ILI9341V situated on MOD-LCD2.8RTP. The communication protocol is SPI with one additional wire DCX. The protocol defines transmission of 8 bit commands with DCX = 0 followed data with DCX=1. Data packets can have any length depending on the launched command. + +### Chip specification + +| IN/OUT | wire | function | +| ------ | ------- | -------------------------------------------------- | +| IN | in[7:0] | byte to be sent. | +| IN | in[8] | =0 send byte and set CSX low | +| IN | in[8] | =1 pull CSX high without sending byte | +| IN | in[9] | value of DCX when transmitting a byte. | +| IN | load | initiates the transmission of a byte, when in[8]=0 | +| IN | load16 | initiates the transmission of 16 bit in[15:0] | +| OUT | out[15] | =0 chip is busy, =0 ready | +| OUT | DCX | =0 command, =1 data | +| OUT | SDO | serial data out | +| OUT | SCK | serial clock | +| OUT | CSX | chip select not | + +The special function register `LCD` communicates with ILI9341V LCD controller over 4 wire SPI. + +When load=1 and in[8]=0 transmission of byte in[7:0] is initiated. CSX is goes low (and stays low even when transmission is completed). DCX is set to in[9]. The byte in[7:0] is send to SDO bitwise together with 8 clock signals on SCK. During transmission out[15] is 1. After 16 clock cycles transmission is completed and out[15] is set to 0. + +When load=1 and in[8]=1 CSX goes high and DCX=in[9] without transmission of any bit. + +When load16=1 transmission of word in[15:0] is initiated. CSX is goes low (and stays low even when transmission is completed). DCX is set to 1 (data). After 32 clock cycles transmission is completed and out[15] is set to 0. + +### Proposed Implementation + +Use a `Bit` to store the state (0 = ready, 1 = busy) which is output to out[15]. Another two `Bit` store the state of DCX and CSX. Use a counter `PC` to count from 0 to 15 or 31 according to load/load16. Finally we need two connected `BitShift8L`. They will be loaded with the byte in[7:0] or the word in[15:0] to be send. After 8/16 bits are transmitted the module cleares out[15]. + +![](LCD.png) + +### Memory map + +The special function register `LCD` is mapped to memory map of HACK according to: + +| address | I/O device | R/W | function | +| --------- | ---------- | --- | ----------------------------------- | +| 4104 | LCD | W | start transmittion of byte in[7:0] | +| 4105 | LCD | W | start transmittion of word in[15:0] | +| 4104/4105 | LCD | R | out[15]=1 busy, out[15]=0 idle | + +### LCD in real hardware + +The board MO-LCD2.8RTP comes with a 2.8 inch LCD screen controlled by a controller chip ILI8341V. MOD-LCD2.8RTP must be connected to iCE40HX1K-EVB with 6 jumper wire cables: +3.3V, GND plus 4 data wires according to `iCE40HX1K-EVB.pcf` (Compare with schematic [iCE40HX1K_EVB](../../doc/iCE40HX1K-EVB_Rev_B.pdf) and [MOD-LCD2.8RTP_RevB.pdf](../../doc/MOD-LCD2.8RTP_RevB.pdf). + +``` +set_io LCD_DCX 1 # PIO3_1A connected to pin 5 of GPIO1 +set_io LCD_SDO 2 # PIO3_1B connected to pin 7 of GPIO1 +set_io LCD_SCK 3 # PIO3_2A connected to pin 9 of GPIO1 +set_io LCD_CSX 4 # PIO3_2B connected to pin 11 of GPIO1 +``` + +| wire | iCE40HX1K-EVB (GPIO1) | MOD-LCD2.8RTP (UEXT) | +| ------- | --------------------- | -------------------- | +| +3.3V | 3 | 1 +3.3V | +| GND | 4 | 2 GND | +| LCD_DCX | 5 | 7 D/C | +| LCD_SDO | 7 | 8 MOSI | +| LCD_SCK | 9 | 9 SCK | +| LCD_CSX | 11 | 11 CS | + +*** + +### Project + +* Implement `LCD.v` and test with testbench: + + ``` + $ cd 06_LCD + $ apio clean + $ apio sim + ``` + +* Compare output `OUT` of special chip`LCD` with `CMP`. + + ![](LCD_tb.png) + +* Add special function register`LCD` to `HACK` at memory addresses 4104/4105 and upload to iCE40HX1K-EVB with the bootloader boot.asm preloaded into ROM + + ``` + $ cd ../05_GO + $ make + $ cd ../00_HACK + $ apio clean + $ apio upload + ``` + +* Proceed to `07_Operating_System` and implement the driver class `Screen.jack` that sends command over `LCD` the controller chip ILI9341V on MOD-LCD2.8RTP diff --git a/06_IO_Devices/06_LCD/apio.ini b/06_IO_Devices/06_LCD/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/06_IO_Devices/06_LCD/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/06_IO_Devices/06_LCD/lcd_tb.gtkw b/06_IO_Devices/06_LCD/lcd_tb.gtkw new file mode 100644 index 0000000..5b465ff --- /dev/null +++ b/06_IO_Devices/06_LCD/lcd_tb.gtkw @@ -0,0 +1,49 @@ +[*] +[*] GTKWave Analyzer v3.3.98 (w)1999-2019 BSI +[*] Wed Jun 17 13:06:36 2020 +[*] +[dumpfile] "/home/micha/git/gitlab/nand2tetris/12_hack-12-nand/lcd/lcd_tb.vcd" +[dumpfile_mtime] "Wed Jun 17 13:05:40 2020" +[dumpfile_size] 150367 +[savefile] "/home/micha/git/gitlab/nand2tetris/12_hack-12-nand/lcd/lcd_tb.gtkw" +[timestart] 0 +[size] 1280 703 +[pos] -1 -1 +*-6.000000 230 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] lcd_tb. +[treeopen] lcd_tb.LCD. +[treeopen] lcd_tb.LCD.ISC. +[sst_width] 238 +[signals_width] 134 +[sst_expanded] 1 +[sst_vpaned_height] 174 +@28 +lcd_tb.startD8 +lcd_tb.LCD.startD16 +@29 +lcd_tb.LCD.startC +@22 +lcd_tb.in[15:0] +lcd_tb.in[15:0] +@28 +lcd_tb.clk +@22 +lcd_tb.LCD.bitc[4:0] +@28 +lcd_tb.LCD.spi_mosi +lcd_tb.LCD.mosi +lcd_tb.LCD.spi_sck +lcd_tb.LCD.sck +lcd_tb.LCD.spi_cen +lcd_tb.LCD.idle +lcd_tb.LCD.spi_cdn +lcd_tb.LCD.dcn +lcd_tb.LCD.clk_baud +@22 +lcd_tb.LCD.data_r[17:0] +@28 +lcd_tb.LCD.load +lcd_tb.LCD.BAUDRATE.reset +lcd_tb.LCD.SWITCH_CLOCK.out +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/06_IO_Devices/07_RTP/Include.v b/06_IO_Devices/07_RTP/Include.v new file mode 100644 index 0000000..8efe6d3 --- /dev/null +++ b/06_IO_Devices/07_RTP/Include.v @@ -0,0 +1,40 @@ +`include "../../01_Boolean_Logic/Nand.v" +`include "../../01_Boolean_Logic/Not.v" +`include "../../01_Boolean_Logic/Buffer.v" +`include "../../01_Boolean_Logic/And.v" +`include "../../01_Boolean_Logic/Or.v" +`include "../../01_Boolean_Logic/Xor.v" +`include "../../01_Boolean_Logic/Mux.v" +`include "../../01_Boolean_Logic/DMux.v" +`include "../../01_Boolean_Logic/Not16.v" +`include "../../01_Boolean_Logic/Buffer16.v" +`include "../../01_Boolean_Logic/And16.v" +`include "../../01_Boolean_Logic/Or16.v" +`include "../../01_Boolean_Logic/Mux16.v" +`include "../../01_Boolean_Logic/Or8Way.v" +`include "../../01_Boolean_Logic/Mux4Way16.v" +`include "../../01_Boolean_Logic/Mux8Way16.v" +`include "../../01_Boolean_Logic/DMux4Way.v" +`include "../../01_Boolean_Logic/DMux8Way.v" + +`include "../../02_Boolean_Arithmetic/HalfAdder.v" +`include "../../02_Boolean_Arithmetic/FullAdder.v" +`include "../../02_Boolean_Arithmetic/Add16.v" +`include "../../02_Boolean_Arithmetic/Inc16.v" +`include "../../02_Boolean_Arithmetic/ALU.v" + +`include "../../03_Sequential_Logic/DFF.v" +`include "../../03_Sequential_Logic/Bit.v" +`include "../../03_Sequential_Logic/Register.v" +`include "../../03_Sequential_Logic/PC.v" +`include "../../03_Sequential_Logic/BitShift9R.v" +`include "../../03_Sequential_Logic/BitShift8L.v" + +`include "../../06_IO_Devices/UartTX.v" +`include "../../06_IO_Devices/UartRX.v" +`include "../../06_IO_Devices/SPI.v" +`include "../../06_IO_Devices/InOut.v" +`include "../../06_IO_Devices/SRAM_D.v" +`include "../../06_IO_Devices/GO.v" +`include "../../06_IO_Devices/LCD.v" +`include "../../06_IO_Devices/RTP.v" diff --git a/06_IO_Devices/07_RTP/RTP.dia b/06_IO_Devices/07_RTP/RTP.dia new file mode 100644 index 0000000..5e8256e Binary files /dev/null and b/06_IO_Devices/07_RTP/RTP.dia differ diff --git a/06_IO_Devices/07_RTP/RTP.png b/06_IO_Devices/07_RTP/RTP.png new file mode 100644 index 0000000..4ff2930 Binary files /dev/null and b/06_IO_Devices/07_RTP/RTP.png differ diff --git a/06_IO_Devices/07_RTP/RTP_tb.gtkw b/06_IO_Devices/07_RTP/RTP_tb.gtkw new file mode 100644 index 0000000..2be529d --- /dev/null +++ b/06_IO_Devices/07_RTP/RTP_tb.gtkw @@ -0,0 +1,48 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Mon Jan 2 15:25:24 2023 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/07_RTP/RTP_tb.vcd" +[dumpfile_mtime] "Mon Jan 2 15:24:52 2023" +[dumpfile_size] 898324 +[savefile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/07_RTP/RTP_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -1 -1 +*-22.000000 2190000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] RTP_tb. +[sst_width] 281 +[signals_width] 160 +[sst_expanded] 1 +[sst_vpaned_height] 259 +@28 +RTP_tb.clk +@200 +-IN +@28 +RTP_tb.load +@22 +RTP_tb.in[15:0] +@28 +RTP_tb.RTP.SDI +@200 +-OUT +@28 +RTP_tb.RTP.SDO +RTP_tb.RTP.SCK +@22 +RTP_tb.out[15:0] +@200 +-CMP +@29 +RTP_tb.SDO_cmp +@28 +RTP_tb.SCK_cmp +@22 +RTP_tb.out_cmp[15:0] +@200 +-Test +@28 +RTP_tb.fail +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/06_IO_Devices/07_RTP/RTP_tb.v b/06_IO_Devices/07_RTP/RTP_tb.v new file mode 100644 index 0000000..d82393c --- /dev/null +++ b/06_IO_Devices/07_RTP/RTP_tb.v @@ -0,0 +1,81 @@ +`timescale 10ns/1ns +`default_nettype none + +module RTP_tb(); + + // IN,OUT + reg clk = 0; + reg load = 0; + reg [15:0] in = 0; + wire [15:0] out; + wire SDO; + reg SDI=0; + wire SCK; + + // Part + RTP RTP( + .clk(clk), + .load(load), + .in(in), + .out(out), + .SDO(SDO), + .SDI(SDI), + .SCK(SCK) + ); + + // Simulate + always #2 clk=~clk; + wire trigger; + assign trigger = (n==20) || (n==420) || (n==820) || (n==1220) || (n==1620); + always @(posedge clk) begin + in <= trigger?$random&16'h03ff:in; + load <= trigger; + end + + always @(posedge SCK_cmp) + SDI <= $random; + // Compare + reg[8:0] bits=0; + always @(posedge clk) + bits <= load?1:((bits==256)?0:(busy?bits+1:0)); + wire busy=|bits[8:0]; + wire [15:0] out_cmp = {busy,7'd0,shift}; + reg [7:0] shift=0; + wire tr=~|bits[3:0]&busy; + reg lsb=0; + always @(posedge clk) + lsb<=(tr&SCK_cmp)?SDI:lsb; + always @(posedge clk) + shift <= load?in[7:0]:((tr&~SCK_cmp)?{shift[6:0],lsb}:shift); + reg SCK_cmp=0; + always @(posedge clk) + SCK_cmp <= load?1:(tr&busy&~bits[8])?~SCK_cmp:SCK_cmp; + wire SDO_cmp; + assign SDO_cmp = shift[7]; + reg fail = 0; + reg [31:0] n = 0; + task check; + #4 + if ((out!=out_cmp)||(SCK!=SCK_cmp)||(SDO!=SDO_cmp)) + begin + $display("FAIL: clk=%1b, load=%1b, in=%16b, out=%16b, SDO=%1b, SDI=%1b, SCK=%1b",clk,load,in,out,SDO,SDI,SCK); + fail=1; + end + endtask + + initial begin + $dumpfile("RTP_tb.vcd"); + $dumpvars(0, RTP_tb); + + $display("------------------------"); + $display("Testbench: RTP"); + + for (n=0; n<2000;n=n+1) + check(); + + if (fail==0) $display("passed"); + $display("------------------------"); + $finish; + end + +endmodule diff --git a/06_IO_Devices/07_RTP/Readme.md b/06_IO_Devices/07_RTP/Readme.md new file mode 100644 index 0000000..6592127 --- /dev/null +++ b/06_IO_Devices/07_RTP/Readme.md @@ -0,0 +1,96 @@ +## 07 RTP + +The special function register `RTP` memory mapped to addresses 4106 enables HACK to read bytes from the resistive touch panel controller chip AR1021 situated on MOD-LCD2.8RTP. The communication is protocol is SPI. + +**Attention:** The specification of AR1200 requires, that SCK is inverted (compare `03_SPI/Readme.md` with CPOL=1) and a slower transfer rate of max. 900kHz + +### Chip specification + +| IN/OUT | wire | function | +| ------ | -------- | ----------------------------- | +| IN | in[7:0] | byte to be sent. | +| IN | load | =1 initiates the transmission | +| OUT | out[15] | =0 chip is busy, =0 ready | +| OUT | out[7:0] | received byte | +| IN | SDI | serial data in | +| OUT | SDO | serial data out | +| OUT | SCK | serial clock | + +When load=1 transmission of byte in[7:0] is initiated. The byte is send to SDO bitwise together with 8 clock signals on SCK. At the same time `RTP` receives a byte at SDI. During transmission out[15] is 1. The transmission of a byte takes 256 clock cycles (32 cycles for each bit to achieve a slower transfer rate). Every 32 clock cycles one bit is shifted out. In the middle of each bit at counter number 31 the bit SDI is sampled. When transmission is completed out[15]=0 and `RTP` outputs the received byte to out[7:0]. + +### Proposed Implementation + +Use a `Bit` to store the state (0 = ready, 1 = busy) which is output to out[15]. Use a counter `PC` that counts from 0 to 511. Finally we need a `BitShift8L`. It will be loaded with the byte in[7:0] to be send. Use a `Bit` to sample the SDI line. After 8 bits are transmitted/received `RTP` cleares out[15] and outputs the received byte to in[7:0]. + +**Attention:** sample on rising edge of SCK and shift on falling edge of SCK. + +![](RTP.png) + +### Memory map + +The special function register `RTP` is mapped to memory map of HACK according to: + +| address | I/O device | R/W | function | +| ------- | ---------- | --- | ----------------------------------------------------------- | +| 4106 | LCD | W | start transmittion of byte in[7:0] | +| 4106 | LCD | R | out[15]=1 busy, out[15]=0 idle, out[7:0] last received byte | + +### RTP in real hardware + +The board MOD-LCD2.8RTP comes with a resistive touch panel controlled by a controller chip AR1021. MOD-LCD2.8RTP must be connected to iCE40HX1K-EVB with 3 more jumper wire cables according to `iCE40HX1K-EVB.pcf` (Compare with schematic [iCE40HX1K_EVB](../../doc/iCE40HX1K-EVB_Rev_B.pdf) and [MOD-LCD2.8RTP_RevB.pdf](../../doc/MOD-LCD2.8RTP_RevB.pdf). + +``` +set_io RTP_SDI 7 # PIO3_3A connected to pin 13 of GPIO1 +set_io RTP_SDO 8 # PIO3_3B connected to pin 15 of GPIO1 +set_io RTP_SCK 9 # PIO3_5A connected to pin 17 of GPIO1 +``` + +| wire | iCE40HX1K-EVB (GPIO1) | MOD-LCD2.8RTP (UEXT) | +| ------- | --------------------- | ---------------------------------- | +| +3.3V | 3 | +3.3V | +| GND | 4 | 2 GND | +| LCD_DCX | 5 | 7 D/C | +| LCD_SDO | 7 | 8 MOSI | +| LCD_SCK | 9 | 9 SCK | +| LCD_CSX | 11 | 10 CS | +| RTP_SDI | 13 | 4 IRQ/SDO (with solder jumper SJ3) | +| RTP_SDO | 15 | 6 SDA | +| RTP_SCK | 17 | 5 SCL | + +**Attention:** To enable SPI communication on the RTP controller chip AR1021 we must modify two solder jumpers. (Compare with schematic of MOD-LCD2.8RTP together with Datasheet of AR1021). + +1. Cut connection SJ1-GND with a sharp cutter knife. (green) + +2. Connect SJ1 to +3.3V to activate SPI mode of AR1021 (yellow) + +3. Connect SJ3 (UEXT pin4 with SDO) (yellow) + +![](jumper_rtp.jpg) + +*** + +### Project + +* Implement special function register `RTP` and test with testbench: + + ``` + $ cd 07_RTP + $ apio clean + $ apio sim + ``` + +* Compare output `OUT` of special chip`RTP` with `CMP`. + + ![](rtp_tb.png) + +* Add special function register`RTP` to `HACK` at memory addresses 4106 and upload to iCE40HX1K-EVB with bootloader boot.asm preloaded into ROM. + + ``` + $ cd ../05_GO + $ make + $ cd ../00_HACK + $ apio clean + $ apio upload + ``` + +* Proceed to `07_Operating_System` and implement the driver class `Touch.jack` that sends command over `RTP` the controller chip AR1021 on MOD-LCD2.8RTP diff --git a/06_IO_Devices/07_RTP/apio.ini b/06_IO_Devices/07_RTP/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/06_IO_Devices/07_RTP/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/06_IO_Devices/07_RTP/jumper_rtp.jpg b/06_IO_Devices/07_RTP/jumper_rtp.jpg new file mode 100644 index 0000000..25a5038 Binary files /dev/null and b/06_IO_Devices/07_RTP/jumper_rtp.jpg differ diff --git a/06_IO_Devices/07_RTP/rtp_tb.png b/06_IO_Devices/07_RTP/rtp_tb.png new file mode 100644 index 0000000..ef8c0c9 Binary files /dev/null and b/06_IO_Devices/07_RTP/rtp_tb.png differ diff --git a/06_IO_Devices/GO.v b/06_IO_Devices/GO.v new file mode 100644 index 0000000..0753329 --- /dev/null +++ b/06_IO_Devices/GO.v @@ -0,0 +1,18 @@ +/** + * GO switches from boot to run mode. + */ +`default_nettype none +module GO( + input clk, + input load, + input [15:0] pc, + input [15:0] sram_addr, + output [15:0] SRAM_ADDR, + input [15:0] sram_data, + input [15:0] ROM_data, + output [15:0] instruction +); + + // Put your code here: + +endmodule diff --git a/06_IO_Devices/HACK.v b/06_IO_Devices/HACK.v new file mode 100644 index 0000000..ca4756a --- /dev/null +++ b/06_IO_Devices/HACK.v @@ -0,0 +1,39 @@ +/** + * The HACK computer, including CPU, ROM and RAM. + * When RST is 1, the program stored in the computer's ROM executes. + * When RST is 0, the execution of the program restarts. + * Thus, to start a program's execution, reset must be pushed "down" (0) + * and "up" (1). From this point onward the user is at the mercy of + * the software. In particular, depending on the program's code, the + * LED may show some output and the user may be able to interact + * with the computer via the BUT. + */ + +`default_nettype none +module HACK( + input CLK, // external clock 100 MHz + input [1:0] BUT, // user button ("pushed down" == 0) ("up" == 1) + output [1:0] LED, // leds (0 off, 1 on) + input UART_RX, // UART recieve + output UART_TX, // UART transmit + output SPI_SDO, // SPI data out + input SPI_SDI, // SPI data in + output SPI_SCK, // SPI serial clock + output SPI_CSX, // SPI chip select not + output [17:0] SRAM_ADDR,// SRAM address 18 Bit = 256K + inout [15:0] SRAM_DATA, // SRAM data 16 Bit + output SRAM_WEX, // SRAM write_enable_not + output SRAM_OEX, // SRAM output_enable_not + output SRAM_CSX, // SRAM chip_select_not + output LCD_DCX, // LCD data/command not + output LCD_SDO, // LCD data out + output LCD_SCK, // LCD serial clock + output LCD_CSX, // LCD chip select not + input RTP_SDI, // RTP data in s + output RTP_SDO, // RTP data out + output RTP_SCK // RTP serial clock +); + + // Put your code here: + +endmodule diff --git a/06_IO_Devices/InOut.v b/06_IO_Devices/InOut.v new file mode 100644 index 0000000..d0fd103 --- /dev/null +++ b/06_IO_Devices/InOut.v @@ -0,0 +1,20 @@ +/** +* Tristate Buffer (16 bit) +* +* if (dir == 0) IN: PIN are set to High-Z, dataR = external PIN +* if (dir == 1) OUTPUT: dataW is output to external PIN, dataR = dataW +*/ +`default_nettype none + +module InOut( + inout [15:0] PIN, + input [15:0] dataW, + output [15:0] dataR, + input dir +); + // No need to implement this chip. + // This chip is implemented using tristate value z + assign PIN = dir? dataW: 16'bzzzzzzzzzzzzzzzz; + assign dataR = PIN; + +endmodule diff --git a/06_IO_Devices/LCD.v b/06_IO_Devices/LCD.v new file mode 100644 index 0000000..d0554d1 --- /dev/null +++ b/06_IO_Devices/LCD.v @@ -0,0 +1,32 @@ +/* + * LCD communicates with ILI9341V LCD controller over 4 wire SPI. + * + * When load=1 and in[8]=0 transmission of byte in[7:0] is initiated. + * CSX is goes low (and stays low even when transmission is completed). + * DCX is set to in[9]. The byte in[7:0] is send to SDO bitwise together + * with 8 clock signals on SCK. During transmission out[15] is 1. + * After 16 clock cycles transmission is completed and out[15] is set to 0. + * + * When load=1 and in[8]=1 CSX goes high and DCX=in[9] without transmission + * of any bit. + * + * When load16=1 transmission of word in[15:0] is initiated. CSX is goes low + * (and stays low even when transmission is completed). DCX is set to 1 (data). + * After 32 clock cycles transmission is completed and out[15] is set to 0. +*/ +`default_nettype none +module LCD( + input clk, //clock 25 MHz + input load, //start send command/byte over SPI + input load16, //start send data (16 bits) + input [15:0] in, //data to be send + output [15:0] out, //data to be send + output DCX, //SPI data/command not + output CSX, //SPI chip select not + output SDO, //SPI serial data out + output SCK //SPI serial clock +); + + // Put your code here: + +endmodule diff --git a/06_IO_Devices/RTP.v b/06_IO_Devices/RTP.v new file mode 100644 index 0000000..5dd52a1 --- /dev/null +++ b/06_IO_Devices/RTP.v @@ -0,0 +1,27 @@ +/** + * The special function register RTP receives bytes from the touch panel + * controller AR1021. + * + * When load=1 transmission of byte in[7:0] is initiated. The byte is send to + * SDO bitwise together with 8 clock signals on SCK. At the same time RTP + * receives a byte at SDI. During transmission out[15] is 1. The transmission + * of a byte takes 256 clock cycles (32 cycles for each bit to achieve a slower + * transfer rate). Every 32 clock cycles one bit is shifted out. In the middle + * of each bit at counter number 31 the bit SDI is sampled. When transmission + * is completed out[15]=0 and RTP outputs the received byte to out[7:0]. + */ +`default_nettype none + +module RTP( + input clk, + input load, + input [15:0] in, + output [15:0] out, + output SDO, + input SDI, + output SCK +); + + // Put your code here: + +endmodule diff --git a/06_IO_Devices/Readme.md b/06_IO_Devices/Readme.md new file mode 100644 index 0000000..c131e0d --- /dev/null +++ b/06_IO_Devices/Readme.md @@ -0,0 +1,59 @@ +# 06 IO Devices + +Build the following special function register to connect HACK to I/O-devices: `UART_TX`, `UART_RX`, `SPI`, `SRAM`, `GO`, `LCD` and `RTP`. For every special function register we provide a folder with implementation details and a testbench. The special function register must be memory mapped, so HACK can read/write data from/to the IO-device. + +| address | I/O dev | function | +| ------- | --------- | -------------------------------------------------- | +| 4096 | LED | 0 = led off, 1 = led on | +| 4097 | BUT | 0 = button pressed "down", 1 = button released | +| 4098 | UART_TX | transmit byte to UART with 115200 baud 8N1 | +| 4099 | UART_RX | receive byte from UART with 115200 baud 8N1 | +| 4100 | SPI | read/write spi flash memory chip | +| 4101 | SRAM_ADDR | address of external SRAM chip | +| 4102 | SRAM_DATA | read/write data from/to external SRAM chip | +| 4103 | GO | Start execution of instructions from external SRAM | +| 4104 | LCD8 | write 8bit command/data to LCD screen | +| 4105 | LCD16 | write 16bit data to LCD screen | +| 4106 | RTP | read/write byte from/to resistive touch panel | +| 4107 | DEBUG0 | used for debugging | +| 4108 | DEBUG1 | used for debugging | +| 4109 | DEBUG2 | used for debugging | +| 4110 | DEBUG3 | used for debugging | +| 4111 | DEBUG4 | used for debugging | + +For every special function register we will need the appropriate software to talk to the device. The simpler device drivers (UART, SPI, SRAM and GO) can be implemented in assembler. After completing the devices UART, SPI, SRAM and GO we will be able to fill the SRAM chip with up to 64K words (16bit) of HACK code. This will enable us to run JACK-OS and applications on HACK. The more sofisticated device drivers for LCD and RTP will be implemented in JACK language. + +### Proposed implementation + +![](/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/00_HACK/HACK.png) + +*** + +### Project + ++ Copy `HACK.v` from `05_Computer_Architecture` into `06_IO_Devices` and add one IO-Device at time at the designated memory mapped address. Implement the corresponding special function register and run the test bench. + + ```shell + $ cd 0X_device + $ apio clean + $ apio sim + ``` + ++ Implement the designated assembler program, install the binary into `00_HACK` and run the testbench: + + ```shell + $ cd 0X_device + $ make + $ cd ../00_HACK + $ apio clean + $ apio sim + ``` +* Run `HACK` in real hardware on iCE40HX1K-EVB with the device attached as real device. + + ```shell + $ cd 00_HACK + $ apio clean + $ apio upload + ``` + +* Check if attached IO-Device is working accorging to the uploaded software. \ No newline at end of file diff --git a/06_IO_Devices/SPI.v b/06_IO_Devices/SPI.v new file mode 100644 index 0000000..0a9bef5 --- /dev/null +++ b/06_IO_Devices/SPI.v @@ -0,0 +1,24 @@ +/** + * SPI controller for W25Q16BV + * + * When load=1 transmission of byte in[7:0] is initiated. The byte is send to + * MOSI (master out slave in) bitwise together with 8 clock signals on SCK. + * At the same time the SPI recieves a byte at MISO (master in slave out). + * Sampling of MISO is done at rising edge of SCK and shiftingis done at + */ +`default_nettype none + +module SPI( + input clk, + input load, + input [15:0] in, + output [15:0] out, + output CSX, + output SDO, + input SDI, + output SCK +); + + // Put your code here: + +endmodule diff --git a/06_IO_Devices/SRAM_D.v b/06_IO_Devices/SRAM_D.v new file mode 100644 index 0000000..c4bd8ac --- /dev/null +++ b/06_IO_Devices/SRAM_D.v @@ -0,0 +1,25 @@ +/** + * SRAM controller: + * If load[t] == 1 then out[t+1] = in[t] + * OEX[t+1] = 1 + * WEX[t+1] = 0 + * DATA[t+1] = in[t] (DATA is configured as output) + * At any other time: + * out = DATA (DATA is configured as input) + * CSX =0; + */ +`default_nettype none +module SRAM_D( + input clk, + input load, + input [15:0] in, + output [15:0] out, + inout [15:0] DATA, // SRAM data 16 Bit + output CSX, // SRAM chip_enable_not + output OEX, // SRAM output_enable_not + output WEX // SRAM write_enable_not +); + + // Put your code here: + +endmodule diff --git a/06_IO_Devices/UartRX.v b/06_IO_Devices/UartRX.v new file mode 100644 index 0000000..8d5285b --- /dev/null +++ b/06_IO_Devices/UartRX.v @@ -0,0 +1,20 @@ +/** + * UartRX receives bytes over UART + * + * When clear = 1 the chip clears the receive buffer and is ready to receive + * next byte. out[15] is set to 1 to show, that chip is ready to receive next + * byte. When RX goes low the chip starts sampling the RX line. After reading + * of byte completes, chip ouputs the received byte to out[7:0]] with out[15]=0. + */ +`default_nettype none + +module UartRX( + input clk, + input clear, + input RX, + output [15:0] out +); + + // Put your code here: + +endmodule diff --git a/06_IO_Devices/UartTX.v b/06_IO_Devices/UartTX.v new file mode 100644 index 0000000..04532a7 --- /dev/null +++ b/06_IO_Devices/UartTX.v @@ -0,0 +1,21 @@ +/** + * UartTX controls transmission of bytes over UART. + * + * When load = 1 the chip starts serial transmission of the byte in[7:0] to the + * TX line according to the protocoll 8N1 with 115200 baud. During transmission + * out[15] is set to high (busy). The transmission is finished after 2170 clock + * cycles (10 byte a 217 cycle each). When transmission completes out[15] goes + * low again (ready). + */ +`default_nettype none +module UartTX( + input clk, + input load, + input [15:0] in, + output TX, + output [15:0] out +); + + // Put your code here: + +endmodule diff --git a/07_Operating_System/00_HACK/And.v b/07_Operating_System/00_HACK/And.v new file mode 100644 index 0000000..7690503 --- /dev/null +++ b/07_Operating_System/00_HACK/And.v @@ -0,0 +1,17 @@ +/** + * And gate: + * out = 1 if (a == 1 and b == 1) + * 0 otherwise + */ + +`default_nettype none +module And( + input a, + input b, + output out +); + + // Put your code here: + and(out,a,b); + +endmodule diff --git a/07_Operating_System/00_HACK/Bit.v b/07_Operating_System/00_HACK/Bit.v new file mode 100644 index 0000000..def1232 --- /dev/null +++ b/07_Operating_System/00_HACK/Bit.v @@ -0,0 +1,19 @@ +/** + * 1-bit register: + * If load[t] == 1 then out[t+1] = in[t] + * else out does not change (out[t+1] = out[t]) + */ + +`default_nettype none +module Bit( + input clk, + input in, + input load, + output out +); + + reg out = 0; + always @(posedge clk) + out <= load?in:out; + +endmodule diff --git a/07_Operating_System/00_HACK/BitShift8L.v b/07_Operating_System/00_HACK/BitShift8L.v new file mode 100644 index 0000000..32311c3 --- /dev/null +++ b/07_Operating_System/00_HACK/BitShift8L.v @@ -0,0 +1,22 @@ +/** +* 8-bit Shiftregister (shifts to left) +* if (load == 1) out[t+1] = in[t] +* else if (shift == 1) out[t+1] = out[t]<<1 | inLSB +* (shift one position to left and insert inLSB as least significant bit) +*/ + +`default_nettype none +module BitShift8L( + input clk, + input [7:0] in, + input inLSB, + input load, + input shift, + output [7:0] out +); + + reg [7:0] out=0; + always @(posedge clk) + out <= load?in:(shift?{out[6:0],inLSB}:out); + +endmodule diff --git a/07_Operating_System/00_HACK/BitShift9R.v b/07_Operating_System/00_HACK/BitShift9R.v new file mode 100644 index 0000000..06c2638 --- /dev/null +++ b/07_Operating_System/00_HACK/BitShift9R.v @@ -0,0 +1,22 @@ +/** +* 10 bit Shiftregister (shifts to right) +* if (load == 1) out[t+1] = in[t] +* else if (shift == 1) out[t+1] = out[t]>>1 | (inMSB<<9) +* (shift one position to right and insert inMSB as most significant bit) +*/ + +`default_nettype none +module BitShift9R( + input clk, + input [8:0] in, + input inMSB, + input load, + input shift, + output [8:0] out +); + + reg [8:0] out = 0; + always @(posedge clk) + out <= load?in:(shift?{inMSB,out[8:1]}:out); + +endmodule diff --git a/07_Operating_System/00_HACK/Buffer.v b/07_Operating_System/00_HACK/Buffer.v new file mode 100644 index 0000000..ca859d4 --- /dev/null +++ b/07_Operating_System/00_HACK/Buffer.v @@ -0,0 +1,14 @@ +/** + * Buffer: + * out = in + */ + +`default_nettype none +module Buffer( + input in, + output out +); + + assign out = in; + +endmodule diff --git a/07_Operating_System/00_HACK/Buffer16.v b/07_Operating_System/00_HACK/Buffer16.v new file mode 100644 index 0000000..81b0052 --- /dev/null +++ b/07_Operating_System/00_HACK/Buffer16.v @@ -0,0 +1,14 @@ +/** + * 16-bit bitwise Buffer: + * for i = 0..15: out[i] = in[i] + */ + +`default_nettype none +module Buffer16( + input [15:0] in, + output [15:0] out +); + + assign out = in; + +endmodule diff --git a/07_Operating_System/00_HACK/CPU.v b/07_Operating_System/00_HACK/CPU.v new file mode 100644 index 0000000..f1d7fa2 --- /dev/null +++ b/07_Operating_System/00_HACK/CPU.v @@ -0,0 +1,37 @@ +`default_nettype none +module CPU( + input clk, + input [15:0] inM, + input [15:0] instruction, + input reset, + output [15:0] outM, + output writeM, + output [15:0] addressM, + output [15:0] pc +); + + // Compare + reg [15:0] addressM=0; + reg [15:0] regD=0; + reg [15:0] pc=0; + wire [15:0] x,y; + wire zr,ng; + assign x = instruction[10]?(instruction[11]?~0:~regD):(instruction[11]?0:regD); + assign y = instruction[8]?(instruction[9]?~0:~(instruction[12]?inM:addressM)):(instruction[9]?0:(instruction[12]?inM:addressM)); + assign outM = instruction[6]?(instruction[7]?~(x+y):~(x&y)):(instruction[7]?(x+y):(x&y)); + wire comp; + wire jmp; + assign comp = instruction[15] && instruction[14] && instruction[13]; + assign zr = (outM==0); + assign ng = outM[15]; + assign jmp = comp && ((ng&&instruction[2])||(zr&&instruction[1])||(~(ng|zr)&&instruction[0])); + + always @(posedge clk) begin + addressM <= comp?(instruction[5]?outM:addressM) : instruction; + regD <= comp?(instruction[4]?outM:regD) : regD; + pc <= reset?0 : (jmp?addressM:pc+1); + end + wire writeM; + assign writeM = comp?instruction[3]:0; + +endmodule diff --git a/07_Operating_System/00_HACK/Clock25_Reset20.v b/07_Operating_System/00_HACK/Clock25_Reset20.v new file mode 100644 index 0000000..d3fa292 --- /dev/null +++ b/07_Operating_System/00_HACK/Clock25_Reset20.v @@ -0,0 +1,18 @@ +`default_nettype none +module Clock25_Reset20( + input CLK, // external clock 100 MHz + output clk, // internal clock 25 Mhz + output reset // reset signal +); + + // put your code here: + reg [15:0] n=0; + always @(posedge CLK) + n <= n + 1; + assign clk = n[1]; + reg resetx=0; + always @(posedge clk) + resetx <= n[11]?1:resetx; + wire reset=~resetx; + +endmodule diff --git a/07_Operating_System/00_HACK/Counter.v b/07_Operating_System/00_HACK/Counter.v new file mode 100644 index 0000000..724154b --- /dev/null +++ b/07_Operating_System/00_HACK/Counter.v @@ -0,0 +1,19 @@ +/** + * A 16-bit counter with reset control bits. + * if (reset[t] == 1) out[t+1] = 0 + * else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition) + * else out[t+1] = out[t] + */ + +`default_nettype none +module Counter( + input clk, + input inc, + input reset, + output [15:0] out +); + reg [15:0] out=0; + always @(posedge clk) + out <= reset?0:(inc?out+1:out); + +endmodule diff --git a/07_Operating_System/00_HACK/DFF.v b/07_Operating_System/00_HACK/DFF.v new file mode 100644 index 0000000..605d65c --- /dev/null +++ b/07_Operating_System/00_HACK/DFF.v @@ -0,0 +1,21 @@ +/** +* Data-Flip-Flop +* out[t+1] = in[t] +*/ + +`default_nettype none +module DFF( + input clk, + input in, + output out +); + + // No need to implement this module + // This module is implemented in verilog using reg-variables + reg out=0; + always @(posedge clk) + if (in) out <= 1'b1; + else out <= 1'b0; + +endmodule + diff --git a/07_Operating_System/00_HACK/DMux.v b/07_Operating_System/00_HACK/DMux.v new file mode 100644 index 0000000..81a82e4 --- /dev/null +++ b/07_Operating_System/00_HACK/DMux.v @@ -0,0 +1,18 @@ +/** + * Demultiplexor: + * {a, b} = {in, 0} if sel == 0 + * {0, in} if sel == 1 + */ + +`default_nettype none +module DMux( + input in, + input sel, + output a, + output b +); + + assign a = ~sel∈ + assign b = sel∈ + +endmodule diff --git a/07_Operating_System/00_HACK/DMux8Way.v b/07_Operating_System/00_HACK/DMux8Way.v new file mode 100644 index 0000000..81a0707 --- /dev/null +++ b/07_Operating_System/00_HACK/DMux8Way.v @@ -0,0 +1,32 @@ +/** + * 8-way demultiplexor: + * {a, b, c, d, e, f, g, h} = {in, 0, 0, 0, 0, 0, 0, 0} if sel == 000 + * {0, in, 0, 0, 0, 0, 0, 0} if sel == 001 + * etc. + * {0, 0, 0, 0, 0, 0, 0, in} if sel == 111 + */ + +`default_nettype none +module DMux8Way( + input in, + input [2:0] sel, + output a, + output b, + output c, + output d, + output e, + output f, + output g, + output h +); + + assign a = (sel==0)?in:0; + assign b = (sel==1)?in:0; + assign c = (sel==2)?in:0; + assign d = (sel==3)?in:0; + assign e = (sel==4)?in:0; + assign f = (sel==5)?in:0; + assign g = (sel==6)?in:0; + assign h = (sel==7)?in:0; + +endmodule diff --git a/07_Operating_System/00_HACK/HACK_tb.gtkw b/07_Operating_System/00_HACK/HACK_tb.gtkw new file mode 100644 index 0000000..bfcae80 --- /dev/null +++ b/07_Operating_System/00_HACK/HACK_tb.gtkw @@ -0,0 +1,52 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Mon Dec 19 17:25:20 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/07_JACK_OS/00_HACK/HACK_tb.vcd" +[dumpfile_mtime] "Mon Dec 19 17:24:51 2022" +[dumpfile_size] 116364543 +[savefile] "/home/micha/gitlab/nand2tetris/07_JACK_OS/00_HACK/HACK_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] 0 40 +*-28.000000 353135000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] HACK_tb. +[treeopen] HACK_tb.HACK. +[sst_width] 281 +[signals_width] 180 +[sst_expanded] 1 +[sst_vpaned_height] 259 +@200 +-GPIO +@28 +HACK_tb.HACK.BUT[1:0] +HACK_tb.HACK.LED[1:0] +@200 +-UART +@28 +HACK_tb.HACK.UART_RX +HACK_tb.HACK.UART_TX +@200 +-LCD +@28 +HACK_tb.HACK.LCD_CSX +HACK_tb.HACK.LCD_DCX +HACK_tb.HACK.LCD_SDO +HACK_tb.HACK.LCD_SCK +@200 +-RTP +@28 +HACK_tb.HACK.RTP_SDI +HACK_tb.HACK.RTP_SDO +HACK_tb.HACK.RTP_SCK +@200 +-DEBUG +@821 +HACK_tb.HACK.outDEBUG0[15:0] +@420 +HACK_tb.HACK.outDEBUG1[15:0] +HACK_tb.HACK.outDEBUG2[15:0] +HACK_tb.HACK.outDEBUG3[15:0] +HACK_tb.HACK.outDEBUG4[15:0] +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/07_Operating_System/00_HACK/HACK_tb.v b/07_Operating_System/00_HACK/HACK_tb.v new file mode 100644 index 0000000..02bdcb8 --- /dev/null +++ b/07_Operating_System/00_HACK/HACK_tb.v @@ -0,0 +1,60 @@ +`timescale 10ns/1ns +`default_nettype none +module HACK_tb(); + +reg CLK = 0; +reg [1:0] BUT = 3; +wire [1:0] LED; +wire RX,TX; +wire LCD_DCX,LCD_SDO,LCD_SCK,LCD_CSX; +wire RTP_SDI; +wire RTP_SCK,RTP_SDO; + +HACK HACK( + .CLK(CLK), + .BUT(BUT), + .LED(LED), + .UART_RX(RX), + .UART_TX(TX), + .LCD_DCX(LCD_DCX), + .LCD_SDO(LCD_SDO), + .LCD_SCK(LCD_SCK), + .LCD_CSX(LCD_CSX), + .RTP_SDO(RTP_SDO), + .RTP_SDI(RTP_SDI), + .RTP_SCK(RTP_SCK) +); + +always #0.5 CLK = ~CLK; + +//Simulate UART +reg [9:0] uart = 10'b1111111111; +reg [15:0] baudrate = 0; +always @(posedge CLK) + baudrate <= (baudrate==866)?0:baudrate+1; +always @(posedge CLK) + if (baudrate==0) uart <= {1'b1,uart[9:1]}; +assign RX = uart[0]; + //Simulate RTP + reg [40:0] spi={1'b0,8'd128,8'd10,8'd25,8'd8,8'd22}; + assign RTP_SDI = spi[40]; + always @(posedge (RTP_SCK)) + spi <= {spi[39:0],1'b0}; + +initial begin + $dumpfile("HACK_tb.vcd"); + $dumpvars(0, HACK_tb); + + #15000 + #30000 + #30000 uart = (("R"<<2)|1); + #30000 uart = (("X"<<2)|1); + #30000 + #30000 BUT = 1; + #30000 + #30000 BUT = 0; + #400000 + $finish; +end + +endmodule diff --git a/07_Operating_System/00_HACK/Hack.dia b/07_Operating_System/00_HACK/Hack.dia new file mode 100644 index 0000000..0f5f83b Binary files /dev/null and b/07_Operating_System/00_HACK/Hack.dia differ diff --git a/07_Operating_System/00_HACK/Hack.pcf b/07_Operating_System/00_HACK/Hack.pcf new file mode 100644 index 0000000..d064cce --- /dev/null +++ b/07_Operating_System/00_HACK/Hack.pcf @@ -0,0 +1,68 @@ +# physical constrain file +# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40HX1K-EVB +# compare to the schematic of the board and the datasheet of fpga + +set_io CLK 15 # SYSCLOCK 100 MHz + +set_io RST 41 # BUT1 +set_io BUT 42 # BUT2 + +set_io LED[0] 40 # LED1 +set_io LED[1] 51 # LED2 + +set_io UART_RX 36 # PIO2_8/RxD connected to pin 3 of UEXT (PGM) +set_io UART_TX 37 # PIO2_9/TxD connected to pin 4 of UEXT (PGM) + +set_io SPI_MOSI 45 # iCE40-SDO +set_io SPI_MISO 46 # iCE40-SDI +set_io SPI_SCK 48 # iCE40-SCK +set_io SPI_CEN 49 # iCE40-SS_B + +set_io SRAM_ADDR[0] 79 # SA0 +set_io SRAM_ADDR[1] 80 # SA1 +set_io SRAM_ADDR[2] 81 # SA2 +set_io SRAM_ADDR[3] 82 # SA3 +set_io SRAM_ADDR[4] 83 # SA4 +set_io SRAM_ADDR[5] 85 # SA5 +set_io SRAM_ADDR[6] 86 # SA6 +set_io SRAM_ADDR[7] 87 # SA7 +set_io SRAM_ADDR[8] 89 # SA8 +set_io SRAM_ADDR[9] 90 # SA9 +set_io SRAM_ADDR[10] 91 # SA10 +set_io SRAM_ADDR[11] 93 # SA11 +set_io SRAM_ADDR[12] 94 # SA12 +set_io SRAM_ADDR[13] 95 # SA13 +set_io SRAM_ADDR[14] 96 # SA14 +set_io SRAM_ADDR[15] 97 # SA15 +set_io SRAM_ADDR[16] 99 # SA16 +set_io SRAM_ADDR[17] 100 # SA17 + +set_io SRAM_CEN 78 # SRAM_#CS +set_io SRAM_OEN 74 # SRAM_#OE +set_io SRAM_WEN 73 # SRAM_#WE + +set_io SRAM_DATA[0] 62 # SD0 +set_io SRAM_DATA[1] 63 # SD1 +set_io SRAM_DATA[2] 64 # SD2 +set_io SRAM_DATA[3] 65 # SD3 +set_io SRAM_DATA[4] 66 # SD4 +set_io SRAM_DATA[5] 68 # SD5 +set_io SRAM_DATA[6] 69 # SD6 +set_io SRAM_DATA[7] 71 # SD7 +set_io SRAM_DATA[8] 72 # SD8 +set_io SRAM_DATA[9] 60 # SD9 +set_io SRAM_DATA[10] 59 # SD10 +set_io SRAM_DATA[11] 57 # SD11 +set_io SRAM_DATA[12] 56 # SD12 +set_io SRAM_DATA[13] 54 # SD13 +set_io SRAM_DATA[14] 53 # SD14 +set_io SRAM_DATA[15] 52 # SD15 + +set_io LCD_DCN 1 # PIO3_1A connected to pin 5 of GPIO1 +set_io LCD_MOSI 2 # PIO3_1B connected to pin 7 of GPIO1 +set_io LCD_SCK 3 # PIO3_2A connected to pin 9 of GPIO1 +set_io LCD_CEN 4 # PIO3_2B connected to pin 11 of GPIO1 + +set_io RTP_MISO 7 # PIO3_3A connected to pin 13 of GPIO1 +set_io RTP_MOSI 8 # PIO3_3B connected to pin 15 of GPIO1 +set_io RTP_SCK 9 # PIO3_5A connected to pin 17 of GPIO1 diff --git a/07_Operating_System/00_HACK/Hack.png b/07_Operating_System/00_HACK/Hack.png new file mode 100644 index 0000000..58f557a Binary files /dev/null and b/07_Operating_System/00_HACK/Hack.png differ diff --git a/07_Operating_System/00_HACK/Hack_tb.gtkw b/07_Operating_System/00_HACK/Hack_tb.gtkw new file mode 100644 index 0000000..56f882e --- /dev/null +++ b/07_Operating_System/00_HACK/Hack_tb.gtkw @@ -0,0 +1,55 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Sun Nov 27 17:22:57 2022 +[*] +[dumpfile] "/home/micha/gitlab/nand2tetris/07_JACK_OS/00_HACK/Hack_tb.vcd" +[dumpfile_mtime] "Sun Nov 27 17:22:36 2022" +[dumpfile_size] 47620156 +[savefile] "/home/micha/gitlab/nand2tetris/07_JACK_OS/00_HACK/Hack_tb.gtkw" +[timestart] 0 +[size] 1920 963 +[pos] -1 -1 +*-28.420643 385300000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] Hack_tb. +[treeopen] Hack_tb.HACK. +[sst_width] 281 +[signals_width] 200 +[sst_expanded] 1 +[sst_vpaned_height] 261 +@28 +Hack_tb.clk_in +Hack_tb.HACK.clk +@29 +Hack_tb.HACK.BUT +@200 +-GPIO +@28 +Hack_tb.HACK.loadLED +Hack_tb.led[1:0] +@200 +-UART +@28 +Hack_tb.HACK.loadRX +Hack_tb.HACK.loadTX +Hack_tb.HACK.UART_RX +Hack_tb.HACK.UART_TX +@200 +-SPI +@28 +Hack_tb.HACK.loadSPI +@22 +Hack_tb.spi_cmd[31:0] +Hack_tb.spi[23:0] +@28 +Hack_tb.mosi +Hack_tb.miso +Hack_tb.sck +Hack_tb.cen +Hack_tb.HACK.SPI.load +@200 +-LCD +@22 +Hack_tb.lcd_c[7:0] +Hack_tb.lcd_d[15:0] +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/07_Operating_System/00_HACK/Include.v b/07_Operating_System/00_HACK/Include.v new file mode 100644 index 0000000..334cb82 --- /dev/null +++ b/07_Operating_System/00_HACK/Include.v @@ -0,0 +1,11 @@ +`include "../../05_Computer_Architecture/Memory.v" + +`include "../../06_IO_Devices/HACK.v" +`include "../../06_IO_Devices/UartTX.v" +`include "../../06_IO_Devices/UartRX.v" +`include "../../06_IO_Devices/SPI.v" +`include "../../06_IO_Devices/SRAM_D.v" +`include "../../06_IO_Devices/GO.v" +`include "../../06_IO_Devices/InOut.v" +`include "../../06_IO_Devices/LCD.v" +`include "../../06_IO_Devices/RTP.v" diff --git a/07_Operating_System/00_HACK/Mux.v b/07_Operating_System/00_HACK/Mux.v new file mode 100644 index 0000000..943bea0 --- /dev/null +++ b/07_Operating_System/00_HACK/Mux.v @@ -0,0 +1,17 @@ +/** + * Multiplexor: + * out = a if sel == 0 + * b otherwise + */ + +`default_nettype none +module Mux( + input a, + input b, + input sel, + output out +); + + assign out = sel?b:a; + +endmodule diff --git a/07_Operating_System/00_HACK/Mux16.v b/07_Operating_System/00_HACK/Mux16.v new file mode 100644 index 0000000..634b157 --- /dev/null +++ b/07_Operating_System/00_HACK/Mux16.v @@ -0,0 +1,17 @@ +/** + * 16-bit multiplexor: + * for i = 0..15 out[i] = a[i] if sel == 0 + * b[i] if sel == 1 + */ + +`default_nettype none +module Mux16( + input [15:0] a, + input [15:0] b, + input sel, + output [15:0] out +); + + assign out = sel?b:a; + +endmodule diff --git a/07_Operating_System/00_HACK/Mux8Way16.v b/07_Operating_System/00_HACK/Mux8Way16.v new file mode 100644 index 0000000..1d3031b --- /dev/null +++ b/07_Operating_System/00_HACK/Mux8Way16.v @@ -0,0 +1,32 @@ +/** + * 16-bit multiplexor: + * for i = 0..15 out[i] = a[i] if sel == 0 + * b[i] if sel == 1 + */ + +`default_nettype none +module Mux8Way16( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input [15:0] e, + input [15:0] f, + input [15:0] g, + input [15:0] h, + input [2:0] sel, + output reg [15:0] out +); + always @(*) begin + case (sel) + 0 : out = a; + 1 : out = b; + 2 : out = c; + 3 : out = d; + 4 : out = e; + 5 : out = f; + 6 : out = g; + 7 : out = h; + endcase + end +endmodule diff --git a/07_Operating_System/00_HACK/Not.v b/07_Operating_System/00_HACK/Not.v new file mode 100644 index 0000000..cc21433 --- /dev/null +++ b/07_Operating_System/00_HACK/Not.v @@ -0,0 +1,15 @@ +/** + * Not gate: + * out = not in + */ + +`default_nettype none +module Not( + input in, + output out +); + + // Put your code here: + not(out,in); + +endmodule diff --git a/07_Operating_System/00_HACK/Or.v b/07_Operating_System/00_HACK/Or.v new file mode 100644 index 0000000..724e430 --- /dev/null +++ b/07_Operating_System/00_HACK/Or.v @@ -0,0 +1,17 @@ + /** + * Or gate: + * out = 1 if (a == 1 or b == 1) + * 0 otherwise + */ + +`default_nettype none +module Or( + input a, + input b, + output out +); + + // Put your code here: + or(out,a,b); + +endmodule diff --git a/07_Operating_System/00_HACK/Or8Way.v b/07_Operating_System/00_HACK/Or8Way.v new file mode 100644 index 0000000..3032c66 --- /dev/null +++ b/07_Operating_System/00_HACK/Or8Way.v @@ -0,0 +1,14 @@ +/** + * 8-way Or: + * out = (in[0] or in[1] or ... or in[7]) + */ + +`default_nettype none +module Or8Way( + input [7:0] in, + output out +); + + // Put your code here: + assign out = |in; +endmodule diff --git a/07_Operating_System/00_HACK/PC.v b/07_Operating_System/00_HACK/PC.v new file mode 100644 index 0000000..9e1e96e --- /dev/null +++ b/07_Operating_System/00_HACK/PC.v @@ -0,0 +1,22 @@ +/** + * A 16-bit counter with load and reset control bits. + * if (reset[t] == 1) out[t+1] = 0 + * else if (load[t] == 1) out[t+1] = in[t] + * else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition) + * else out[t+1] = out[t] + */ + +`default_nettype none +module PC( + input clk, + input [15:0] in, + input load, + input inc, + input reset, + output [15:0] out +); + + reg [15:0] out = 0; + always @(posedge clk) + out <= reset?0:(load?in:(inc?out+1:out)); +endmodule diff --git a/07_Operating_System/00_HACK/RAM3840.v b/07_Operating_System/00_HACK/RAM3840.v new file mode 100644 index 0000000..2949076 --- /dev/null +++ b/07_Operating_System/00_HACK/RAM3840.v @@ -0,0 +1,24 @@ +/** +* RAM implements 3840 Bytes of RAM addressed from 0000 - 3839 +* out = M[address] +* if (load =i= 1) M[address][t+1] = in[t] +*/ + +`default_nettype none +module RAM3840( + input clk, + input [15:0] address, + input [15:0] in, + input load, + output [15:0] out +); + + // No need to implement this chip + // RAM is implemented using BRAM of iCE40 + reg [15:0] regRAM [0:3839]; + always @(posedge clk) + if (load) regRAM[address[11:0]] <= in; + + assign out = regRAM[address[11:0]]; + +endmodule diff --git a/07_Operating_System/00_HACK/ROM.v b/07_Operating_System/00_HACK/ROM.v new file mode 100644 index 0000000..dcbe4b8 --- /dev/null +++ b/07_Operating_System/00_HACK/ROM.v @@ -0,0 +1,26 @@ +/** + * instruction memory at boot time + * The instruction memory is read only (ROM) and + * preloaded with 256 x 16bit of Hackcode holding the bootloader. + * + * instruction = ROM[pc] + */ + +`default_nettype none +module ROM( + input [15:0] pc, + output [15:0] instruction +); + + // No need to implement this chip + // The file ROM.BIN holds the hack code + parameter ROMFILE = "ROM.hack"; + + reg [15:0] mem [0:65535]; + assign instruction = mem[pc]; + + initial begin + $readmemb(ROMFILE,mem); + end + +endmodule diff --git a/07_Operating_System/00_HACK/Register.v b/07_Operating_System/00_HACK/Register.v new file mode 100644 index 0000000..53dc3cb --- /dev/null +++ b/07_Operating_System/00_HACK/Register.v @@ -0,0 +1,19 @@ +/** + * 16-bit register: + * If load[t] == 1 then out[t+1] = in[t] + * else out does not change + */ + +`default_nettype none + +module Register( + input clk, + input [15:0] in, + input load, + output [15:0] out +); + reg [15:0] out = 0; + always @(posedge clk) + out <= load?in:out; + initial out = 0; +endmodule diff --git a/07_Operating_System/00_HACK/Switch.v b/07_Operating_System/00_HACK/Switch.v new file mode 100644 index 0000000..bbb3e10 --- /dev/null +++ b/07_Operating_System/00_HACK/Switch.v @@ -0,0 +1,20 @@ +/** +* One Bit-register, that can be switched on and off +* +* if (out[t] == 0) and (on[t] == 1) out[t+1] = 1 +* if (out[t] == 1) and (off[t] == 1) out[t+1] = 0 +*/ + +`default_nettype none +module Switch( + input clk, + input on, + input off, + output out +); + + reg out = 0; + always @(posedge clk) + out <= (on&off)?(~out):(on?1:(off?0:(out?1:0))); + +endmodule diff --git a/07_Operating_System/00_HACK/apio.ini b/07_Operating_System/00_HACK/apio.ini new file mode 100644 index 0000000..f98fb86 --- /dev/null +++ b/07_Operating_System/00_HACK/apio.ini @@ -0,0 +1,3 @@ +[env] +board = iCE40-HX1K-EVB + diff --git a/07_Operating_System/01_GPIO_Test/GPIO.jack b/07_Operating_System/01_GPIO_Test/GPIO.jack new file mode 120000 index 0000000..4583844 --- /dev/null +++ b/07_Operating_System/01_GPIO_Test/GPIO.jack @@ -0,0 +1 @@ +../GPIO.jack \ No newline at end of file diff --git a/07_Operating_System/01_GPIO_Test/Makefile b/07_Operating_System/01_GPIO_Test/Makefile new file mode 100644 index 0000000..29614ad --- /dev/null +++ b/07_Operating_System/01_GPIO_Test/Makefile @@ -0,0 +1,18 @@ +all: jack vm asm bin sim + +jack: + ../../tools/JackCompiler/JackCompiler.pyc ./ +vm: + ../../tools/VMTranslator/VMTranslator.pyc ./ +asm: + ../../tools/Assembler/assembler.pyc out.asm +bin: + ../../tools/AsciiToBin.py out.hack +sim: + cp out.hack ../00_HACK/ROM.hack +upload: + iceprogduino -o 64k -w out.bin +clean: + rm -f *.vm *.asm *.hack *.bin *~ + +.PHONY: all clean diff --git a/07_Operating_System/01_GPIO_Test/Readme.md b/07_Operating_System/01_GPIO_Test/Readme.md new file mode 100644 index 0000000..5e4cf85 --- /dev/null +++ b/07_Operating_System/01_GPIO_Test/Readme.md @@ -0,0 +1,50 @@ +## GPIO.jack + +This library provides access to `BUT` and `LED`. + +### GPIO-Test + +In the Testfolder `01_GPIO_Test` you find a minimal version of `Sys.jack` containing the init function `Sys.init()`, which is called after starting JACK-OS. `Sys.init()` is the JACK-OS version of `leds.asm`, which reads the BUT and writes the values to LED in an endless loop: + +``` +class Sys { + + function void init() { + do GPIO.init(4096); + while (true){ + do GPIO.writeLed(GPIO.readBut()); + } + return; + } +} +``` + +*** + +### Project + +* Implement `GPIO.jack` + +* Test in simulation: + + ``` + $ cd 01_GPIO_Test + $ make + $ cd ../00_HACK + $ apio clean + $ apio sim + ``` + + The test bench will simulate the pushing of BUT1/2. Check if the LED change accordingly. + + ![](gpio.png) + +* run in real hardware with HACK build at `06_IO_Devices/05_GO` (together with the bootloader). Build and upload GPIO_Test to iCE40HX1K-EVB with: + + ``` + $ cd 01_GPIO_Test + $ make + $ make upload + ``` + +* push buttons BUT on iCE40HX1K-EVB and check the LED. \ No newline at end of file diff --git a/07_Operating_System/01_GPIO_Test/Readme.md.backup b/07_Operating_System/01_GPIO_Test/Readme.md.backup new file mode 100644 index 0000000..b4399d9 --- /dev/null +++ b/07_Operating_System/01_GPIO_Test/Readme.md.backup @@ -0,0 +1,49 @@ +## GPIO.jack +This library provides access to `BUT` and `LED`. +### function void init(int addr) +Initialize LED (addr) and BUT (addr+1). +### function int readLed() +Returns the value of LED. +### function void writeLed(int c) +Write c to LED. +### function int readBut() +Returns the state of BUT. + +*** +## Project +In the Testfolder `01_GPIO_Test` you find a minimal version of `Sys.jack` containing the init function `Sys.init()`, which is called after starting JACK-OS. `Sys.init()` is the JACK-OS version of `leds.asm`, which reads the BUT and writes the values to LED in an endless loop: + +``` +class Sys { + + function void init() { + do GPIO.init(4096); + while (true){ + do GPIO.writeLed(GPIO.readBut()); + } + return; + } +} + +``` +* Implement `GPIO.jack` +* Test in simulation: +``` +$ cd 01_GPIO_Test +$ make +$ cd ../00_HACK +$ apio clean +$ apio sim +``` +The test bench will simulate the pushing of BUT1/2. Check if the LED change accordingly. + +![](gpio.png) + +* run in real hardware with HACK build at `06_IO_Devices/05_GO` (together with the bootloader). Build and upload GPIO_Test to iCE40HX1K-EVB with: +``` +$ cd 01_GPIO_Test +$ make +$ make upload +``` + +* push buttons BUT on iCE40HX1K-EVB and check the LED. \ No newline at end of file diff --git a/07_Operating_System/01_GPIO_Test/Sys.jack b/07_Operating_System/01_GPIO_Test/Sys.jack new file mode 100644 index 0000000..d82f4ba --- /dev/null +++ b/07_Operating_System/01_GPIO_Test/Sys.jack @@ -0,0 +1,15 @@ +/** + * A library that supports various program execution services. + */ +class Sys { + + /** Performs all the initializations required by the OS. */ + function void init() { + do GPIO.init(4096); + while (true){ + do GPIO.writeLed(GPIO.readBut()); + } + return; + } + +} diff --git a/07_Operating_System/01_GPIO_Test/gpio.png b/07_Operating_System/01_GPIO_Test/gpio.png new file mode 100644 index 0000000..3c7d6a1 Binary files /dev/null and b/07_Operating_System/01_GPIO_Test/gpio.png differ diff --git a/07_Operating_System/02_UART_Test/GPIO.jack b/07_Operating_System/02_UART_Test/GPIO.jack new file mode 100644 index 0000000..2877979 --- /dev/null +++ b/07_Operating_System/02_UART_Test/GPIO.jack @@ -0,0 +1,25 @@ +class GPIO { + static Array gpio; + + function void init(int addr){ + let gpio = addr; + return; + } + + function boolean readBut() { + if (gpio[1] & 2){ + return false; + } + return true; + } + + function void writeLed(int c){ + let gpio[0] = c; + return; + } + + function void readLed(){ + return gpio[0]; + } + +} diff --git a/07_Operating_System/02_UART_Test/Makefile b/07_Operating_System/02_UART_Test/Makefile new file mode 100644 index 0000000..29614ad --- /dev/null +++ b/07_Operating_System/02_UART_Test/Makefile @@ -0,0 +1,18 @@ +all: jack vm asm bin sim + +jack: + ../../tools/JackCompiler/JackCompiler.pyc ./ +vm: + ../../tools/VMTranslator/VMTranslator.pyc ./ +asm: + ../../tools/Assembler/assembler.pyc out.asm +bin: + ../../tools/AsciiToBin.py out.hack +sim: + cp out.hack ../00_HACK/ROM.hack +upload: + iceprogduino -o 64k -w out.bin +clean: + rm -f *.vm *.asm *.hack *.bin *~ + +.PHONY: all clean diff --git a/07_Operating_System/02_UART_Test/Readme.md b/07_Operating_System/02_UART_Test/Readme.md new file mode 100644 index 0000000..79b5d38 --- /dev/null +++ b/07_Operating_System/02_UART_Test/Readme.md @@ -0,0 +1,54 @@ +## UART.jack + +Library that provides character based access to `UART_TX` and `UART_RX`. + +### UART_Test + +In the Testfolder `02_UART_Test` you find a minimal version of `Sys.jack` containing the init function `Sys.init()`, which is called after starting JACK-OS. `Sys.init()` is the JACK-OS version of `echo.asm`, which reads the bytes received at `UART_RX` and writes the values to `UART_TX` in an endless loop: + +``` +class Sys { + + function void init() { + do UART.init(4098); + while (true){ + do UART.write(UART.read()); + } + return; + } +} +``` + +*** + +### Project + +* Implement `UART.jack` + +* Test in simulation: + + ``` + $ cd 02_UARTTest + $ make + $ cd ../00_HACK + $ apio clean + $ apio sim + ``` + + The test bench will simulate the transmission of "RX" to UART_RX. Check if HACK echoes to `UART_TX`. + + ![](uart.png) + +* run in real hardware with HACK build at `06_IO_Devices/05_GO` (together with the bootloader). Build and upload the UART_Test to iCE40HX1K-EVB with: + + ``` + $ cd 02_UART_Test + $ make + $ make upload + ``` + +* Connect HACK with your computer over UART, open a terminal program and type some chars. Check if HACK can echo them. + + ``` + $ tio /dev/ttyACM0 + ``` diff --git a/07_Operating_System/02_UART_Test/Readme.md.backup b/07_Operating_System/02_UART_Test/Readme.md.backup new file mode 100644 index 0000000..82a483f --- /dev/null +++ b/07_Operating_System/02_UART_Test/Readme.md.backup @@ -0,0 +1,46 @@ +## UART.jack +Library that provides access to `UART_TX` and `UART_RX`. + +*** +## Project +In the Testfolder `02_UART_Test` you find a minimal version of `Sys.jack` containing the init function `Sys.init()`, which is called after starting JACK-OS. `Sys.init()` is the JACK-OS version of `echo.asm`, which reads the bytes received at `UART_RX` and writes the values to `UART_TX` in an endless loop: + +``` +class Sys { + + function void init() { + do UART.init(4098); + while (true){ + do UART.write(UART.read()); + } + return; + } +} + +``` +* Implement `UART.jack` +* Test in simulation: +``` +$ cd 02_UARTTest +$ make +$ cd ../00_HACK +$ apio clean +$ apio sim +``` +The test bench will simulate the transmission of "RX" to UART_RX. Check if HACK echoes to `UART_TX`. + +![](uart.png) + +* run in real hardware with HACK build at `06_IO_Devices/05_GO` (together with the bootloader). Build and upload the UART_Test to iCE40HX1K-EVB with: + +``` +$ cd 02_UART_Test +$ make +$ make upload +``` + +* Connect HACK with your computer over UART, open a terminal program and type some chars. Check if HACK can echo them. + +``` +$ tio /dev/ttyACM0 +``` diff --git a/07_Operating_System/02_UART_Test/Sys.jack b/07_Operating_System/02_UART_Test/Sys.jack new file mode 100644 index 0000000..2d60a45 --- /dev/null +++ b/07_Operating_System/02_UART_Test/Sys.jack @@ -0,0 +1,17 @@ +/** + * A library that supports various program execution services. + */ +class Sys { + + /** Performs all the initializations required by the OS. */ + function void init() { + do UART.init(4098); + do UART.writeChar(71); + do UART.writeChar(79); + while (true){ + do UART.writeChar(UART.readChar()); + } + return; + } + +} diff --git a/07_Operating_System/02_UART_Test/UART.jack b/07_Operating_System/02_UART_Test/UART.jack new file mode 120000 index 0000000..e7e97fa --- /dev/null +++ b/07_Operating_System/02_UART_Test/UART.jack @@ -0,0 +1 @@ +../UART.jack \ No newline at end of file diff --git a/07_Operating_System/02_UART_Test/uart.png b/07_Operating_System/02_UART_Test/uart.png new file mode 100644 index 0000000..1cfafd6 Binary files /dev/null and b/07_Operating_System/02_UART_Test/uart.png differ diff --git a/07_Operating_System/03_Sys_Test/GPIO.jack b/07_Operating_System/03_Sys_Test/GPIO.jack new file mode 120000 index 0000000..4583844 --- /dev/null +++ b/07_Operating_System/03_Sys_Test/GPIO.jack @@ -0,0 +1 @@ +../GPIO.jack \ No newline at end of file diff --git a/07_Operating_System/03_Sys_Test/Main.jack b/07_Operating_System/03_Sys_Test/Main.jack new file mode 100644 index 0000000..2f4106c --- /dev/null +++ b/07_Operating_System/03_Sys_Test/Main.jack @@ -0,0 +1,11 @@ +class Main{ + + function void main() { + while(true){ + do GPIO.writeLed(GPIO.readLed()+1); + do Sys.wait(1); + } + return; + } + +} diff --git a/07_Operating_System/03_Sys_Test/Makefile b/07_Operating_System/03_Sys_Test/Makefile new file mode 100644 index 0000000..29614ad --- /dev/null +++ b/07_Operating_System/03_Sys_Test/Makefile @@ -0,0 +1,18 @@ +all: jack vm asm bin sim + +jack: + ../../tools/JackCompiler/JackCompiler.pyc ./ +vm: + ../../tools/VMTranslator/VMTranslator.pyc ./ +asm: + ../../tools/Assembler/assembler.pyc out.asm +bin: + ../../tools/AsciiToBin.py out.hack +sim: + cp out.hack ../00_HACK/ROM.hack +upload: + iceprogduino -o 64k -w out.bin +clean: + rm -f *.vm *.asm *.hack *.bin *~ + +.PHONY: all clean diff --git a/07_Operating_System/03_Sys_Test/Readme.md b/07_Operating_System/03_Sys_Test/Readme.md new file mode 100644 index 0000000..d6aaf67 --- /dev/null +++ b/07_Operating_System/03_Sys_Test/Readme.md @@ -0,0 +1,46 @@ +## Sys.jack + +A library that supports various program execution services. + +**Hint:** To debug the next projects in real hardware, we can implement one or both of the following strategies into `Sys.jack` + +1. Use LED to indicate the state of JACK-OS according to + +| LED[1:0] | Sys.jack | JACK-OS state | +| -------- | -------------- | ---------------------------------- | +| 00 | at entry | nothing happened yet | +| 01 | Sys.init() | start execution of Main.main() | +| 10 | Sys.halt() | Main.main() terminated succesfully | +| 11 | Sys.error(int) | a system error occured | + +2. We can use UART to send some chars according to the state of JACK-OS. e.g. send "GO" at `Sys.init()`, "HALT" at `Sys.halt()` and "ERR" at `Sys.error(int)`. + +*** + +### Project + +* Implement `Sys.jack` + +* Test in simulation. Change the delay time in `Main.jack` to 1ms. + + ``` + $ cd 03_Sys_Test + $ make + $ cd ../00_HACK + $ apio clean + $ apio sim + ``` + +* Check, if the LED toggles every 1 milli second: + + ![](sys.png) + +* run in real hardware. Set the delay to 1s = 1000ms with `Sys.wait(1000)` in `Main.main()`. + + ``` + $ cd 03_Sys_Test + $ make + $ make upload + ``` + +* Check if the LED change state every 1 second. \ No newline at end of file diff --git a/07_Operating_System/03_Sys_Test/Readme.md.backup b/07_Operating_System/03_Sys_Test/Readme.md.backup new file mode 100644 index 0000000..d68f806 --- /dev/null +++ b/07_Operating_System/03_Sys_Test/Readme.md.backup @@ -0,0 +1,40 @@ +## Sys.jack +A library that supports various program execution services. +*** +## Project +* Implement `Sys.jack` +* Test in simulation. Change the delay time in `Main.jack` to 1ms. +``` +$ cd 03_Sys_Test +$ make +$ cd ../00_HACK +$ apio clean +$ apio sim +``` + +Check, if the LED toggles every 1 milli second: + +![](sys.png) + +* run in real hardware. Set the delay to 1s = 1000ms with `Sys.wait(1000)` in `Main.main()`. +``` +$ cd 03_Sys_Test +$ make +$ make upload +``` + +* Check if the LED change state every 1 second. + +**Hint:** To debug the next projects in real hardware, we can implement one or both of the following strategies into `Sys.jack` + + +1. Use LED to indicate the state of JACK-OS according to + +|LED[1:0]|Sys.jack |JACK-OS state | +|------|-|-------| +|00 |at entry|nothing happened yet| +|01 |Sys.init()|start execution of Main.main()| +|10 |Sys.halt()|Main.main() terminated succesfully| +|11 |Sys.error(int)|a system error occured| + +2. We can use UART to send some chars according to the state of JACK-OS. e.g. send "GO" at Sys,init(), "HALT" at Sys.halt() and "ERR" at Sys.error(int). \ No newline at end of file diff --git a/07_Operating_System/03_Sys_Test/Sys.jack b/07_Operating_System/03_Sys_Test/Sys.jack new file mode 120000 index 0000000..4b50826 --- /dev/null +++ b/07_Operating_System/03_Sys_Test/Sys.jack @@ -0,0 +1 @@ +../Sys.jack \ No newline at end of file diff --git a/07_Operating_System/03_Sys_Test/UART.jack b/07_Operating_System/03_Sys_Test/UART.jack new file mode 120000 index 0000000..e7e97fa --- /dev/null +++ b/07_Operating_System/03_Sys_Test/UART.jack @@ -0,0 +1 @@ +../UART.jack \ No newline at end of file diff --git a/07_Operating_System/03_Sys_Test/sys.png b/07_Operating_System/03_Sys_Test/sys.png new file mode 100644 index 0000000..0c7b923 Binary files /dev/null and b/07_Operating_System/03_Sys_Test/sys.png differ diff --git a/07_Operating_System/04_Memory_Test/Array.jack b/07_Operating_System/04_Memory_Test/Array.jack new file mode 120000 index 0000000..3b12439 --- /dev/null +++ b/07_Operating_System/04_Memory_Test/Array.jack @@ -0,0 +1 @@ +../Array.jack \ No newline at end of file diff --git a/07_Operating_System/04_Memory_Test/GPIO.jack b/07_Operating_System/04_Memory_Test/GPIO.jack new file mode 120000 index 0000000..4583844 --- /dev/null +++ b/07_Operating_System/04_Memory_Test/GPIO.jack @@ -0,0 +1 @@ +../GPIO.jack \ No newline at end of file diff --git a/07_Operating_System/04_Memory_Test/Main.jack b/07_Operating_System/04_Memory_Test/Main.jack new file mode 100644 index 0000000..d49e54c --- /dev/null +++ b/07_Operating_System/04_Memory_Test/Main.jack @@ -0,0 +1,42 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/12/MemoryTest/Main.jack + +/** Test program for the OS Memory class. */ +class Main { + + /** Performs various memory manipulations. */ + function void main() { + var int temp; + var Array a, b, c; + + do Memory.poke(4107, 333); // RAM[4107] = 333 + let temp = Memory.peek(4107); + do Memory.poke(4108, temp + 1); // RAM[4108] = 334 + + let a = Array.new(3); // uses Memory.alloc + let a[2] = 222; + do Memory.poke(4109, a[2]); // RAM[4109] = 222 + + let b = Array.new(3); + let b[1] = a[2] - 100; + do Memory.poke(4110, b[1]); // RAM[4110] = 122 + + let c = Array.new(500); + let c[499] = a[2] - b[1]; + do Memory.poke(4111, c[499]); // RAM[4111] = 100 + + do a.dispose(); // uses Memory.deAlloc + do b.dispose(); + + let b = Array.new(3); + let b[0] = c[499] - 90; + do Memory.poke(4107, b[0]); // RAM[4107] = 10 + + do c.dispose(); + do b.dispose(); + + return; + } +} diff --git a/07_Operating_System/04_Memory_Test/Makefile b/07_Operating_System/04_Memory_Test/Makefile new file mode 100644 index 0000000..29614ad --- /dev/null +++ b/07_Operating_System/04_Memory_Test/Makefile @@ -0,0 +1,18 @@ +all: jack vm asm bin sim + +jack: + ../../tools/JackCompiler/JackCompiler.pyc ./ +vm: + ../../tools/VMTranslator/VMTranslator.pyc ./ +asm: + ../../tools/Assembler/assembler.pyc out.asm +bin: + ../../tools/AsciiToBin.py out.hack +sim: + cp out.hack ../00_HACK/ROM.hack +upload: + iceprogduino -o 64k -w out.bin +clean: + rm -f *.vm *.asm *.hack *.bin *~ + +.PHONY: all clean diff --git a/07_Operating_System/04_Memory_Test/Memory.jack b/07_Operating_System/04_Memory_Test/Memory.jack new file mode 120000 index 0000000..e8b63fa --- /dev/null +++ b/07_Operating_System/04_Memory_Test/Memory.jack @@ -0,0 +1 @@ +../Memory.jack \ No newline at end of file diff --git a/07_Operating_System/04_Memory_Test/MemoryTest.cmp b/07_Operating_System/04_Memory_Test/MemoryTest.cmp new file mode 100644 index 0000000..057958b --- /dev/null +++ b/07_Operating_System/04_Memory_Test/MemoryTest.cmp @@ -0,0 +1,2 @@ +|RAM[8000]|RAM[8001]|RAM[8002]|RAM[8003]|RAM[8004]|RAM[8005]| +| 333 | 334 | 222 | 122 | 100 | 10 | diff --git a/07_Operating_System/04_Memory_Test/MemoryTest.tst b/07_Operating_System/04_Memory_Test/MemoryTest.tst new file mode 100644 index 0000000..1da34fd --- /dev/null +++ b/07_Operating_System/04_Memory_Test/MemoryTest.tst @@ -0,0 +1,15 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/12/MemoryTest/MemoryTest.tst + +load, +output-file MemoryTest.out, +compare-to MemoryTest.cmp, +output-list RAM[8000]%D2.6.1 RAM[8001]%D2.6.1 RAM[8002]%D2.6.1 RAM[8003]%D2.6.1 RAM[8004]%D2.6.1 RAM[8005]%D2.6.1; + +repeat 1000000 { + vmstep; +} + +output; diff --git a/07_Operating_System/04_Memory_Test/Readme.md b/07_Operating_System/04_Memory_Test/Readme.md new file mode 100644 index 0000000..6ef0226 --- /dev/null +++ b/07_Operating_System/04_Memory_Test/Readme.md @@ -0,0 +1,33 @@ +## Memory.jack + +This library provides two services: direct access to the computer's main memory (RAM), and allocation and recycling of memory blocks. The Hack RAM consists of 3840 words, each holding a 16-bit binary number. + +Don't be afraid of the limited memory size of "only" 3840 words. Let the heap start at address 1024 with `do Memory.init(1024,3839)` in the Sys.init(). This will leave 768 words of stack, which is surely enough to run tetris. + +| addr | segment | +| --------- | ----------------------------- | +| 0-15 | R0-R15 (SP,LCL,ARG,THIS,THAT) | +| 16-255 | static | +| 256-1023 | stack | +| 1024-3839 | heap | +| 4096-4111 | IO-devices | + +*** + +### Project + +* Implement `Memory.jack` + +* Test in simulation: + + ``` + $ cd 04_Memory_Test + $ make + $ cd ../00_HACK + $ apio clean + $ apio sim + ``` + +* Check the content of special function register DEBUG0--DEBUG4. + + ![](memory.png) diff --git a/07_Operating_System/04_Memory_Test/Readme.md.backup b/07_Operating_System/04_Memory_Test/Readme.md.backup new file mode 100644 index 0000000..c957e4f --- /dev/null +++ b/07_Operating_System/04_Memory_Test/Readme.md.backup @@ -0,0 +1,28 @@ +## Memory.jack +This library provides two services: direct access to the computer's main memory (RAM), and allocation and recycling of memory blocks. The Hack RAM consists of 3840 words, each holding a 16-bit binary number. + +### function void init(int start, int end) +Initializes the class. First address of heap is start, last address of heap is end. +### function int peek(int address) +Returns the RAM value at the given address. +### function void poke(int address, int value) +Sets the RAM value at the given address to the given value. +### function int alloc(int size) +Finds an available RAM block of the given size and returns a reference to its base address. +### function void deAlloc(Array o) +De-allocates the given object (cast as an array) by making it available for future allocations. +*** +### Project +* Implement `Memory.jack` +* Test in simulation: +``` +$ cd 04_Memory_Test +$ make +$ cd ../00_HACK +$ apio clean +$ apio sim +``` + +* Check the content of special function register DEBUG0--DEBUG4. + +![](memory.png) diff --git a/07_Operating_System/04_Memory_Test/Sys.jack b/07_Operating_System/04_Memory_Test/Sys.jack new file mode 120000 index 0000000..4b50826 --- /dev/null +++ b/07_Operating_System/04_Memory_Test/Sys.jack @@ -0,0 +1 @@ +../Sys.jack \ No newline at end of file diff --git a/07_Operating_System/04_Memory_Test/UART.jack b/07_Operating_System/04_Memory_Test/UART.jack new file mode 120000 index 0000000..e7e97fa --- /dev/null +++ b/07_Operating_System/04_Memory_Test/UART.jack @@ -0,0 +1 @@ +../UART.jack \ No newline at end of file diff --git a/07_Operating_System/04_Memory_Test/memory.png b/07_Operating_System/04_Memory_Test/memory.png new file mode 100644 index 0000000..2ff9f0a Binary files /dev/null and b/07_Operating_System/04_Memory_Test/memory.png differ diff --git a/07_Operating_System/05_Array_Test/Array.jack b/07_Operating_System/05_Array_Test/Array.jack new file mode 120000 index 0000000..3b12439 --- /dev/null +++ b/07_Operating_System/05_Array_Test/Array.jack @@ -0,0 +1 @@ +../Array.jack \ No newline at end of file diff --git a/07_Operating_System/05_Array_Test/ArrayTest.cmp b/07_Operating_System/05_Array_Test/ArrayTest.cmp new file mode 100644 index 0000000..d1a9798 --- /dev/null +++ b/07_Operating_System/05_Array_Test/ArrayTest.cmp @@ -0,0 +1,2 @@ +|RAM[8000]|RAM[8001]|RAM[8002]|RAM[8003]| +| 222 | 122 | 100 | 10 | diff --git a/07_Operating_System/05_Array_Test/ArrayTest.tst b/07_Operating_System/05_Array_Test/ArrayTest.tst new file mode 100644 index 0000000..89934b9 --- /dev/null +++ b/07_Operating_System/05_Array_Test/ArrayTest.tst @@ -0,0 +1,15 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/12/ArrayTest/ArrayTest.tst + +load, +output-file ArrayTest.out, +compare-to ArrayTest.cmp, +output-list RAM[8000]%D2.6.1 RAM[8001]%D2.6.1 RAM[8002]%D2.6.1 RAM[8003]%D2.6.1; + +repeat 1000000 { + vmstep; +} + +output; diff --git a/07_Operating_System/05_Array_Test/GPIO.jack b/07_Operating_System/05_Array_Test/GPIO.jack new file mode 120000 index 0000000..4583844 --- /dev/null +++ b/07_Operating_System/05_Array_Test/GPIO.jack @@ -0,0 +1 @@ +../GPIO.jack \ No newline at end of file diff --git a/07_Operating_System/05_Array_Test/Main.jack b/07_Operating_System/05_Array_Test/Main.jack new file mode 100644 index 0000000..928818d --- /dev/null +++ b/07_Operating_System/05_Array_Test/Main.jack @@ -0,0 +1,40 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/12/ArrayTest/Main.jack + +/** Test program for the OS Array class. */ +class Main { + + /** Performs several Array manipulations. */ + function void main() { + var Array r; // stores test results + var Array a, b, c; + + let r = 4107; + + let a = Array.new(3); + let a[2] = 222; + let r[0] = a[2]; // RAM[4107] = 222 + + let b = Array.new(3); + let b[1] = a[2] - 100; + let r[1] = b[1]; // RAM[4108] = 122 + + let c = Array.new(500); + let c[499] = a[2] - b[1]; + let r[2] = c[499]; // RAM[4109] = 100 + + do a.dispose(); + do b.dispose(); + + let b = Array.new(3); + let b[0] = c[499] - 90; + let r[3] = b[0]; // RAM[4110] = 10 + + do c.dispose(); + do b.dispose(); + + return; + } +} diff --git a/07_Operating_System/05_Array_Test/Makefile b/07_Operating_System/05_Array_Test/Makefile new file mode 100644 index 0000000..29614ad --- /dev/null +++ b/07_Operating_System/05_Array_Test/Makefile @@ -0,0 +1,18 @@ +all: jack vm asm bin sim + +jack: + ../../tools/JackCompiler/JackCompiler.pyc ./ +vm: + ../../tools/VMTranslator/VMTranslator.pyc ./ +asm: + ../../tools/Assembler/assembler.pyc out.asm +bin: + ../../tools/AsciiToBin.py out.hack +sim: + cp out.hack ../00_HACK/ROM.hack +upload: + iceprogduino -o 64k -w out.bin +clean: + rm -f *.vm *.asm *.hack *.bin *~ + +.PHONY: all clean diff --git a/07_Operating_System/05_Array_Test/Memory.jack b/07_Operating_System/05_Array_Test/Memory.jack new file mode 120000 index 0000000..e8b63fa --- /dev/null +++ b/07_Operating_System/05_Array_Test/Memory.jack @@ -0,0 +1 @@ +../Memory.jack \ No newline at end of file diff --git a/07_Operating_System/05_Array_Test/Readme.md b/07_Operating_System/05_Array_Test/Readme.md new file mode 100644 index 0000000..bb042d1 --- /dev/null +++ b/07_Operating_System/05_Array_Test/Readme.md @@ -0,0 +1,24 @@ +## Array.jack + +Represents an array. +In the Jack language, arrays are instances of the Array class. Once declared, the array entries can be accessed using the usual syntax arr[i]. Each array entry can hold a primitive data type as well as any object type. Different array entries can have different data types. + +*** + +### Project + +* Implement `Array.jack` + +* Test in simulation: + + ``` + $ cd 05_Array_Test + $ make + $ cd ../00_HACK + $ apio clean + $ apio sim + ``` + +* Check the content of special function register DEBUG0--DEBUG4. + + ![](array.png) diff --git a/07_Operating_System/05_Array_Test/Readme.md.backup b/07_Operating_System/05_Array_Test/Readme.md.backup new file mode 100644 index 0000000..8980492 --- /dev/null +++ b/07_Operating_System/05_Array_Test/Readme.md.backup @@ -0,0 +1,31 @@ +## Array.jack +Represents an array. +In the Jack language, arrays are instances of the Array class. Once declared, the array entries can be accessed using the usual syntax arr[i]. Each array entry can hold a primitive data type as well as any object type. Different array entries can have different data types. + +### function Array new(int size) +Constructs a new Array of the given size. + + if (~(size>0)){ + do Sys.error(3); + } + return Memory.alloc(size); + } + + /** Disposes this array. */ + method void dispose() { + do Memory.deAlloc(this); +*** +## Project +* Implement `Array.jack` +* Test in simulation: +``` +$ cd 05_Array_Test +$ make +$ cd ../00_HACK +$ apio clean +$ apio sim +``` + +* Check the content of special function register DEBUG0--DEBUG4. + +![](array.png) diff --git a/07_Operating_System/05_Array_Test/Sys.jack b/07_Operating_System/05_Array_Test/Sys.jack new file mode 120000 index 0000000..4b50826 --- /dev/null +++ b/07_Operating_System/05_Array_Test/Sys.jack @@ -0,0 +1 @@ +../Sys.jack \ No newline at end of file diff --git a/07_Operating_System/05_Array_Test/UART.jack b/07_Operating_System/05_Array_Test/UART.jack new file mode 120000 index 0000000..e7e97fa --- /dev/null +++ b/07_Operating_System/05_Array_Test/UART.jack @@ -0,0 +1 @@ +../UART.jack \ No newline at end of file diff --git a/07_Operating_System/05_Array_Test/array.png b/07_Operating_System/05_Array_Test/array.png new file mode 100644 index 0000000..f888edc Binary files /dev/null and b/07_Operating_System/05_Array_Test/array.png differ diff --git a/07_Operating_System/06_Math_Test/Array.jack b/07_Operating_System/06_Math_Test/Array.jack new file mode 120000 index 0000000..3b12439 --- /dev/null +++ b/07_Operating_System/06_Math_Test/Array.jack @@ -0,0 +1 @@ +../Array.jack \ No newline at end of file diff --git a/07_Operating_System/06_Math_Test/GPIO.jack b/07_Operating_System/06_Math_Test/GPIO.jack new file mode 120000 index 0000000..4583844 --- /dev/null +++ b/07_Operating_System/06_Math_Test/GPIO.jack @@ -0,0 +1 @@ +../GPIO.jack \ No newline at end of file diff --git a/07_Operating_System/06_Math_Test/Main.jack b/07_Operating_System/06_Math_Test/Main.jack new file mode 100644 index 0000000..fe21bb1 --- /dev/null +++ b/07_Operating_System/06_Math_Test/Main.jack @@ -0,0 +1,35 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/12/MathTest/Main.jack + +/** Test program for the OS Math class. */ +class Main { + + /** Performs various mathematical operations, using calls to the Math class methods. */ + function void main() { + var Array r; // stores the test results; + + let r = 4107; + + let r[0] = 2 * 3; // 6 + let r[1] = r[0] * (-30); // 6 * (-30) = -180 + let r[2] = r[1] * 100; // (-180) * 100 = -18000 + let r[3] = 1 * r[2]; // 1 * (-18000) = -18000 + let r[4] = r[3] * 0; // 0 + + let r[0] = 9 / 3; // 3 + let r[1] = (-18000) / 6; // -3000 + let r[2] = 32766 / (-32767); // 0 + + let r[3] = Math.sqrt(9); // 3 + let r[4] = Math.sqrt(32767); // 181 + + let r[0] = Math.min(345, 123); // 123 + let r[1] = Math.max(123, -345); // 123 + let r[2] = Math.abs(27); // 27 + let r[3] = Math.abs(-32767); // 32767 + + return; + } +} diff --git a/07_Operating_System/06_Math_Test/Makefile b/07_Operating_System/06_Math_Test/Makefile new file mode 100644 index 0000000..29614ad --- /dev/null +++ b/07_Operating_System/06_Math_Test/Makefile @@ -0,0 +1,18 @@ +all: jack vm asm bin sim + +jack: + ../../tools/JackCompiler/JackCompiler.pyc ./ +vm: + ../../tools/VMTranslator/VMTranslator.pyc ./ +asm: + ../../tools/Assembler/assembler.pyc out.asm +bin: + ../../tools/AsciiToBin.py out.hack +sim: + cp out.hack ../00_HACK/ROM.hack +upload: + iceprogduino -o 64k -w out.bin +clean: + rm -f *.vm *.asm *.hack *.bin *~ + +.PHONY: all clean diff --git a/07_Operating_System/06_Math_Test/Math.jack b/07_Operating_System/06_Math_Test/Math.jack new file mode 120000 index 0000000..a22c6f5 --- /dev/null +++ b/07_Operating_System/06_Math_Test/Math.jack @@ -0,0 +1 @@ +../Math.jack \ No newline at end of file diff --git a/07_Operating_System/06_Math_Test/MathTest.cmp b/07_Operating_System/06_Math_Test/MathTest.cmp new file mode 100644 index 0000000..703c1be --- /dev/null +++ b/07_Operating_System/06_Math_Test/MathTest.cmp @@ -0,0 +1,2 @@ +|RAM[8000]|RAM[8001]|RAM[8002]|RAM[8003]|RAM[8004]|RAM[8005]|RAM[8006]|RAM[8007]|RAM[8008]|RAM[8009]|RAM[8010]|RAM[8011]|RAM[8012]|RAM[8013]| +| 6 | -180 | -18000 | -18000 | 0 | 3 | -3000 | 0 | 3 | 181 | 123 | 123 | 27 | 32767 | diff --git a/07_Operating_System/06_Math_Test/MathTest.tst b/07_Operating_System/06_Math_Test/MathTest.tst new file mode 100644 index 0000000..127dbb4 --- /dev/null +++ b/07_Operating_System/06_Math_Test/MathTest.tst @@ -0,0 +1,15 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/12/MathTest/MathTest.tst + +load, +output-file MathTest.out, +compare-to MathTest.cmp, +output-list RAM[8000]%D2.6.1 RAM[8001]%D2.6.1 RAM[8002]%D2.6.1 RAM[8003]%D2.6.1 RAM[8004]%D2.6.1 RAM[8005]%D2.6.1 RAM[8006]%D2.6.1 RAM[8007]%D2.6.1 RAM[8008]%D2.6.1 RAM[8009]%D2.6.1 RAM[8010]%D2.6.1 RAM[8011]%D2.6.1 RAM[8012]%D2.6.1 RAM[8013]%D2.6.1; + +repeat 1000000 { + vmstep; +} + +output; diff --git a/07_Operating_System/06_Math_Test/Memory.jack b/07_Operating_System/06_Math_Test/Memory.jack new file mode 120000 index 0000000..e8b63fa --- /dev/null +++ b/07_Operating_System/06_Math_Test/Memory.jack @@ -0,0 +1 @@ +../Memory.jack \ No newline at end of file diff --git a/07_Operating_System/06_Math_Test/Readme.md b/07_Operating_System/06_Math_Test/Readme.md new file mode 100644 index 0000000..0c098eb --- /dev/null +++ b/07_Operating_System/06_Math_Test/Readme.md @@ -0,0 +1,24 @@ +## Math_Test + +A library of commonly used mathematical functions. + +**Note:** Jack compilers implement multiplication and division using OS method calls. + +*** + +### Project + +* Implement `Math.jack` + +* Test in simulation: + + ``` + $ cd 00_Math_Test + $ make + $ cd ../00_HACK + $ apio clean + $ apio sim + ``` + +* Compare the content of special function register DEBUG0--DEBUG4. + ![](math.png) diff --git a/07_Operating_System/06_Math_Test/Readme.md.backup b/07_Operating_System/06_Math_Test/Readme.md.backup new file mode 100644 index 0000000..39974f6 --- /dev/null +++ b/07_Operating_System/06_Math_Test/Readme.md.backup @@ -0,0 +1,33 @@ +## Math_Test +A library of commonly used mathematical functions. + +**Note:** Jack compilers implement multiplication and division using OS method calls. + +### function void init() { +Initializes the library. +### function int abs(int x) +Returns the absolute value of x. +### function int multiply(int x, int y) +Returns the product of x and y. When a Jack compiler detects the multiplication operator `"*"` in the program's code, it handles it by invoking this method. In other words, the Jack expressions x*y and multiply(x,y) return the same value. +### function int divide(int x, int y) +Returns the integer part of x/y. When a Jack compiler detects the multiplication operator `"/"` in the program's code, it handles it by invoking this method. In other words, the Jack expressions x/y and divide(x,y) return the same value. +### function int sqrt(int x) +Returns the integer part of the square root of x. +### function int max(int a, int b) +Returns the greater number. +### function int min(int a, int b) +Returns the smaller number. +*** +## Project +* Implement `Math.jack` +* Test in simulation: +``` +$ cd 00_Math_Test +$ make +$ cd ../00_HACK +$ apio clean +$ apio sim +``` + +* Compare the content of special function register DEBUG0--DEBUG4. +![](math.png) diff --git a/07_Operating_System/06_Math_Test/Sys.jack b/07_Operating_System/06_Math_Test/Sys.jack new file mode 120000 index 0000000..4b50826 --- /dev/null +++ b/07_Operating_System/06_Math_Test/Sys.jack @@ -0,0 +1 @@ +../Sys.jack \ No newline at end of file diff --git a/07_Operating_System/06_Math_Test/UART.jack b/07_Operating_System/06_Math_Test/UART.jack new file mode 120000 index 0000000..e7e97fa --- /dev/null +++ b/07_Operating_System/06_Math_Test/UART.jack @@ -0,0 +1 @@ +../UART.jack \ No newline at end of file diff --git a/07_Operating_System/06_Math_Test/math.png b/07_Operating_System/06_Math_Test/math.png new file mode 100644 index 0000000..752c2f2 Binary files /dev/null and b/07_Operating_System/06_Math_Test/math.png differ diff --git a/07_Operating_System/07_String_Test/Array.jack b/07_Operating_System/07_String_Test/Array.jack new file mode 120000 index 0000000..3b12439 --- /dev/null +++ b/07_Operating_System/07_String_Test/Array.jack @@ -0,0 +1 @@ +../Array.jack \ No newline at end of file diff --git a/07_Operating_System/07_String_Test/GPIO.jack b/07_Operating_System/07_String_Test/GPIO.jack new file mode 120000 index 0000000..4583844 --- /dev/null +++ b/07_Operating_System/07_String_Test/GPIO.jack @@ -0,0 +1 @@ +../GPIO.jack \ No newline at end of file diff --git a/07_Operating_System/07_String_Test/Main.jack b/07_Operating_System/07_String_Test/Main.jack new file mode 100644 index 0000000..62d3831 --- /dev/null +++ b/07_Operating_System/07_String_Test/Main.jack @@ -0,0 +1,83 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/12/StringTest/Main.jack + +/** Test program for the OS String class. */ +class Main { + + /** Performs various string manipulations and displays their results. */ + function void main() { + var String s; + var String i; + + let s = String.new(0); // a zero-capacity string should be supported + do s.dispose(); + + let s = String.new(6); // capacity 6, make sure that length 5 is displayed + let s = s.appendChar(97); + let s = s.appendChar(98); + let s = s.appendChar(99); + let s = s.appendChar(100); + let s = s.appendChar(101); + do StdIO.printString("new,appendChar: "); + do StdIO.printString(s); // new, appendChar: abcde + do StdIO.println(); + + let i = String.new(6); + do i.setInt(12345); + do StdIO.printString("setInt: "); + do StdIO.printString(i); // setInt: 12345 + do StdIO.println(); + + let i = String.new(6); + do i.setInt(-32767); + do StdIO.printString("setInt: "); + do StdIO.printString(i); // setInt: -32767 + do StdIO.println(); + + let s="abcde"; + do StdIO.printString("length: "); + do StdIO.printInt(s.length()); // length: 5 + do StdIO.println(); + + do StdIO.printString("charAt[2]: "); + do StdIO.printInt(s.charAt(2)); // charAt[2]: 99 + do StdIO.println(); + + do s.setCharAt(2, 45); + do StdIO.printString("setCharAt(2,'-'): "); + do StdIO.printString(s); // setCharAt(2,'-'): ab-de + do StdIO.println(); + + let s="abcde"; + do s.eraseLastChar(); + do StdIO.printString("eraseLastChar: "); + do StdIO.printString(s); // eraseLastChar: ab-d + do StdIO.println(); + + let s = "456"; + do StdIO.printString("intValue: "); + do StdIO.printInt(s.intValue()); // intValue: 456 + do StdIO.println(); + + let s = "-32123"; + do StdIO.printString("intValue: "); + do StdIO.printInt(s.intValue()); // intValue: -32123 + do StdIO.println(); + + do StdIO.printString("backSpace: "); + do StdIO.printInt(String.backSpace()); // backSpace: 129 + do StdIO.println(); + + do StdIO.printString("doubleQuote: "); + do StdIO.printInt(String.doubleQuote());// doubleQuote: 34 + do StdIO.println(); + + do StdIO.printString("newLine: "); + do StdIO.printInt(String.newLine()); // newLine: 128 + do StdIO.println(); + + return; + } +} diff --git a/07_Operating_System/07_String_Test/Makefile b/07_Operating_System/07_String_Test/Makefile new file mode 100644 index 0000000..29614ad --- /dev/null +++ b/07_Operating_System/07_String_Test/Makefile @@ -0,0 +1,18 @@ +all: jack vm asm bin sim + +jack: + ../../tools/JackCompiler/JackCompiler.pyc ./ +vm: + ../../tools/VMTranslator/VMTranslator.pyc ./ +asm: + ../../tools/Assembler/assembler.pyc out.asm +bin: + ../../tools/AsciiToBin.py out.hack +sim: + cp out.hack ../00_HACK/ROM.hack +upload: + iceprogduino -o 64k -w out.bin +clean: + rm -f *.vm *.asm *.hack *.bin *~ + +.PHONY: all clean diff --git a/07_Operating_System/07_String_Test/Math.jack b/07_Operating_System/07_String_Test/Math.jack new file mode 120000 index 0000000..a22c6f5 --- /dev/null +++ b/07_Operating_System/07_String_Test/Math.jack @@ -0,0 +1 @@ +../Math.jack \ No newline at end of file diff --git a/07_Operating_System/07_String_Test/Memory.jack b/07_Operating_System/07_String_Test/Memory.jack new file mode 120000 index 0000000..e8b63fa --- /dev/null +++ b/07_Operating_System/07_String_Test/Memory.jack @@ -0,0 +1 @@ +../Memory.jack \ No newline at end of file diff --git a/07_Operating_System/07_String_Test/Readme.md b/07_Operating_System/07_String_Test/Readme.md new file mode 100644 index 0000000..4c7e7c8 --- /dev/null +++ b/07_Operating_System/07_String_Test/Readme.md @@ -0,0 +1,38 @@ +## String.jack + +Represents character strings. In addition for constructing and disposing strings, the class features methods for getting and setting individual characters of the string, for erasing the string's last character, for appending a character to the string's end, and more typical string-oriented operations. + +*** + +### Project + +* Implement `String.jack` and at least the function `StdIO.printString(String s)` + +* Test by running `String_Test`, which performs several String operation and outputs them to StdIO (UART) + + **Hint:** Use the debug register to show which caracters are transmitted over `UartTX`. Add the following code in function UART.writeChar(): + + ``` + do Memory.Poke(4107,data) + ``` + + ![](string.png) + +* Run String_Test in real hardware on iCE40HX1K-EVB using a terminal program connected to UART. + +* Compare your terminal output with: + + ``` + new,appendChar: abcde + setInt: 12345 + setInt: -32767 + length: 5 + charAt[2]: 99 + setCharAt(2,'-'): ab-de + eraseLastChar: abcd + intValue: 456 + intValue: -32123 + backSpace: 129 + doubleQuote: 34 + newLine: 128 + ``` \ No newline at end of file diff --git a/07_Operating_System/07_String_Test/Readme.md.backup b/07_Operating_System/07_String_Test/Readme.md.backup new file mode 100644 index 0000000..9e4d36c --- /dev/null +++ b/07_Operating_System/07_String_Test/Readme.md.backup @@ -0,0 +1,54 @@ +## String.jack +Represents character strings. In addition for constructing and disposing strings, the class features methods for getting and setting individual characters of the string, for erasing the string's last character, for appending a character to the string's end, and more typical string-oriented operations. +### constructor String new(int maxLength) +constructs a new empty string with a maximum length of maxLength and initial length of 0. +### method void dispose() +Disposes this string. +### method int length() +Returns the current length of this string. +### method char charAt(int j) +Returns the character at the j-th location of this string. +### method String appendChar(char c) +Appends c to this string's end and returns this string. +### method void eraseLastChar() +Erases the last character from this string. +### method int intValue() +Returns the integer value of this string until a non-digit character is detected. +### method void setInt(int val) +Sets this string to hold a representation of the given value. +### function char newLine() +Returns the new line character. +### function char backSpace() +Returns the backspace character. +### function char doubleQuote() +Returns the double quote (`"`) character. + +*** +## Project +* Implement `String.jack` and at least the function `StdIO.printString(String s)` +* Test by running String_Test, which performs several String operation and outputs them to StdIO (UART) + +**Hint:** Use the debug register to show which caracters are transmitted over UART_TX. Add the following code in function UART.writeChar(): +``` +do Memory.Poke(4107,data) +``` + +![](string.png) + +* Run String_Test in real hardware on iCE40HX1K-EVB using a terminal program connected to UART. + +* Compare your terminal output with: +``` +new,appendChar: abcde +setInt: 12345 +setInt: -32767 +length: 5 +charAt[2]: 99 +setCharAt(2,'-'): ab-de +eraseLastChar: abcd +intValue: 456 +intValue: -32123 +backSpace: 129 +doubleQuote: 34 +newLine: 128 +``` \ No newline at end of file diff --git a/07_Operating_System/07_String_Test/StdIO.jack b/07_Operating_System/07_String_Test/StdIO.jack new file mode 120000 index 0000000..7883f6e --- /dev/null +++ b/07_Operating_System/07_String_Test/StdIO.jack @@ -0,0 +1 @@ +../StdIO.jack \ No newline at end of file diff --git a/07_Operating_System/07_String_Test/String.jack b/07_Operating_System/07_String_Test/String.jack new file mode 120000 index 0000000..6b71bed --- /dev/null +++ b/07_Operating_System/07_String_Test/String.jack @@ -0,0 +1 @@ +../String.jack \ No newline at end of file diff --git a/07_Operating_System/07_String_Test/StringTestOutput.gif b/07_Operating_System/07_String_Test/StringTestOutput.gif new file mode 100644 index 0000000..5c2932c Binary files /dev/null and b/07_Operating_System/07_String_Test/StringTestOutput.gif differ diff --git a/07_Operating_System/07_String_Test/Sys.jack b/07_Operating_System/07_String_Test/Sys.jack new file mode 120000 index 0000000..4b50826 --- /dev/null +++ b/07_Operating_System/07_String_Test/Sys.jack @@ -0,0 +1 @@ +../Sys.jack \ No newline at end of file diff --git a/07_Operating_System/07_String_Test/UART.jack b/07_Operating_System/07_String_Test/UART.jack new file mode 120000 index 0000000..e7e97fa --- /dev/null +++ b/07_Operating_System/07_String_Test/UART.jack @@ -0,0 +1 @@ +../UART.jack \ No newline at end of file diff --git a/07_Operating_System/07_String_Test/string.png b/07_Operating_System/07_String_Test/string.png new file mode 100644 index 0000000..a830e27 Binary files /dev/null and b/07_Operating_System/07_String_Test/string.png differ diff --git a/07_Operating_System/08_StdIO_Test/Array.jack b/07_Operating_System/08_StdIO_Test/Array.jack new file mode 120000 index 0000000..3b12439 --- /dev/null +++ b/07_Operating_System/08_StdIO_Test/Array.jack @@ -0,0 +1 @@ +../Array.jack \ No newline at end of file diff --git a/07_Operating_System/08_StdIO_Test/GPIO.jack b/07_Operating_System/08_StdIO_Test/GPIO.jack new file mode 120000 index 0000000..4583844 --- /dev/null +++ b/07_Operating_System/08_StdIO_Test/GPIO.jack @@ -0,0 +1 @@ +../GPIO.jack \ No newline at end of file diff --git a/07_Operating_System/08_StdIO_Test/Main.jack b/07_Operating_System/08_StdIO_Test/Main.jack new file mode 100644 index 0000000..781224a --- /dev/null +++ b/07_Operating_System/08_StdIO_Test/Main.jack @@ -0,0 +1,70 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/12/KeyboardTest/Main.jack + +/** Test program for the OS Keyboard class. */ +class Main { + + /** Gets input from the user and verifies its contents. */ + function void main() { + var char c, key; + var String s; + var int i; + var boolean ok; + + do StdIO.printString("StdIO test:"); + do StdIO.println(); + + let ok = false; + while (~ok) { + do StdIO.printString("Please press the number '3': "); + let c = UART.readChar(); + + do StdIO.println(); + + if (c = 51) { + do StdIO.printString("ok"); + do StdIO.println(); + let ok = true; + } + } + + let ok = false; + do StdIO.printString("readLine test:"); + do StdIO.println(); + do StdIO.printString("(Verify echo and usage of 'backspace')"); + do StdIO.println(); + while (~ok) { + let s = StdIO.readLine("Please type 'JACK' and press enter: "); + + if (s.length() = 4) { + if ((s.charAt(0) = 74) & (s.charAt(1) = 65) & (s.charAt(2) = 67) & (s.charAt(3) = 75)) { + do StdIO.printString("ok"); + do StdIO.println(); + let ok = true; + } + } + } + + let ok = false; + do StdIO.printString("readInt test:"); + do StdIO.println(); + do StdIO.printString("(Verify echo and usage of 'backspace')"); + do StdIO.println(); + while (~ok) { + let i = StdIO.readInt("Please type '-32123' and press enter: "); + + if (i = (-32123)) { + do StdIO.printString("ok"); + do StdIO.println(); + let ok = true; + } + } + + do StdIO.println(); + do StdIO.printString("Test completed successfully"); + + return; + } +} diff --git a/07_Operating_System/08_StdIO_Test/Makefile b/07_Operating_System/08_StdIO_Test/Makefile new file mode 100644 index 0000000..29614ad --- /dev/null +++ b/07_Operating_System/08_StdIO_Test/Makefile @@ -0,0 +1,18 @@ +all: jack vm asm bin sim + +jack: + ../../tools/JackCompiler/JackCompiler.pyc ./ +vm: + ../../tools/VMTranslator/VMTranslator.pyc ./ +asm: + ../../tools/Assembler/assembler.pyc out.asm +bin: + ../../tools/AsciiToBin.py out.hack +sim: + cp out.hack ../00_HACK/ROM.hack +upload: + iceprogduino -o 64k -w out.bin +clean: + rm -f *.vm *.asm *.hack *.bin *~ + +.PHONY: all clean diff --git a/07_Operating_System/08_StdIO_Test/Math.jack b/07_Operating_System/08_StdIO_Test/Math.jack new file mode 120000 index 0000000..a22c6f5 --- /dev/null +++ b/07_Operating_System/08_StdIO_Test/Math.jack @@ -0,0 +1 @@ +../Math.jack \ No newline at end of file diff --git a/07_Operating_System/08_StdIO_Test/Memory.jack b/07_Operating_System/08_StdIO_Test/Memory.jack new file mode 120000 index 0000000..e8b63fa --- /dev/null +++ b/07_Operating_System/08_StdIO_Test/Memory.jack @@ -0,0 +1 @@ +../Memory.jack \ No newline at end of file diff --git a/07_Operating_System/08_StdIO_Test/Readme.md b/07_Operating_System/08_StdIO_Test/Readme.md new file mode 100644 index 0000000..40dfa2c --- /dev/null +++ b/07_Operating_System/08_StdIO_Test/Readme.md @@ -0,0 +1,29 @@ +## StdIO.jack + +A library of functions for text based input and output over UART. + +*** + +### Project + +* Implement `StdIO.jack`. + +* Run `StdIO_Test` in real hardware on iCE40HX1K-EVB using a terminal program connected to UART. + +* Compare your terminal output with: + + ``` + StdIO test: + Please press the number '3': + ok + readLine test: + (Verify echo and usage of 'backspace') + Please type 'JACK' and press enter: JACK + ok + readInt test: + (Verify echo and usage of 'backspace') + Please type '-32123' and press enter: -32123 + ok + + Test completed successfully + ``` \ No newline at end of file diff --git a/07_Operating_System/08_StdIO_Test/Readme.md.backup b/07_Operating_System/08_StdIO_Test/Readme.md.backup new file mode 100644 index 0000000..ac56045 --- /dev/null +++ b/07_Operating_System/08_StdIO_Test/Readme.md.backup @@ -0,0 +1,35 @@ +## StdIO.jack +A library of functions for textual input and output over UART. + +### function void printString(String s) +Print the String s to UART_TX and disposes the String s. +### function void printInt(int i) +Prints the decimal representation of i to UART_TX +### function void println() +Prints the new line character to UART_TX +### function int readInt(String message) +Displays the message on the screen, disposes the message, reads from UART_RX the entered text until a newline character is detected, echoes the text to UART_TX, and returns its integer value (until the first non-digit character in the entered text is detected). Also handles user backspaces. +### function String readLine(String message) +Sends the message to UART_TX, reads from UART_RX the entered text until a newline character is detected, echoes the text to the UART_TX, and returns its value. Also handles user backspaces. +*** +## Project +* Implement `StdIO.jack`. +* Run String_Test in real hardware on iCE40HX1K-EVB using a terminal program connected to UART. + +* Compare your terminal output with: + +``` +StdIO test: +Please press the number '3': +ok +readLine test: +(Verify echo and usage of 'backspace') +Please type 'JACK' and press enter: JACK +ok +readInt test: +(Verify echo and usage of 'backspace') +Please type '-32123' and press enter: -32123 +ok + +Test completed successfully +``` \ No newline at end of file diff --git a/07_Operating_System/08_StdIO_Test/StdIO.jack b/07_Operating_System/08_StdIO_Test/StdIO.jack new file mode 120000 index 0000000..7883f6e --- /dev/null +++ b/07_Operating_System/08_StdIO_Test/StdIO.jack @@ -0,0 +1 @@ +../StdIO.jack \ No newline at end of file diff --git a/07_Operating_System/08_StdIO_Test/String.jack b/07_Operating_System/08_StdIO_Test/String.jack new file mode 120000 index 0000000..6b71bed --- /dev/null +++ b/07_Operating_System/08_StdIO_Test/String.jack @@ -0,0 +1 @@ +../String.jack \ No newline at end of file diff --git a/07_Operating_System/08_StdIO_Test/Sys.jack b/07_Operating_System/08_StdIO_Test/Sys.jack new file mode 120000 index 0000000..4b50826 --- /dev/null +++ b/07_Operating_System/08_StdIO_Test/Sys.jack @@ -0,0 +1 @@ +../Sys.jack \ No newline at end of file diff --git a/07_Operating_System/08_StdIO_Test/UART.jack b/07_Operating_System/08_StdIO_Test/UART.jack new file mode 120000 index 0000000..e7e97fa --- /dev/null +++ b/07_Operating_System/08_StdIO_Test/UART.jack @@ -0,0 +1 @@ +../UART.jack \ No newline at end of file diff --git a/07_Operating_System/09_Screen_Test/Array.jack b/07_Operating_System/09_Screen_Test/Array.jack new file mode 120000 index 0000000..3b12439 --- /dev/null +++ b/07_Operating_System/09_Screen_Test/Array.jack @@ -0,0 +1 @@ +../Array.jack \ No newline at end of file diff --git a/07_Operating_System/09_Screen_Test/GPIO.jack b/07_Operating_System/09_Screen_Test/GPIO.jack new file mode 120000 index 0000000..4583844 --- /dev/null +++ b/07_Operating_System/09_Screen_Test/GPIO.jack @@ -0,0 +1 @@ +../GPIO.jack \ No newline at end of file diff --git a/07_Operating_System/09_Screen_Test/Main.jack b/07_Operating_System/09_Screen_Test/Main.jack new file mode 100644 index 0000000..1679b1d --- /dev/null +++ b/07_Operating_System/09_Screen_Test/Main.jack @@ -0,0 +1,94 @@ +class Main { + + function void main() { + var int x; + var int vx; + var Array map; + do Screen.setPenColor(Screen.BLACK()); + do Screen.drawRectangle(5,5,35,35); + do Screen.setPenColor(Screen.NAVY()); + do Screen.drawRectangle(45,5,75,35); + do Screen.setPenColor(Screen.BLUE()); + do Screen.drawRectangle(85,5,115,35); + do Screen.setPenColor(Screen.GREEN()); + do Screen.drawRectangle(125,5,155,35); + do Screen.setPenColor(Screen.CYAN()); + do Screen.drawRectangle(165,5,195,35); + do Screen.setPenColor(Screen.MAROON()); + do Screen.drawRectangle(205,5,235,35); + do Screen.setPenColor(Screen.PURPLE()); + do Screen.drawRectangle(5,45,35,75); + do Screen.setPenColor(Screen.OLIVE()); + do Screen.drawRectangle(45,45,75,75); + do Screen.setPenColor(Screen.MAGENTA()); + do Screen.drawRectangle(85,45,115,75); + do Screen.setPenColor(Screen.DARKGREY()); + do Screen.drawRectangle(125,45,155,75); + do Screen.setPenColor(Screen.LIGHTGREY()); + do Screen.drawRectangle(165,45,195,75); + do Screen.setPenColor(Screen.RED()); + do Screen.drawRectangle(205,45,235,75); + do Screen.setPenColor(Screen.YELLOW()); + do Screen.drawRectangle(5,85,35,115); + do Screen.setPenColor(Screen.ORANGE()); + do Screen.drawRectangle(45,85,75,115); + do Screen.setPenColor(Screen.LIME()); + do Screen.drawRectangle(85,85,115,115); + do Screen.setPenColor(Screen.TEAL()); + do Screen.drawRectangle(125,85,155,115); + + do Screen.setPenColor(Screen.BLACK()); + + let x=0; + while (x<240){ + do Screen.drawPixel(x,150); + let x=x+2; + } + do Screen.drawLine(120,200,170,200); + do Screen.drawLine(120,200,170,250); + do Screen.drawLine(120,200,120,250); + do Screen.drawLine(120,200,70,250); + do Screen.drawLine(120,200,70,200); + do Screen.drawLine(120,200,70,150); + do Screen.drawLine(120,200,120,150); + do Screen.drawLine(120,200,170,150); + + let map = Array.new(16); + let map[0]=768; + let map[1]=768; + let map[2]=896; + let map[3]=896; + let map[4]=960; + let map[5]=960; + let map[6]=16352; + let map[7]=16352; + let map[8]=8176; + let map[9]=8176; + let map[10]=3840; + let map[11]=3840; + let map[12]=1792; + let map[13]=1792; + let map[14]=768; + let map[15]=768; + + do Screen.setPenColor(Screen.RED()); + do Screen.drawBitMap(112, 260, 127, 275,map); + let x=120; + let vx=10; + while (true){ + do Sys.wait(100); + do Screen.setPenColor(Screen.WHITE()); + do Screen.drawCircle(x,300,5); + let x=x+vx; + do Screen.setPenColor(Screen.RED()); + do Screen.drawCircle(x,300,5); + if (x>220) { + let vx=-10; + } + if (x<20) { + let vx=10; + } + } + return; + } +} diff --git a/07_Operating_System/09_Screen_Test/Makefile b/07_Operating_System/09_Screen_Test/Makefile new file mode 100644 index 0000000..29614ad --- /dev/null +++ b/07_Operating_System/09_Screen_Test/Makefile @@ -0,0 +1,18 @@ +all: jack vm asm bin sim + +jack: + ../../tools/JackCompiler/JackCompiler.pyc ./ +vm: + ../../tools/VMTranslator/VMTranslator.pyc ./ +asm: + ../../tools/Assembler/assembler.pyc out.asm +bin: + ../../tools/AsciiToBin.py out.hack +sim: + cp out.hack ../00_HACK/ROM.hack +upload: + iceprogduino -o 64k -w out.bin +clean: + rm -f *.vm *.asm *.hack *.bin *~ + +.PHONY: all clean diff --git a/07_Operating_System/09_Screen_Test/Math.jack b/07_Operating_System/09_Screen_Test/Math.jack new file mode 120000 index 0000000..a22c6f5 --- /dev/null +++ b/07_Operating_System/09_Screen_Test/Math.jack @@ -0,0 +1 @@ +../Math.jack \ No newline at end of file diff --git a/07_Operating_System/09_Screen_Test/Memory.jack b/07_Operating_System/09_Screen_Test/Memory.jack new file mode 120000 index 0000000..e8b63fa --- /dev/null +++ b/07_Operating_System/09_Screen_Test/Memory.jack @@ -0,0 +1 @@ +../Memory.jack \ No newline at end of file diff --git a/07_Operating_System/09_Screen_Test/Readme.md b/07_Operating_System/09_Screen_Test/Readme.md new file mode 100644 index 0000000..d58708a --- /dev/null +++ b/07_Operating_System/09_Screen_Test/Readme.md @@ -0,0 +1,70 @@ +## Screen.jack + +A library of functions for displaying graphics on the screen. +The connected LCD physical screen consists of 320 rows (indexed 0..319, top to bottom) of 240 pixels each (indexed 0..239, left to right). The top left pixel on the screen is indexed (0,0). Every pixel can be set to a 16 bit color code composed of RGB-parts of 5 bit red, 6 bit green and 5 bit blue: `rrrrrggggggbbbbb`. + +### Special function register LCD + +The Screen is controlled by sending commands to special function register LCD, which connects to the ILI9341V controller on MOD-LCD2.8RTP. Every command is 8bit long with DCX=0 pulled low followed by any number (also none) of arguments, which are send with DCX=1 pushed high. All commands are described in the datasheet of [ILI9341V](../../doc/ILI9341V_v1.0.pdf). (h denote hexadecimal and d denote decimal notation). + +1. **Memory access control (36h)**: send 54d (DCX=0) followed by the argument 72d (with DCX=1) to get access to the memory of ILI9341V. +2. **COLMOD Pixel Format Set (3Ah)**: send 58d (DCX=0) followed by the argument 85d (DCX=1) to set the pixel format to rgb 16 bit. +3. **Sleep Out (11h)**: send 17d (DCX=0) and wait 500 ms to awake ILI9341V from sleep mode. +4. **Display ON (29h)**: send 41d (DCX=0) and wait 500 ms to switch the display on. + +After initialisation with commands 1.-4., the screen turns on showing a random pattern of RGB colors. To paint something on the screen, we must send the following three commands to LCD. + +5. **Colum addres set (2Ah)**: To set the x-range of the window into which to paint, send command 42d with DCX=0 followed by x1 (16 bit) and x2 (16 bit) with DCX=1. x1 and x2 must be in the range [0:239] with x2>=x1. +6. **Page address set (2Bh):** To set the y-range of the window into which to paint, send 43d with DCX=0 followed by value of y1 (16 bit) and value of y2 (16 bit) with DCX=1. y1 and y2 must be in the range [0:319] with y2>=y1. +7. **Memory write (2Ch):** To paint the pixel in the rectangle defined by (x1,y1)-(x2,y2) send 44d with DCX=0 followed by `w*h` 16 bit RGB values (DCX=1) of every individual pixel in the rectangle starting at top left and ending at bottom right. + +For convenience the commands 1.-7. are distributed to three functions of Screen.jack: + +### function void init(int addr) + +Initializes the LCD screen, by sending the commands 1.-4. to LCD. The LCD is memory mapped to the two memory addresses addr and addr+1 according to `06_IO_Devices/08_LCD`. + +### function void setWindow(int x1,int y1, int x2, int y2) + +Sets a rectangle window by sending commands 4.,5. and the command 7. without the arguments. (x1,y1) is the upper left corner and (x2,y2) is the lower right corner of the rectangle window. The next `w*h` calls of writeData16(int value) will paint the pixels in the rectangle according to the rgb values starting in the upper left corner and ending in the lower right corner. + +### function void writeData16(int color) + +Sends a 16 bit RGB value to paint the next pixel in the window defined by `setWindow(int,int,int,int)`. This procedure must be called `w*h` times to paint every pixel in the rectangle defined by `setAddrWindow(int,int,int,int)`. + +*** + +### Project + +* implement `Screen.jack` + +* Test in simulation + + ``` + $ cd 09_Screen_Test + $ make + $ cd ../00_HACK + $ apio clean + $ apio sim + ``` + + ![](lcd.png) + +* Check for the correct init sequence: + + * CSX is low starting from the first command. + * DCX is low while sending commands and high while sending data + * SDO shows the serial binary representation of the send command/data + * SCK shows 8 clocks cycles + +* Run Screen_Test in real hardware on iCE40HX1K-EVB with MOD-LCD2.8RTP connected as described in `06_IO_Devices/LCD`. + + ``` + $ cd 09_Screen_Test + $ make + $ make upload + ``` + +* Compare the pattern on the LCD with the following picture: + + ![](screen.png) \ No newline at end of file diff --git a/07_Operating_System/09_Screen_Test/Readme.md.backup b/07_Operating_System/09_Screen_Test/Readme.md.backup new file mode 100644 index 0000000..989ac1a --- /dev/null +++ b/07_Operating_System/09_Screen_Test/Readme.md.backup @@ -0,0 +1,57 @@ +## Screen.jack +A library of functions for displaying graphics on the screen. +The connected LCD physical screen consists of 320 rows (indexed 0..319, top to bottom) of 240 pixels each (indexed 0..239, left to right). The top left pixel on the screen is indexed (0,0). Every pixel can be set to a 16 bit color code divided into RGB-parts of 5 bit red, 6 bit green and 5 bit blue: `rrrrrggggggbbbbb`. + +### LCD +LCD is controlled by sending commands to LCD. Every command is 8bit long with CDX high followed by any number (also none) of arguments, which are send with CDX low. The needed commands are described in the datasheet of [ILI9341V](../../doc/ILI9341V_v1.0.pdf). (h denote hexadecimal and d denote decimal notation). + +1. **Memory access control (36h)**: send 54d (CDX high) followed by the argument 72d (with CDX low) to get access to the memory of ILI9341V. +2. **COLMOD Pixel Format Set (3Ah)**: send 58d (CDX high) followed by the argument 85d (CDX low) to set the pixel format to rgb 16 bit. +3. **Sleep Out (11h)**: send 17d (CDX high) and wait 500 ms to awake ILI9341V from sleep mode. +4. **Display ON (29h)**: send 41d (CDX high) and wait 500 ms to switch the display on. + +After initialisation with commands 1-4, the screen turns on showing a random pattern of RGB colors. To paint something on the screen, we must send the following three commands to LCD. + +5. **Colum addres set (2Ah)**: To set the x-range of the window into which to paint, send command 42d with CDX high followed by x1 (16 bit) and x2 (16 bit) with CDX low. x1 and x2 must be in the range [0:239] with x2>=x1. +6. **Page address set (2Bh):** To set the y-range of the window into which to paint, send 43d with CDX high followed by value of y1 (16 bit) and value of y2 (16 bit) with CDX low. y1 and y2 must be in the range [0:319] with y2>=y1. +7. **Memory write (2Ch):** To paint the pixel in the rectangle defined by (x1,y1)-(x2,y2) send 44d with CDX high followed by `w*h` 16 bit RGB values of every individual pixel in the rectangle starting at top left and ending at bottom right. + +For convenience the commands 1.-7. are distributed to three functions of Screen.jack: +### function void init(int addr) +Initializes the LCD screen, by sending the commands 1.-4. to LCD. The LCD is memory mapped to the two memory addresses addr and addr+1 according to `06_IO_Devices/08_LCD`. + +### function void setWindow(int x1,int y1, int x2, int y2) +Sets a rectangle window by sending commands 4.,5. and the command 7. without the arguments. (x1,y1) is the upper left corner and (x2,y2) is the lower right corof the rectangle with width and height. The next `w*h` calls of writeData16(int value) will paint the pixels in the rectangle according to the rgb values. + +### function void writeData16(int color) +Sends a 16 bit RGB value to paint the next pixel in the window defined by `setWindow(int,int,int,int)`. This procedure must be called `w*h` times to paint every pixel in the rectangle defined by `setAddrWindow(int,int,int,int)`. + +*** +### Project +* implement `Screen.jack` +* Test in simulation +``` +$ cd 09_Screen_Test +$ make +$ cd ../00_HACK +$ apio clean +$ apio sim +``` + +![](lcd.png) + +* Check for the correct init sequence: + * CSX is low starting from the first command. + * DCX is low while sending commands and high while sending data + * SDO shows the serial binary representation of the send command/data + * SCK shows 8 clocks cycles + +* Run Screen_Test in real hardware on iCE40HX1K-EVB with MOD-LCD2.8RTP connected as described in `06_IO_Devices/LCD`. +``` +$ cd 09_Screen_Test +$ make +$ make upload +``` +* Compare the pattern on the LCD with the following picture: + +![](screen.jpg) \ No newline at end of file diff --git a/07_Operating_System/09_Screen_Test/Screen.jack b/07_Operating_System/09_Screen_Test/Screen.jack new file mode 120000 index 0000000..5844b79 --- /dev/null +++ b/07_Operating_System/09_Screen_Test/Screen.jack @@ -0,0 +1 @@ +../Screen.jack \ No newline at end of file diff --git a/07_Operating_System/09_Screen_Test/StdIO.jack b/07_Operating_System/09_Screen_Test/StdIO.jack new file mode 120000 index 0000000..7883f6e --- /dev/null +++ b/07_Operating_System/09_Screen_Test/StdIO.jack @@ -0,0 +1 @@ +../StdIO.jack \ No newline at end of file diff --git a/07_Operating_System/09_Screen_Test/String.jack b/07_Operating_System/09_Screen_Test/String.jack new file mode 120000 index 0000000..6b71bed --- /dev/null +++ b/07_Operating_System/09_Screen_Test/String.jack @@ -0,0 +1 @@ +../String.jack \ No newline at end of file diff --git a/07_Operating_System/09_Screen_Test/Sys.jack b/07_Operating_System/09_Screen_Test/Sys.jack new file mode 120000 index 0000000..4b50826 --- /dev/null +++ b/07_Operating_System/09_Screen_Test/Sys.jack @@ -0,0 +1 @@ +../Sys.jack \ No newline at end of file diff --git a/07_Operating_System/09_Screen_Test/UART.jack b/07_Operating_System/09_Screen_Test/UART.jack new file mode 120000 index 0000000..e7e97fa --- /dev/null +++ b/07_Operating_System/09_Screen_Test/UART.jack @@ -0,0 +1 @@ +../UART.jack \ No newline at end of file diff --git a/07_Operating_System/09_Screen_Test/lcd.png b/07_Operating_System/09_Screen_Test/lcd.png new file mode 100644 index 0000000..d9ba42a Binary files /dev/null and b/07_Operating_System/09_Screen_Test/lcd.png differ diff --git a/07_Operating_System/09_Screen_Test/screen.png b/07_Operating_System/09_Screen_Test/screen.png new file mode 100644 index 0000000..6ea534f Binary files /dev/null and b/07_Operating_System/09_Screen_Test/screen.png differ diff --git a/07_Operating_System/10_Output_Test/Array.jack b/07_Operating_System/10_Output_Test/Array.jack new file mode 120000 index 0000000..3b12439 --- /dev/null +++ b/07_Operating_System/10_Output_Test/Array.jack @@ -0,0 +1 @@ +../Array.jack \ No newline at end of file diff --git a/07_Operating_System/10_Output_Test/GPIO.jack b/07_Operating_System/10_Output_Test/GPIO.jack new file mode 120000 index 0000000..4583844 --- /dev/null +++ b/07_Operating_System/10_Output_Test/GPIO.jack @@ -0,0 +1 @@ +../GPIO.jack \ No newline at end of file diff --git a/07_Operating_System/10_Output_Test/Main.jack b/07_Operating_System/10_Output_Test/Main.jack new file mode 100644 index 0000000..e4b36c8 --- /dev/null +++ b/07_Operating_System/10_Output_Test/Main.jack @@ -0,0 +1,49 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/12/OutputTest/Main.jack + +/** Test program for the OS Output class. */ +class Main { + + /** Outputs the entire character set to the screen using all the + * methods of the Output class. */ + function void main() { + var String s; + + let s = String.new(1); + do s.appendChar(String.doubleQuote()); + + do Output.moveCursor(0, 29); + do Output.printChar(66); + do Output.moveCursor(28, 0); + do Output.printChar(67); + do Output.moveCursor(28, 29); + do Output.printChar(68); + do Output.printChar(65); + + do Output.moveCursor(2, 0); + do Output.printString("0123456789"); + do Output.println(); + + do Output.printString("ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz"); + do Output.println(); + + do Output.printString("!#$%&'()*+,-./:;<=>?@[\]^_`{|}~"); + do Output.printString(s); + do Output.println(); + + do Output.printInt(-12345); + do Output.backSpace(); + do Output.printInt(6789); + + do Screen.setPenColor(Screen.WHITE()); + do Screen.setBackColor(Screen.RED()); + + do Output.moveCursor(10, 0); + do Output.printString("Back Color Red"); + do Output.println(); + + return; + } +} diff --git a/07_Operating_System/10_Output_Test/Makefile b/07_Operating_System/10_Output_Test/Makefile new file mode 100644 index 0000000..29614ad --- /dev/null +++ b/07_Operating_System/10_Output_Test/Makefile @@ -0,0 +1,18 @@ +all: jack vm asm bin sim + +jack: + ../../tools/JackCompiler/JackCompiler.pyc ./ +vm: + ../../tools/VMTranslator/VMTranslator.pyc ./ +asm: + ../../tools/Assembler/assembler.pyc out.asm +bin: + ../../tools/AsciiToBin.py out.hack +sim: + cp out.hack ../00_HACK/ROM.hack +upload: + iceprogduino -o 64k -w out.bin +clean: + rm -f *.vm *.asm *.hack *.bin *~ + +.PHONY: all clean diff --git a/07_Operating_System/10_Output_Test/Math.jack b/07_Operating_System/10_Output_Test/Math.jack new file mode 120000 index 0000000..a22c6f5 --- /dev/null +++ b/07_Operating_System/10_Output_Test/Math.jack @@ -0,0 +1 @@ +../Math.jack \ No newline at end of file diff --git a/07_Operating_System/10_Output_Test/Memory.jack b/07_Operating_System/10_Output_Test/Memory.jack new file mode 120000 index 0000000..e8b63fa --- /dev/null +++ b/07_Operating_System/10_Output_Test/Memory.jack @@ -0,0 +1 @@ +../Memory.jack \ No newline at end of file diff --git a/07_Operating_System/10_Output_Test/Output.jack b/07_Operating_System/10_Output_Test/Output.jack new file mode 120000 index 0000000..1bc55b8 --- /dev/null +++ b/07_Operating_System/10_Output_Test/Output.jack @@ -0,0 +1 @@ +../Output.jack \ No newline at end of file diff --git a/07_Operating_System/10_Output_Test/Readme.md b/07_Operating_System/10_Output_Test/Readme.md new file mode 100644 index 0000000..ea1f247 --- /dev/null +++ b/07_Operating_System/10_Output_Test/Readme.md @@ -0,0 +1,20 @@ +## Output.jack + +A library of functions for writing text on the screen. +The Hack physical screen consists of 320 rows of 240 pixels each. The library uses a fixed font, in which each character is displayed within a frame which is 11 pixels high (including 1 pixel for inter-line spacing) and 8 pixels wide (including 2 pixels for inter-character spacing). The resulting grid accommodates 29 rows (indexed 0..28, top to bottom) of 30 characters each (indexed 0..29, left to right). The top left character position on the screen is indexed (0,0). A cursor, implemented as a small filled square, indicates where the next character will be displayed. + +*** + +### Project + +* implement `Output.jack` +* test in real hardware + +``` +$ cd 09_Output_Test +$ make +$ make upload +``` + +* compare your screen with: + ![loading-ag-118](output.png) \ No newline at end of file diff --git a/07_Operating_System/10_Output_Test/Readme.md.backup b/07_Operating_System/10_Output_Test/Readme.md.backup new file mode 100644 index 0000000..c79f69d --- /dev/null +++ b/07_Operating_System/10_Output_Test/Readme.md.backup @@ -0,0 +1,15 @@ +## Output.jack +A library of functions for writing text on the screen. +The Hack physical screen consists of 320 rows of 240 pixels each. The library uses a fixed font, in which each character is displayed within a frame which is 11 pixels high (including 1 pixel for inter-line spacing) and 8 pixels wide (including 2 pixels for inter-character spacing). The resulting grid accommodates 29 rows (indexed 0..28, top to bottom) of 30 characters each (indexed 0..29, left to right). The top left character position on the screen is indexed (0,0). A cursor, implemented as a small filled square, indicates where the next character will be displayed. +*** +### Project +* implement `Output.jack` +* test in real hardware + +``` +$ cd 09_Output_Test +$ make +$ make update +``` +* compare your screen with: +![](output.jpg) \ No newline at end of file diff --git a/07_Operating_System/10_Output_Test/Screen.jack b/07_Operating_System/10_Output_Test/Screen.jack new file mode 120000 index 0000000..5844b79 --- /dev/null +++ b/07_Operating_System/10_Output_Test/Screen.jack @@ -0,0 +1 @@ +../Screen.jack \ No newline at end of file diff --git a/07_Operating_System/10_Output_Test/StdIO.jack b/07_Operating_System/10_Output_Test/StdIO.jack new file mode 120000 index 0000000..7883f6e --- /dev/null +++ b/07_Operating_System/10_Output_Test/StdIO.jack @@ -0,0 +1 @@ +../StdIO.jack \ No newline at end of file diff --git a/07_Operating_System/10_Output_Test/String.jack b/07_Operating_System/10_Output_Test/String.jack new file mode 120000 index 0000000..6b71bed --- /dev/null +++ b/07_Operating_System/10_Output_Test/String.jack @@ -0,0 +1 @@ +../String.jack \ No newline at end of file diff --git a/07_Operating_System/10_Output_Test/Sys.jack b/07_Operating_System/10_Output_Test/Sys.jack new file mode 120000 index 0000000..4b50826 --- /dev/null +++ b/07_Operating_System/10_Output_Test/Sys.jack @@ -0,0 +1 @@ +../Sys.jack \ No newline at end of file diff --git a/07_Operating_System/10_Output_Test/UART.jack b/07_Operating_System/10_Output_Test/UART.jack new file mode 120000 index 0000000..e7e97fa --- /dev/null +++ b/07_Operating_System/10_Output_Test/UART.jack @@ -0,0 +1 @@ +../UART.jack \ No newline at end of file diff --git a/07_Operating_System/10_Output_Test/output.png b/07_Operating_System/10_Output_Test/output.png new file mode 100644 index 0000000..81bef30 Binary files /dev/null and b/07_Operating_System/10_Output_Test/output.png differ diff --git a/07_Operating_System/11_Touch_Test/Array.jack b/07_Operating_System/11_Touch_Test/Array.jack new file mode 120000 index 0000000..3b12439 --- /dev/null +++ b/07_Operating_System/11_Touch_Test/Array.jack @@ -0,0 +1 @@ +../Array.jack \ No newline at end of file diff --git a/07_Operating_System/11_Touch_Test/GPIO.jack b/07_Operating_System/11_Touch_Test/GPIO.jack new file mode 120000 index 0000000..4583844 --- /dev/null +++ b/07_Operating_System/11_Touch_Test/GPIO.jack @@ -0,0 +1 @@ +../GPIO.jack \ No newline at end of file diff --git a/07_Operating_System/11_Touch_Test/Main.jack b/07_Operating_System/11_Touch_Test/Main.jack new file mode 100644 index 0000000..45147fb --- /dev/null +++ b/07_Operating_System/11_Touch_Test/Main.jack @@ -0,0 +1,17 @@ +class Main{ + + function void main(){ + while (true){ + if (Touch.getEvent()) { + do StdIO.printInt(Touch.getX()); + do StdIO.printString(" "); + do StdIO.printInt(Touch.getY()); + do StdIO.printString(" "); + do StdIO.printInt(Touch.getPen()); + do StdIO.println(); + } + } + return; + } + +} diff --git a/07_Operating_System/11_Touch_Test/Makefile b/07_Operating_System/11_Touch_Test/Makefile new file mode 100644 index 0000000..29614ad --- /dev/null +++ b/07_Operating_System/11_Touch_Test/Makefile @@ -0,0 +1,18 @@ +all: jack vm asm bin sim + +jack: + ../../tools/JackCompiler/JackCompiler.pyc ./ +vm: + ../../tools/VMTranslator/VMTranslator.pyc ./ +asm: + ../../tools/Assembler/assembler.pyc out.asm +bin: + ../../tools/AsciiToBin.py out.hack +sim: + cp out.hack ../00_HACK/ROM.hack +upload: + iceprogduino -o 64k -w out.bin +clean: + rm -f *.vm *.asm *.hack *.bin *~ + +.PHONY: all clean diff --git a/07_Operating_System/11_Touch_Test/Math.jack b/07_Operating_System/11_Touch_Test/Math.jack new file mode 120000 index 0000000..a22c6f5 --- /dev/null +++ b/07_Operating_System/11_Touch_Test/Math.jack @@ -0,0 +1 @@ +../Math.jack \ No newline at end of file diff --git a/07_Operating_System/11_Touch_Test/Memory.jack b/07_Operating_System/11_Touch_Test/Memory.jack new file mode 120000 index 0000000..e8b63fa --- /dev/null +++ b/07_Operating_System/11_Touch_Test/Memory.jack @@ -0,0 +1 @@ +../Memory.jack \ No newline at end of file diff --git a/07_Operating_System/11_Touch_Test/Readme.md b/07_Operating_System/11_Touch_Test/Readme.md new file mode 100644 index 0000000..e80c3aa --- /dev/null +++ b/07_Operating_System/11_Touch_Test/Readme.md @@ -0,0 +1,55 @@ +## Touch.jack + +A library to read touch events from the resistive touch panel controller AR1021. + +See datasheet [AR1021](../../doc/AR1000.pdf): + +To read the next touch event just read 5 consecutive bytes from RTP: +pen,xlow,xhigh,ylow and yhigh. Between every byte there should be a delay of min. 50us. When no data is available, the controller will answer with 4Dh (77d). The Event is only valid if the first byte is 128 or 129, and the x and y coordinates are in the range [0..4095]. + +1. **pen**: 128 = pen up, 129 = pen down +2. **xlow**; 7 least significant bits of x coordinate +3. **xhigh**; 5 most significant bits of x coordinate +4. **ylow**; 7 least significant bits of y coordinate +5. **yhigh**; 5 most significant bits of y coordinate + +xhigh[4:0]*128+xlow[6:0] represent a 12 bit x-coordinate in the range 0-4095. + +yhigh[4:0]*128+ylow[6:0] represent a 12 bit y-coordinate in the range 0-4095 + +![](touch_event.png) + +*** + +### Project + +* implement `Touch.jack` + +* Test in simulation + + ``` + $ cd 11_Touch_Test + $ make + $ cd ../00_HACK + $ apio clean + $ apio sim + ``` + + ![](touch.png) + +* Check for the inter byte delay of approximately 50us. + +* SDO is low while reading data from RTP + +* SCK shows 5 blocks of 8 clocks cycles + +* Connect the resitive touch panel controller AR1021 of MOD-LCD2.8RTP to iCE40HX1K-EVB as described in `06_IO_Devices/07_RTP` + +* Run Touch_Test in real hardware on iCE40HX1K-EVB. Create some touch events on the resistive touch panel RTP and check the messages send to UART_TX. + + ``` + $ cd 11_Touch_Test + $ make + $ make upload + $ tio /dev/ttyACM0 + ``` \ No newline at end of file diff --git a/07_Operating_System/11_Touch_Test/StdIO.jack b/07_Operating_System/11_Touch_Test/StdIO.jack new file mode 120000 index 0000000..7883f6e --- /dev/null +++ b/07_Operating_System/11_Touch_Test/StdIO.jack @@ -0,0 +1 @@ +../StdIO.jack \ No newline at end of file diff --git a/07_Operating_System/11_Touch_Test/String.jack b/07_Operating_System/11_Touch_Test/String.jack new file mode 120000 index 0000000..6b71bed --- /dev/null +++ b/07_Operating_System/11_Touch_Test/String.jack @@ -0,0 +1 @@ +../String.jack \ No newline at end of file diff --git a/07_Operating_System/11_Touch_Test/Sys.jack b/07_Operating_System/11_Touch_Test/Sys.jack new file mode 120000 index 0000000..4b50826 --- /dev/null +++ b/07_Operating_System/11_Touch_Test/Sys.jack @@ -0,0 +1 @@ +../Sys.jack \ No newline at end of file diff --git a/07_Operating_System/11_Touch_Test/Touch.jack b/07_Operating_System/11_Touch_Test/Touch.jack new file mode 120000 index 0000000..a846382 --- /dev/null +++ b/07_Operating_System/11_Touch_Test/Touch.jack @@ -0,0 +1 @@ +../Touch.jack \ No newline at end of file diff --git a/07_Operating_System/11_Touch_Test/UART.jack b/07_Operating_System/11_Touch_Test/UART.jack new file mode 120000 index 0000000..e7e97fa --- /dev/null +++ b/07_Operating_System/11_Touch_Test/UART.jack @@ -0,0 +1 @@ +../UART.jack \ No newline at end of file diff --git a/07_Operating_System/11_Touch_Test/touch.png b/07_Operating_System/11_Touch_Test/touch.png new file mode 100644 index 0000000..486d5b3 Binary files /dev/null and b/07_Operating_System/11_Touch_Test/touch.png differ diff --git a/07_Operating_System/11_Touch_Test/touch_event.png b/07_Operating_System/11_Touch_Test/touch_event.png new file mode 100644 index 0000000..6e8af3d Binary files /dev/null and b/07_Operating_System/11_Touch_Test/touch_event.png differ diff --git a/07_Operating_System/12_Tetris/Array.jack b/07_Operating_System/12_Tetris/Array.jack new file mode 120000 index 0000000..3b12439 --- /dev/null +++ b/07_Operating_System/12_Tetris/Array.jack @@ -0,0 +1 @@ +../Array.jack \ No newline at end of file diff --git a/07_Operating_System/12_Tetris/Button.jack b/07_Operating_System/12_Tetris/Button.jack new file mode 100644 index 0000000..e0e018d --- /dev/null +++ b/07_Operating_System/12_Tetris/Button.jack @@ -0,0 +1,40 @@ +class Button{ + + field int position; + field String text; + + constructor Button new(int p,String t){ + let position = p; + let text = t; + return this; + } + + method void dispose(){ + if (~(text=null)){ + do text.dispose(); + } + do Memory.deAlloc(this); + return; + } + + method void draw(boolean press){ + var int x; + var int y; + var int color; + let x = position & 3; + let y = position/4; + if (press) { + let color = Screen.DARKGREY(); + } else { + let color = Screen.LIGHTGREY(); + } + do Screen.setPenColor(color); + do Screen.drawRectangle((x*60)+1,288-(y*33),(x*60)+58,318-(y*33)); + do Screen.setBackColor(color); + do Screen.setPenColor(Screen.BLACK()); + do Output.moveCursor(27-(3*y),1+((x*15)/2)); + if (~(text=null)){do Output.printString(text);} + do Screen.setBackColor(Screen.WHITE()); + return; + } +} diff --git a/07_Operating_System/12_Tetris/GPIO.jack b/07_Operating_System/12_Tetris/GPIO.jack new file mode 120000 index 0000000..4583844 --- /dev/null +++ b/07_Operating_System/12_Tetris/GPIO.jack @@ -0,0 +1 @@ +../GPIO.jack \ No newline at end of file diff --git a/07_Operating_System/12_Tetris/Grid.jack b/07_Operating_System/12_Tetris/Grid.jack new file mode 100644 index 0000000..1316556 --- /dev/null +++ b/07_Operating_System/12_Tetris/Grid.jack @@ -0,0 +1,89 @@ +class Grid { + field Array grid; + + /** Constructs a new Tile + */ + constructor Grid new() { + var int i; + let grid = Array.new(220); + do Screen.setPenColor(Screen.DARKGREY()); + do Screen.drawRectangle(2,4,3,283); + do Screen.drawRectangle(2,284,147,285); + do Screen.drawRectangle(146,4,147,285); + let i=0; + while (i<220){ + let grid[i]=-1; + let i=i+1; + } + return this; + } + + /** Deallocates the Tile's memory. */ + method void dispose() { + do grid.dispose(); + do Memory.deAlloc(this); + return; + } + + method void draw(int x, int y, int color){ + do Screen.setPenColor(color); + do Screen.drawRectangle((x*14)+6,(y*14)-24,(x*14)+18,(y*14)-12); + if ((x<10)&(x>-1)&(y>-1)&(y<22)) {let grid[(y*10)+x] = color;} + return; + } + + method boolean hasTile(int x, int y){ + if ((x>9)|(x<0)|(y>21)|(y<0)){ + return true; + } + if (grid[(y*10)+x]=-1){ + return false; + } + return true; + } + method boolean isClear(int x, int y){ + return (grid[(y*10)+x]=Screen.DARKGREY()); + } + + method int clearRow(){ + var int x,y,z; + var int r; + var boolean isClear; + let y=0; + let r=0; + while (y<22){ + let isClear = true; + let x=0; + while (x<10){ + if (~hasTile(x,y)) { let isClear = false;} + let x=x+1; + } + if (isClear){ + let r=r+1; + let x=0; + while (x<10){ + do draw(x,y,Screen.DARKGREY()); + let x=x+1; + } + } + let y = y+1; + } + let y=1; + while (y<22){ + let x=0; + while (x<10){ + if (isClear(x,y)) { + let z=y; + while (z>0){ + do draw(x,z,grid[(z*10)-10+x]); + let z=z-1; + } + } + let x=x+1; + } + let y = y+1; + } + + return r; + } +} diff --git a/07_Operating_System/12_Tetris/Main.jack b/07_Operating_System/12_Tetris/Main.jack new file mode 100644 index 0000000..b87fff4 --- /dev/null +++ b/07_Operating_System/12_Tetris/Main.jack @@ -0,0 +1,67 @@ +/** + * The main class of the Tetris game. + */ +class Main { + static Tile tile; + static Menu menu; + static TetrisGame game; + + /** Initializes a Tetris game and starts running it. */ + function void main() { + var int x; + var int time; + let menu = Menu.new(null,null,null," Play"); + do Tile.init(); + let time = 10000; + while(time > 0){ + if (time = 10000){ + do Main.drawStart(); + do Main.drawTile(); + do menu.draw(); + } + if (time = 1){ + do Main.clearTile(); + do Main.drawTile(); + let time = 10000; + } + let x = menu.getButton(); + if (x = 3) { + do Main.clearTile(); + let game = TetrisGame.new(); + do game.run(); + do game.dispose(); + do menu.draw(); + do Sys.wait(5000); + let time = 20000; + } + let time = time - 1; + } + return; + } + + function void drawTile(){ + let tile = Tile.new(); + do tile.move(6,12); + do tile.draw(); + return; + } + + function void clearTile(){ + do tile.erase(); + do tile.dispose(); + return; + } + + function void drawStart(){ + var String n2t; + var String hv; + let n2t = "nand2tetris-fpga"; + do Screen.clearScreen(); + do Screen.setPenColor(0); + do Output.moveCursor(6,7); + do Output.printString(n2t); + do n2t.dispose(); + return; + } + +} diff --git a/07_Operating_System/12_Tetris/Makefile b/07_Operating_System/12_Tetris/Makefile new file mode 100644 index 0000000..29614ad --- /dev/null +++ b/07_Operating_System/12_Tetris/Makefile @@ -0,0 +1,18 @@ +all: jack vm asm bin sim + +jack: + ../../tools/JackCompiler/JackCompiler.pyc ./ +vm: + ../../tools/VMTranslator/VMTranslator.pyc ./ +asm: + ../../tools/Assembler/assembler.pyc out.asm +bin: + ../../tools/AsciiToBin.py out.hack +sim: + cp out.hack ../00_HACK/ROM.hack +upload: + iceprogduino -o 64k -w out.bin +clean: + rm -f *.vm *.asm *.hack *.bin *~ + +.PHONY: all clean diff --git a/07_Operating_System/12_Tetris/Math.jack b/07_Operating_System/12_Tetris/Math.jack new file mode 120000 index 0000000..a22c6f5 --- /dev/null +++ b/07_Operating_System/12_Tetris/Math.jack @@ -0,0 +1 @@ +../Math.jack \ No newline at end of file diff --git a/07_Operating_System/12_Tetris/Memory.jack b/07_Operating_System/12_Tetris/Memory.jack new file mode 120000 index 0000000..e8b63fa --- /dev/null +++ b/07_Operating_System/12_Tetris/Memory.jack @@ -0,0 +1 @@ +../Memory.jack \ No newline at end of file diff --git a/07_Operating_System/12_Tetris/Menu.jack b/07_Operating_System/12_Tetris/Menu.jack new file mode 100644 index 0000000..4c0c1c0 --- /dev/null +++ b/07_Operating_System/12_Tetris/Menu.jack @@ -0,0 +1,70 @@ +class Menu{ + field Array button; + field int last; + field boolean pressed; + + constructor void new(String t0, String t1, String t2, String t3){ + let button = Array.new(4); + let button[0] = Button.new(0,t0); + let button[1] = Button.new(1,t1); + let button[2] = Button.new(2,t2); + let button[3] = Button.new(3,t3); + let last = 0; + let pressed = false; + return this; + } + + method void dispose(){ + var Button b; + var int i; + let i=0; + while (i<4){ + let b=button[i]; + do b.dispose(); + let i=i+1; + } + do button.dispose(); + do Memory.deAlloc(this); + return; + } + + method void draw(){ + var Button b; + var int i; + let i=0; + while (i<4){ + let b=button[i]; + do b.draw(false); + let i=i+1; + } + return; + } + method int getButton(){ + var boolean t; + var Button b; + let t = Touch.getEvent(); + if (~t){ + return -1; + } + if (pressed){ + if (Touch.getPen()=0) { + let pressed = false; + let b=button[last]; + do b.draw(false); + } + } else { + if ((Touch.getPen()=1) & (Touch.getY()<1024)){ + let pressed = true; + let b = button[last]; + do b.draw(false); + let last = Touch.getX()/1024; + let b = button[last]; + do b.draw(true); + return last; + } + return -1; + } + return -1; + } + +} diff --git a/07_Operating_System/12_Tetris/Output.jack b/07_Operating_System/12_Tetris/Output.jack new file mode 120000 index 0000000..1bc55b8 --- /dev/null +++ b/07_Operating_System/12_Tetris/Output.jack @@ -0,0 +1 @@ +../Output.jack \ No newline at end of file diff --git a/07_Operating_System/12_Tetris/Random.jack b/07_Operating_System/12_Tetris/Random.jack new file mode 100644 index 0000000..8a9030a --- /dev/null +++ b/07_Operating_System/12_Tetris/Random.jack @@ -0,0 +1,13 @@ +class Random { + static int r; + + function int nextInt() { + let r = (r * 31421) + 6927; + return r; + } + + function void seed(int i){ + let r = i; + return; + } +} diff --git a/07_Operating_System/12_Tetris/Screen.jack b/07_Operating_System/12_Tetris/Screen.jack new file mode 120000 index 0000000..5844b79 --- /dev/null +++ b/07_Operating_System/12_Tetris/Screen.jack @@ -0,0 +1 @@ +../Screen.jack \ No newline at end of file diff --git a/07_Operating_System/12_Tetris/StdIO.jack b/07_Operating_System/12_Tetris/StdIO.jack new file mode 120000 index 0000000..7883f6e --- /dev/null +++ b/07_Operating_System/12_Tetris/StdIO.jack @@ -0,0 +1 @@ +../StdIO.jack \ No newline at end of file diff --git a/07_Operating_System/12_Tetris/String.jack b/07_Operating_System/12_Tetris/String.jack new file mode 120000 index 0000000..6b71bed --- /dev/null +++ b/07_Operating_System/12_Tetris/String.jack @@ -0,0 +1 @@ +../String.jack \ No newline at end of file diff --git a/07_Operating_System/12_Tetris/Sys.jack b/07_Operating_System/12_Tetris/Sys.jack new file mode 120000 index 0000000..4b50826 --- /dev/null +++ b/07_Operating_System/12_Tetris/Sys.jack @@ -0,0 +1 @@ +../Sys.jack \ No newline at end of file diff --git a/07_Operating_System/12_Tetris/TetrisGame.jack b/07_Operating_System/12_Tetris/TetrisGame.jack new file mode 100644 index 0000000..d5ac75e --- /dev/null +++ b/07_Operating_System/12_Tetris/TetrisGame.jack @@ -0,0 +1,106 @@ +/** + * Represents a Tetris game. + */ +class TetrisGame { + + field String S_next; + field String S_score; + field String S_game; + field Tile tile; // the tile + field Tile next; + field boolean exit; // true when the game is over + field int score; // the current score. + field boolean update; + field Grid grid; + field int time; + field Menu menu; + + /** Constructs a new Tetris game. */ + constructor TetrisGame new() { + let score = 0; + let S_next = "Next:"; + let S_score = "Score:"; + let S_game = "Game over!"; + do Screen.clearScreen(); + let menu = Menu.new(" <-"," L"," R"," ->"); + do menu.draw(); + do Screen.setPenColor(0); + do Output.moveCursor(4,20); + do Output.printString(S_next); + do Output.moveCursor(13,20); + do Output.printString(S_score); + do Output.moveCursor(15,21); + do Output.printInt(score); + let exit = false; + let grid = Grid.new(); + let next = Tile.new(); + do next.draw(); + let time = 2000; + return this; + } + + /** Deallocates the object's memory. */ + method void dispose() { + do S_next.dispose(); + do S_score.dispose(); + do S_game.dispose(); + do grid.dispose(); + do next.dispose(); + do menu.dispose(); + do Memory.deAlloc(this); + return; + } + + method void score(int r){ + if (r=1) {let score = score + 40; } + if (r=2) {let score = score + 100; } + if (r=3) {let score = score + 300; } + if (r=4) {let score = score +1200; } + do Screen.setPenColor(0); + do Output.moveCursor(15,21); + do Output.printInt(score); + return; + } + /** Starts the game, and handles inputs from the user that control + * the bat's movement direction. */ + method void run() { + var int p; + let exit = false; + let tile = next; + do tile.span(grid); + let next = Tile.new(); + do next.draw(); + let exit = false; + while (~exit){ + let p = menu.getButton(); + if (p = 3) { do tile.moveRight();} + if (p = 2) { do tile.rotateRight();} + if (p = 1) { do tile.rotateLeft();} + if (p = 0) { do tile.moveLeft();} + let time = time -1; + if (time=0){ + if (~(tile.moveDown())){ + do score(tile.getScore()); + do tile.dispose(); + let tile = next; + if (~(next.span(grid))) { + let exit = true; + } else { + let next = Tile.new(); + do next.draw(); + } + } + + + if (exit) { + do Screen.setPenColor(0); + do Output.moveCursor(10,5); + do Output.printString(S_game); + } + let time = 2000; + } + } + return; + } + +} diff --git a/07_Operating_System/12_Tetris/Tile.jack b/07_Operating_System/12_Tetris/Tile.jack new file mode 100644 index 0000000..ebd06dc --- /dev/null +++ b/07_Operating_System/12_Tetris/Tile.jack @@ -0,0 +1,260 @@ +/** + * A graphical tile. Characterized by a screen location and color. + * Has methods for drawing, erasing and moving on the screen. + */ + +class Tile { + field int x; + field int y; + field int r; + field int type; + field Grid grid; + static Array colors; + static Array bits; + + function void init(){ + let colors = Array.new(7); + let colors[0] = Screen.YELLOW(); + let colors[1] = Screen.TEAL(); + let colors[2] = Screen.PURPLE(); + let colors[3] = Screen.GREEN(); + let colors[4] = Screen.RED(); + let colors[5] = Screen.BLUE(); + let colors[6] = Screen.ORANGE(); + + let bits = Array.new(28); + let bits[0] = 1632; + let bits[1] = 1632; + let bits[2] = 1632; + let bits[3] = 1632; + + let bits[4] = 3840; + let bits[5] = 8738; + let bits[6] = 240; + let bits[7] = 17476; + + let bits[8] = 19968; + let bits[9] = 17984; + let bits[10] = 3648; + let bits[11] = 19520; + + let bits[12] = 27648; + let bits[13] = 17952; + let bits[14] = 1728; + let bits[15] = ~29631; + + let bits[16] = ~14847; + let bits[17] = 9792; + let bits[18] = 3168; + let bits[19] = 19584; + + let bits[20] = ~29183; + let bits[21] = 25664; + let bits[22] = 3616; + let bits[23] = 17600; + + let bits[24] = 11776; + let bits[25] = 17504; + let bits[26] = 3712; + let bits[27] = ~15295; + return; + } + + /** Constructs a new Tile + */ + constructor Tile new() { + var int r; + let grid = null; + let type=7; + while (type = 7){ + let type = Random.nextInt() & 7; + } + let x = 11; + let y = 6; + let r = 0; + return this; + } + + method void move(int px,int py){ + let x=px; + let y=py; + return; + } + /** Deallocates the Tile's memory. */ + method void dispose() { + do Memory.deAlloc(this); + return; + } + + method boolean check(){ + var int i; + var int j; + var int bit; + let j = 0; + let bit = bits[(type*4)+r]; + while (j<4){ + let i=0; + while (i<4){ + if (bit<0){ + if (grid.hasTile(x+i,y+j)) { + return false; + } + } + let i=i+1; + let bit = bit + bit; + } + let j = j+1; + } + return true; + } + + method int getScore(){ + return grid.clearRow(); + } + + method void rotateRight(){ + do erase(); + let r = r+1; + if (r>3) { + let r=r-4; + } + if (check()) { + do draw(); + } else { + let r = r-1; + if (r<0) { + let r=r+4; + } + do draw(); + } + return; + } + + method void rotateLeft(){ + do erase(); + let r = r-1; + if (r<0) { + let r=r+4; + } + if (check()) { + do draw(); + } else { + let r = r+1; + if (r>3) { + let r=r-4; + } + do draw(); + } + return; + } + + method void moveRight(){ + do erase(); + let x = x + 1; + if (check()) { + do draw(); + } else { + let x = x-1; + do draw(); + } + return; + } + + method void moveLeft(){ + do erase(); + let x = (x-1); + if (~(check())) { + let x = x + 1; + } + do draw(); + return; + } + + method void moveUp(){ + do erase(); + let y = y - 1; + if (check()) { + do draw(); + } else { + let y = y + 1; + do draw(); + } + return; + } + + method boolean moveDown(){ + do erase(); + let y = y + 1; + if (check()) { + do draw(); + return true; + } + let y = y - 1; + do draw(); + return false; + } + + method boolean span(Grid g){ + do erase(); + let grid=g; + let x=3; + let y=0; + if (check()){ + do draw(); + return true; + } + return false; + } + + method void draw(){ + var int i,j; + var int bit; + let i = 0; + let j = 0; + let bit = bits[(type*4)+r]; + while (j<4){ + let i=0; + while (i<4){ + if (bit<0){ + if (~(grid=null)) {do grid.draw(x+i,y+j,colors[type]);} + else { + do Screen.setPenColor(colors[type]); + do Screen.drawRectangle(((x+i)*14)+6,((y+j)*14)-24,((x+i)*14)+18,((y+j)*14)-12); + } + } + let i = i+1; + let bit = bit + bit; + } + let j = j+1; + } + return; + } + + method void erase(){ + var int i,j; + var int bit; + let i = 0; + let j = 0; + let bit = bits[(type*4)+r]; + while (j<4){ + let i=0; + while (i<4){ + if (bit<0){ + if (~(grid=null)) { + do grid.draw(x+i,y+j,-1); + } + else { + do Screen.setPenColor(-1); + do Screen.drawRectangle(((x+i)*14)+6,((y+j)*14)-24,((x+i)*14)+18,((y+j)*14)-12); + } + } + let i = i+1; + let bit = bit + bit; + } + let j = j+1; + } + return; + } + + +} diff --git a/07_Operating_System/12_Tetris/Touch.jack b/07_Operating_System/12_Tetris/Touch.jack new file mode 120000 index 0000000..a846382 --- /dev/null +++ b/07_Operating_System/12_Tetris/Touch.jack @@ -0,0 +1 @@ +../Touch.jack \ No newline at end of file diff --git a/07_Operating_System/12_Tetris/UART.jack b/07_Operating_System/12_Tetris/UART.jack new file mode 120000 index 0000000..e7e97fa --- /dev/null +++ b/07_Operating_System/12_Tetris/UART.jack @@ -0,0 +1 @@ +../UART.jack \ No newline at end of file diff --git a/07_Operating_System/Array.jack b/07_Operating_System/Array.jack new file mode 100644 index 0000000..b30dc13 --- /dev/null +++ b/07_Operating_System/Array.jack @@ -0,0 +1,18 @@ +/** + * Represents an array. + * In the Jack language, arrays are instances of the Array class. + * Once declared, the array entries can be accessed using the usual + * syntax arr[i]. Each array entry can hold a primitive data type as + * well as any object type. Different array entries can have different + * data types. + */ +class Array { + + /** Constructs a new Array of the given size. */ + function Array new(int size) { + } + + /** Disposes this array. */ + method void dispose() { + } +} diff --git a/07_Operating_System/GPIO.jack b/07_Operating_System/GPIO.jack new file mode 100644 index 0000000..cdcd6b1 --- /dev/null +++ b/07_Operating_System/GPIO.jack @@ -0,0 +1,22 @@ +/** + * This library provides access to BUT and LED. + */ +class GPIO { + + /** Initialize LED and BUT. LED is memory mapped to addr. + * BUT is memory mapepd to addr +1 */ + function void init(int addr){ + } + + /** Returns the value of LED. */ + function int readLed(){ + } + + /** Write c to LED */ + function void writeLed(int value){ + } + + /** Returns the value of BUT */ + function int readBut() { + } +} diff --git a/07_Operating_System/Math.jack b/07_Operating_System/Math.jack new file mode 100644 index 0000000..b803e44 --- /dev/null +++ b/07_Operating_System/Math.jack @@ -0,0 +1,42 @@ +/** + * A library of commonly used mathematical functions. + * Note: Jack compilers implement multiplication and division using OS method calls. + */ +class Math { + + /** Initializes the library. */ + function void init() { + } + + /** Returns the absolute value of x. */ + function int abs(int x) { + } + + /** Returns the product of x and y. + * When a Jack compiler detects the multiplication operator '*' in the + * program's code, it handles it by invoking this method. In other words, + * the Jack expressions x*y and multiply(x,y) return the same value. + */ + function int multiply(int x, int y) { + } + + /** Returns the integer part of x/y. + * When a Jack compiler detects the multiplication operator '/' in the + * program's code, it handles it by invoking this method. In other words, + * the Jack expressions x/y and divide(x,y) return the same value. + */ + function int divide(int x, int y) { + } + + /** Returns the integer part of the square root of x. */ + function int sqrt(int x) { + } + + /** Returns the greater number. */ + function int max(int a, int b) { + } + + /** Returns the smaller number. */ + function int min(int a, int b) { + } +} diff --git a/07_Operating_System/Memory.jack b/07_Operating_System/Memory.jack new file mode 100644 index 0000000..d39ac08 --- /dev/null +++ b/07_Operating_System/Memory.jack @@ -0,0 +1,30 @@ +/** + * This library provides two services: direct access to the computer's main + * memory (RAM), and allocation and recycling of memory blocks. The Hack RAM + * consists of 3840 words, each holding a 16-bit binary number. + */ +class Memory { + + /** Initializes the class. start is the first memory address of the heap. + * end is the last memory address of the heap */ + function void init(int start, int end) { + } + + /** Returns the RAM value at the given address. */ + function int peek(int address) { + } + + /** Sets the RAM value at the given address to the given value. */ + function void poke(int address, int value) { + } + + /** Finds an available RAM block of the given size and returns + * a reference to its base address. */ + function int alloc(int size) { + } + + /** De-allocates the given object (cast as an array) by making + * it available for future allocations. */ + function void deAlloc(Array o) { + } +} diff --git a/07_Operating_System/Output.jack b/07_Operating_System/Output.jack new file mode 100644 index 0000000..bcc12b7 --- /dev/null +++ b/07_Operating_System/Output.jack @@ -0,0 +1,196 @@ +/** + * A library of functions for writing text on the screen. + * The Hack physical screen consists of 320 rows of 240 pixels each. + * The library uses a fixed font, in which each character is displayed + * within a frame which is 11 pixels high (including 1 pixel for inter-line + * spacing) and 8 pixels wide (including 2 pixels for inter-character spacing). + * The resulting grid accommodates 29 rows (indexed 0..28, top to bottom) + * of 30 characters each (indexed 0..29, left to right). The top left + * character position on the screen is indexed (0,0). A cursor, implemented + * as a small filled square, indicates where the next character will be displayed. + */ + +class Output { + + // Character map for displaying characters + static Array charMaps; + /** Initializes the screen, and locates the cursor at the screen's top-left. */ + function void init() { + } + // Initializes the character map array + function void initMap() { + var int i; + let charMaps = Array.new(127); + + // Black square, used for displaying non-printable characters. + do Output.create(0,63,63,63,63,63,63,63,63,63,0,0); + + // Assigns the bitmap for each character in the charachter set. + // The first parameter is the character index, the next 11 numbers + // are the values of each row in the frame that represents this character. + do Output.create(32,0,0,0,0,0,0,0,0,0,0,0); // + do Output.create(33,12,30,30,30,12,12,0,12,12,0,0); // ! + do Output.create(34,54,54,20,0,0,0,0,0,0,0,0); // " + do Output.create(35,0,18,18,63,18,18,63,18,18,0,0); // # + do Output.create(36,12,30,51,3,30,48,51,30,12,12,0); // $ + do Output.create(37,0,0,35,51,24,12,6,51,49,0,0); // % + do Output.create(38,12,30,30,12,54,27,27,27,54,0,0); // & + do Output.create(39,12,12,6,0,0,0,0,0,0,0,0); // ' + do Output.create(40,24,12,6,6,6,6,6,12,24,0,0); // ( + do Output.create(41,6,12,24,24,24,24,24,12,6,0,0); // ) + do Output.create(42,0,0,0,51,30,63,30,51,0,0,0); // * + do Output.create(43,0,0,0,12,12,63,12,12,0,0,0); // + + do Output.create(44,0,0,0,0,0,0,0,12,12,6,0); // , + do Output.create(45,0,0,0,0,0,63,0,0,0,0,0); // - + do Output.create(46,0,0,0,0,0,0,0,12,12,0,0); // . + do Output.create(47,0,0,32,48,24,12,6,3,1,0,0); // / + + do Output.create(48,12,30,51,51,51,51,51,30,12,0,0); // 0 + do Output.create(49,12,14,15,12,12,12,12,12,63,0,0); // 1 + do Output.create(50,30,51,48,24,12,6,3,51,63,0,0); // 2 + do Output.create(51,30,51,48,48,28,48,48,51,30,0,0); // 3 + do Output.create(52,16,24,28,26,25,63,24,24,60,0,0); // 4 + do Output.create(53,63,3,3,31,48,48,48,51,30,0,0); // 5 + do Output.create(54,28,6,3,3,31,51,51,51,30,0,0); // 6 + do Output.create(55,63,49,48,48,24,12,12,12,12,0,0); // 7 + do Output.create(56,30,51,51,51,30,51,51,51,30,0,0); // 8 + do Output.create(57,30,51,51,51,62,48,48,24,14,0,0); // 9 + + do Output.create(58,0,0,12,12,0,0,12,12,0,0,0); // : + do Output.create(59,0,0,12,12,0,0,12,12,6,0,0); // ; + do Output.create(60,0,0,24,12,6,3,6,12,24,0,0); // < + do Output.create(61,0,0,0,63,0,0,63,0,0,0,0); // = + do Output.create(62,0,0,3,6,12,24,12,6,3,0,0); // > + do Output.create(64,30,51,51,59,59,59,27,3,30,0,0); // @ + do Output.create(63,30,51,51,24,12,12,0,12,12,0,0); // ? + + do Output.create(65,12,30,51,51,63,51,51,51,51,0,0); // A ** TO BE FILLED ** + do Output.create(66,31,51,51,51,31,51,51,51,31,0,0); // B + do Output.create(67,28,54,35,3,3,3,35,54,28,0,0); // C + do Output.create(68,15,27,51,51,51,51,51,27,15,0,0); // D + do Output.create(69,63,51,35,11,15,11,35,51,63,0,0); // E + do Output.create(70,63,51,35,11,15,11,3,3,3,0,0); // F + do Output.create(71,28,54,35,3,59,51,51,54,44,0,0); // G + do Output.create(72,51,51,51,51,63,51,51,51,51,0,0); // H + do Output.create(73,30,12,12,12,12,12,12,12,30,0,0); // I + do Output.create(74,60,24,24,24,24,24,27,27,14,0,0); // J + do Output.create(75,51,51,51,27,15,27,51,51,51,0,0); // K + do Output.create(76,3,3,3,3,3,3,35,51,63,0,0); // L + do Output.create(77,33,51,63,63,51,51,51,51,51,0,0); // M + do Output.create(78,51,51,55,55,63,59,59,51,51,0,0); // N + do Output.create(79,30,51,51,51,51,51,51,51,30,0,0); // O + do Output.create(80,31,51,51,51,31,3,3,3,3,0,0); // P + do Output.create(81,30,51,51,51,51,51,63,59,30,48,0);// Q + do Output.create(82,31,51,51,51,31,27,51,51,51,0,0); // R + do Output.create(83,30,51,51,6,28,48,51,51,30,0,0); // S + do Output.create(84,63,63,45,12,12,12,12,12,30,0,0); // T + do Output.create(85,51,51,51,51,51,51,51,51,30,0,0); // U + do Output.create(86,51,51,51,51,51,30,30,12,12,0,0); // V + do Output.create(87,51,51,51,51,51,63,63,63,18,0,0); // W + do Output.create(88,51,51,30,30,12,30,30,51,51,0,0); // X + do Output.create(89,51,51,51,51,30,12,12,12,30,0,0); // Y + do Output.create(90,63,51,49,24,12,6,35,51,63,0,0); // Z + + do Output.create(91,30,6,6,6,6,6,6,6,30,0,0); // [ + do Output.create(92,0,0,1,3,6,12,24,48,32,0,0); // \ + do Output.create(93,30,24,24,24,24,24,24,24,30,0,0); // ] + do Output.create(94,8,28,54,0,0,0,0,0,0,0,0); // ^ + do Output.create(95,0,0,0,0,0,0,0,0,0,63,0); // _ + do Output.create(96,6,12,24,0,0,0,0,0,0,0,0); // ` + + do Output.create(97,0,0,0,14,24,30,27,27,54,0,0); // a + do Output.create(98,3,3,3,15,27,51,51,51,30,0,0); // b + do Output.create(99,0,0,0,30,51,3,3,51,30,0,0); // c + do Output.create(100,48,48,48,60,54,51,51,51,30,0,0); // d + do Output.create(101,0,0,0,30,51,63,3,51,30,0,0); // e + do Output.create(102,28,54,38,6,15,6,6,6,15,0,0); // f + do Output.create(103,0,0,30,51,51,51,62,48,51,30,0); // g + do Output.create(104,3,3,3,27,55,51,51,51,51,0,0); // h + do Output.create(105,12,12,0,14,12,12,12,12,30,0,0); // i + do Output.create(106,48,48,0,56,48,48,48,48,51,30,0); // j + do Output.create(107,3,3,3,51,27,15,15,27,51,0,0); // k + do Output.create(108,14,12,12,12,12,12,12,12,30,0,0); // l + do Output.create(109,0,0,0,29,63,43,43,43,43,0,0); // m + do Output.create(110,0,0,0,29,51,51,51,51,51,0,0); // n + do Output.create(111,0,0,0,30,51,51,51,51,30,0,0); // o + do Output.create(112,0,0,0,30,51,51,51,31,3,3,0); // p + do Output.create(113,0,0,0,30,51,51,51,62,48,48,0); // q + do Output.create(114,0,0,0,29,55,51,3,3,7,0,0); // r + do Output.create(115,0,0,0,30,51,6,24,51,30,0,0); // s + do Output.create(116,4,6,6,15,6,6,6,54,28,0,0); // t + do Output.create(117,0,0,0,27,27,27,27,27,54,0,0); // u + do Output.create(118,0,0,0,51,51,51,51,30,12,0,0); // v + do Output.create(119,0,0,0,51,51,51,63,63,18,0,0); // w + do Output.create(120,0,0,0,51,30,12,12,30,51,0,0); // x + do Output.create(121,0,0,0,51,51,51,62,48,24,15,0); // y + do Output.create(122,0,0,0,63,27,12,6,51,63,0,0); // z + + do Output.create(123,56,12,12,12,7,12,12,12,56,0,0); // { + do Output.create(124,12,12,12,12,12,12,12,12,12,0,0); // | + do Output.create(125,7,12,12,12,56,12,12,12,7,0,0); // } + do Output.create(126,38,45,25,0,0,0,0,0,0,0,0); // ~ + + return; + } + + // Creates the character map array of the given character index, using the given values. + function void create(int index, int a, int b, int c, int d, int e, + int f, int g, int h, int i, int j, int k) { + var Array map; + + let map = Array.new(11); + let charMaps[index] = map; + + let map[0] = a; + let map[1] = b; + let map[2] = c; + let map[3] = d; + let map[4] = e; + let map[5] = f; + let map[6] = g; + let map[7] = h; + let map[8] = i; + let map[9] = j; + let map[10] = k; + + return; + } + + // Returns the character map (array of size 11) of the given character. + // If the given character is invalid or non-printable, returns the + // character map of a black square. + function Array getMap(char c) { + if ((c < 32) | (c > 126)) { + let c = 0; + } + return charMaps[c]; + } + + /** Moves the cursor to the j-th column of the i-th row, + * and erases the character displayed there. */ + function void moveCursor(int i, int j) { + } + + /** Displays the given character at the cursor location, + * and advances the cursor one column forward. */ + function void printChar(char c) { + } + + /** displays the given string starting at the cursor location, + * and advances the cursor appropriately. */ + function void printString(String s) { + } + + /** Displays the given integer starting at the cursor location, + * and advances the cursor appropriately. */ + function void printInt(int i) { + } + + /** Advances the cursor to the beginning of the next line. */ + function void println() { + } + + /** Moves the cursor one column back. */ + function void backSpace() { + } +} diff --git a/07_Operating_System/Readme.md b/07_Operating_System/Readme.md new file mode 100644 index 0000000..1a0f665 --- /dev/null +++ b/07_Operating_System/Readme.md @@ -0,0 +1,39 @@ +# 07 Operating System + +To run serious application like Tetris we need the operating system JACK-OS, written in the high level language JACK. + +For every JACK-OS class we provide a skeleton file, with the signatures of functions and methods. In the dedicated test folder you find implementation details and test classes. + +The folder `00_HACK` contains a simulation of HACK similar to the one in `06_IO_Devices/00_HACK` with the following differences: + +* uses build in chips from `01_Boolean_Logic` to `03_Sequential_Logic` instead of going down to the nand gate level. +* has 64k words of instruction ROM preloaded with JACK-OS and applications +* is not uploadable to iCE40HX1K-EVB + +## Simulation of JACK-OS classes + +Use `00_HACK` of `07_Operating_System` to test your JACK-OS classes in simulation. + +``` +$ cd +$ make +$ cd ../00_HACK +$ apio clean +$ apio sim +``` + +## Run JACK-OS in real hardware on iCE40HX1K-EVB + +To test JACK-OS on real hardware iCE40HX1K-EVB use the design of HACK developed in `06_IO_Devices` with the bootloader of `05_GO`. Attach iCE40HX1K-EVB to your computer and run the following commands: + +``` +$ cd +$ make +$ make upload +``` + +This will compile all classes in the test folder and upload the binary file to SPI flash rom starting at address 64k (0x010000), where the bootloader can find it. + +**Attention:** All used classes must be linked to the folder in which you run the compiler. To add the class `.jack` simply make a soft link in the working directory: + +Finally you can run Tetris! \ No newline at end of file diff --git a/07_Operating_System/Screen.jack b/07_Operating_System/Screen.jack new file mode 100644 index 0000000..f951dba --- /dev/null +++ b/07_Operating_System/Screen.jack @@ -0,0 +1,128 @@ +/** +* A library of functions for displaying graphics on the screen. +* The connected LCD physical screen consists of 320 rows (indexed 0..319, top to bottom) +* of 240 pixels each (indexed 0..239, left to right). The top left pixel on +* the screen is indexed (0,0). Every pixel can be set to a 16 bit color code composed of +* RGB parts of 5 bit red, 6 bit green and 5 bit blue: rrrrrggggggbbbbb. +*/ +class Screen { + + /** Initializes the Screen. */ + function void init(int addr){ + } + + /** Erases the entire screen. */ + function void clearScreen(){ + } + + /** Sets the current pen color, to be used for all subsequent drawXXX + * commands. Colors are represented by 16 bit RGB values with + * binary representation: rrrrrggggggbbbbb */ + function void setPenColor(int color){ + } + + /** Sets the current back ground color, to be used for clearScreen() + * and drawBitMap() commands. + * Colors are represented by 16 bit RGB values: rrrrrggggggbbbbb */ + function void setBackColor(int color){ + } + + /** Draws the (x,y) pixel, using the current pen color. */ + function void drawPixel(int x,int y){ + } + + /** Draws a line from pixel (x1,y1) to pixel (x2,y2), using the current + * pen color. */ + function void drawLine(int x1,int y1,int x2,int y2){ + } + + /** Draws a filled rectangle whose top left corner is (x1, y1) + * and bottom right corner is (x2,y2), using the current pen color. */ + function void drawRectangle(int x1, int y1, int x2, int y2){ + } + + /** Draws a filled circle of radius r<=181 around (x,y), using the + * current pen color. */ + function void drawCircle(int x, int y, int r){ + } + + /** sets the Window to a rectangle with upper left corner (x1,y1) + * and lower right corner (x2,y2). The next w*h calls to + * writeData16(int color) will paint the w*h pixels in the rectangle + * in the corresponding color.*/ + function void setWindow(int x1, int y1, int x2, int y2){ + } + + /** sets the rgb color for the next pixel in the rectangle set by + * setWindow(int x1, int y1, int x2, int y2).*/ + function void writeData16(int color){ + } + + /** writes 8 bit data to LCD with DCX wire set to high. */ + function void writeData(int data){ + } + + /** writes the 8 bit command with DCX wire set to low */ + function void writeCommand(int command){ + } + + /** draws the BitMap into the rectangle with upper left corner (x1,y1) + * and lower right corner (x2,y2) using the pen color for all 1s and the + * back color for all 0s in the BitMap. BitMap is an Array of h integers + * representing up to 16 pixel in the row. The rectangle is limited + * to maximal 16 pixels in width.*/ + function void drawBitMap(int x1, int y1, int x2, int y2, Array map){ + } + + /** RGB values for various colors. */ + function int BLACK(){ + } + function int NAVY(){ + return 30; //00000 000000 11110 + } + function int BLUE(){ + return 31; //00000 000000 11111 + } + function int LIME(){ + return 2016; //00000 111111 00000 + } + function int GREEN(){ + return 1920; //00000 111100 00000 + } + function int CYAN(){ + return 2047; //00000 111111 11111 + } + function int MAROON(){ + return -4096; //11110 000000 00000 + } + function int PURPLE(){ + return -4066; //11110 000000 11110 + } + function int OLIVE(){ + return -2176; //11110 111100 00000 + } + function int DARKGREY(){ + return -14824; //11000 110000 11000 + } + function int TEAL(){ + return 1950; //00000 111000 11100 + } + function int LIGHTGREY(){ + return -6372; //11100 111000 11100 + } + function int RED(){ + return -2048; //11111 000000 00000 + } + function int MAGENTA(){ + return -2017; //11111 000000 11111 + } + function int YELLOW(){ + return -32; //11111 111111 00000 + } + function int ORANGE(){ + return -128; //11111 111000 00000 + } + function int WHITE(){ + return -1; //11111 111111 11111 + } +} diff --git a/07_Operating_System/StdIO.jack b/07_Operating_System/StdIO.jack new file mode 100644 index 0000000..401979a --- /dev/null +++ b/07_Operating_System/StdIO.jack @@ -0,0 +1,33 @@ +/** +* A library of functions for text based input and output over UART +*/ +class StdIO { + + /** Prints the String s to UART_TX and disposes the String s */ + function void printString(String s){ + } + + /** Prints the decimal representation of i to UART_TX */ + function void printInt(int i) { + } + + /** Prints the new line character to UART_TX */ + function void println(){ + } + + /** + * Sends the message to UART_TX, disposes the message, + * reads from UART_RX the entered text until a newline character + * is detected, echoes the text to UART_TX, and returns its integer + * value (until the first non-digit character in the entered text is + * detected). Also handles user backspaces. */ + function int readInt(String message) { + } + + /** + * Sends the message to UART_TX, reads from UART_RX the entered + * text until a newline character is detected, echoes the text + * to the UART_TX, and returns its value. Also handles user backspaces. */ + function String readLine(String message) { + } +} diff --git a/07_Operating_System/String.jack b/07_Operating_System/String.jack new file mode 100644 index 0000000..0f91c37 --- /dev/null +++ b/07_Operating_System/String.jack @@ -0,0 +1,60 @@ +/** + * Represents character strings. In addition for constructing and disposing + * strings, the class features methods for getting and setting individual + * characters of the string, for erasing the string's last character, + * for appending a character to the string's end, and more typical + * string-oriented operations. + */ + +class String { + + /** constructs a new empty string with a maximum length of maxLength + * and initial length of 0. */ + constructor String new(int maxLength) { + } + + /** Disposes this string. */ + method void dispose() { + } + + /** Returns the current length of this string. */ + method int length() { + } + + /** Returns the character at the j-th location of this string. */ + method char charAt(int j) { + } + + /** Sets the character at the j-th location of this string to c. */ + method void setCharAt(int j, char c) { + } + + /** Appends c to this string's end and returns this string. */ + method String appendChar(char c) { + } + + /** Erases the last character from this string. */ + method void eraseLastChar() { + } + + /** Returns the integer value of this string, + * until a non-digit character is detected. */ + method int intValue() { + } + + /** Sets this string to hold a representation of the given value. */ + method void setInt(int val) { + } + + /** Returns the new line character. */ + function char newLine() { + } + + /** Returns the backspace character. */ + function char backSpace() { + } + + /** Returns the double quote (") character. */ + function char doubleQuote() { + } +} diff --git a/07_Operating_System/Sys.jack b/07_Operating_System/Sys.jack new file mode 100644 index 0000000..91a1f52 --- /dev/null +++ b/07_Operating_System/Sys.jack @@ -0,0 +1,23 @@ +/** + * A library that supports various program execution services. + */ +class Sys { + + /** Performs all the initializations required by the OS. */ + function void init() { + } + + /** Halts the program execution. */ + function void halt() { + } + + /** Waits approximately duration milliseconds and returns. */ + function void wait(int duration) { + } + + /** Displays the given error code in the form "ERR", + * and halts the program's execution. */ + function void error(int errorCode) { + } + +} diff --git a/07_Operating_System/Touch.jack b/07_Operating_System/Touch.jack new file mode 100644 index 0000000..f6014f2 --- /dev/null +++ b/07_Operating_System/Touch.jack @@ -0,0 +1,29 @@ +/** A library to read touch events from the resistive touch panel controller + * AR1021.*/ +class Touch{ + + function void init(int addr){ + } + + /** writes 8 bits of c to RTP and returns the response of RTP. + * also responsable for the inter byte delay of approx. 50 us */ + function int writeRTP(int c){ + } + + /** trys to read a valid touch event report. returns true on success. + * returns false, if no valid touch event is available. */ + function boolean getEvent(){ + } + + /** returns the x coordinate in the range [0..4095] of the last touch event report */ + function int getX(){ + } + + /** returns the x coordinate in the range [0..4095] of the last touch event report */ + function int getY(){ + } + + /** returns the pen value (1 = down, 0 = up) of the last touch event report */ + function boolean getPen(){ + } +} diff --git a/07_Operating_System/UART.jack b/07_Operating_System/UART.jack new file mode 100644 index 0000000..5662f0b --- /dev/null +++ b/07_Operating_System/UART.jack @@ -0,0 +1,18 @@ +/** + * Library that provides character based access to UART_TX and UART_RX + */ +class UART { + + /** initializes UART. UART_TX is memory mapped at addr. + * UART_RX is memory mapped at addr+1 */ + function void init(int addr){ + } + + /** wait until UART_RX receives the next char and return the value. */ + function int readChar() { + } + + /** wait for UART_TX to be ready to send next byte and send c. */ + function void writeChar(int c){ + } +} diff --git a/08_3D_Printer/HX1K-Cube_0.2mm_PETG_MK3S_3h2m.gcode b/08_3D_Printer/HX1K-Cube_0.2mm_PETG_MK3S_3h2m.gcode new file mode 100644 index 0000000..1fdf16f --- /dev/null +++ b/08_3D_Printer/HX1K-Cube_0.2mm_PETG_MK3S_3h2m.gcode @@ -0,0 +1,59577 @@ +; generated by PrusaSlicer 2.3.3+linux-x64-GTK3 on 2022-11-11 at 10:38:33 UTC + +; + +; external perimeters extrusion width = 0.45mm +; perimeters extrusion width = 0.45mm +; infill extrusion width = 0.45mm +; solid infill extrusion width = 0.45mm +; top infill extrusion width = 0.40mm +; first layer extrusion width = 0.42mm + +M73 P0 R182 +M73 Q0 S183 +M201 X1000 Y1000 Z200 E5000 ; sets maximum accelerations, mm/sec^2 +M203 X200 Y200 Z12 E120 ; sets maximum feedrates, mm/sec +M204 P1250 R1250 T1250 ; sets acceleration (P, T) and retract acceleration (R), mm/sec^2 +M205 X8.00 Y8.00 Z0.40 E4.50 ; sets the jerk limits, mm/sec +M205 S0 T0 ; sets the minimum extruding and travel feed rate, mm/sec +M107 +;TYPE:Custom +M862.3 P "MK3S" ; printer model check +M862.1 P0.4 ; nozzle diameter check +M115 U3.10.0 ; tell printer latest fw version +G90 ; use absolute coordinates +M83 ; extruder relative mode +M104 S230 ; set extruder temp +M140 S85 ; set bed temp +M190 S85 ; wait for bed temp +M109 S230 ; wait for extruder temp +G28 W ; home all without mesh bed level +G80 ; mesh bed leveling +G1 Y-3.0 F1000.0 ; go outside print area +G92 E0.0 +G1 X60.0 E9.0 F1000.0 ; intro line +G1 X100.0 E12.5 F1000.0 ; intro line +G92 E0.0 +M221 S95 + +; Don't change E values below. Excessive value can damage the printer. +M907 E430 ; set extruder motor current +G21 ; set units to millimeters +G90 ; use absolute coordinates +M83 ; use relative distances for extrusion +M900 K0.08 ; Filament gcode LA 1.5 +M900 K45 ; Filament gcode LA 1.0 +;LAYER_CHANGE +;Z:0.2 +;HEIGHT:0.2 +;BEFORE_LAYER_CHANGE +G92 E0.0 +;0.2 + + +G1 E-1.00000 F2100.000 +M73 Q0 S182 +G1 Z0.200 F10800.000 +;AFTER_LAYER_CHANGE +;0.2 +G1 Z0.400 +G1 X61.172 Y57.879 +G1 Z0.200 +G1 E1.00000 F2100.000 +M204 S1000 +;TYPE:Skirt +;WIDTH:0.42 +G1 F1200.000 +G1 X61.517 Y57.393 E0.01870 +G1 X62.533 Y56.398 E0.04459 +G1 X63.283 Y56.001 E0.02661 +G1 X64.485 Y55.679 E0.03900 +G1 X64.983 Y55.623 E0.01574 +G1 X185.004 Y55.623 E3.76316 +G1 X185.525 Y55.682 E0.01645 +G1 X186.801 Y56.030 E0.04146 +G1 X187.266 Y56.256 E0.01621 +G1 X187.671 Y56.577 E0.01621 +G1 X188.520 Y57.433 E0.03780 +G1 X188.852 Y57.924 E0.01858 +G1 X189.301 Y59.403 E0.04847 +G1 X189.376 Y59.941 E0.01704 +G1 X189.377 Y150.050 E2.82528 +G1 X189.297 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printing object rear_HX1K-Cube.stl id:1 copy 0 +;WIPE_START +G1 F8640.000;_WIPE +G1 X185.500 Y149.934 E-0.08739 +G1 F8640.000;_WIPE +G1 X185.500 Y146.198 E-0.86261 +;WIPE_END +G1 E-0.05000 F2100.000 +G1 Z20.200 F10800.000 +M107 +;TYPE:Custom +; Filament-specific end gcode +G4 ; wait +M221 S100 ; reset flow +M900 K0 ; reset LA +M907 E538 ; reset extruder motor current +M104 S0 ; turn off temperature +M140 S0 ; turn off heatbed +M107 ; turn off fan +G1 Z50 ; Move print head up +G1 X0 Y200 F3000 ; home X axis +M84 ; disable motors +M73 P100 R0 +M73 Q100 S0 +; filament used [mm] = 12457.25 +; filament used [cm3] = 29.96 +; filament used [g] = 38.05 +; filament cost = 1.06 +; total filament used [g] = 38.05 +; total filament cost = 1.06 +; estimated printing time (normal mode) = 3h 1m 48s +; estimated printing time (silent mode) = 3h 2m 36s + +; avoid_crossing_perimeters = 0 +; avoid_crossing_perimeters_max_detour = 0 +; bed_custom_model = +; bed_custom_texture = +; bed_shape = 0x0,250x0,250x210,0x210 +; bed_temperature = 90 +; before_layer_gcode = ;BEFORE_LAYER_CHANGE\nG92 E0.0\n;[layer_z]\n\n +; between_objects_gcode = +; bottom_fill_pattern = monotonic +; bottom_solid_layers = 4 +; bottom_solid_min_thickness = 0.5 +; bridge_acceleration = 1000 +; bridge_angle = 0 +; bridge_fan_speed = 50 +; bridge_flow_ratio = 0.95 +; bridge_speed = 30 +; brim_width = 0 +; clip_multipart_objects = 1 +; color_change_gcode = M600\nG1 E0.4 F1500 ; prime after color change +; compatible_printers_condition_cummulative = "printer_notes=~/.*PRINTER_VENDOR_PRUSA3D.*/ and printer_notes=~/.*PRINTER_MODEL_MK3.*/ and nozzle_diameter[0]==0.4";"nozzle_diameter[0]!=0.6 and nozzle_diameter[0]!=0.8 and printer_model!=\"MK2SMM\" and printer_model!=\"MINI\" and ! (printer_notes=~/.*PRINTER_VENDOR_PRUSA3D.*/ and printer_notes=~/.*PRINTER_MODEL_MK(2.5|3).*/ and single_extruder_multi_material)" +; complete_objects = 0 +; cooling = 1 +; cooling_tube_length = 5 +; cooling_tube_retraction = 91.5 +; default_acceleration = 1000 +; default_filament_profile = "Prusament PLA" +; default_print_profile = 0.15mm QUALITY @MK3 +; deretract_speed = 0 +; disable_fan_first_layers = 3 +; dont_support_bridges = 1 +; draft_shield = 0 +; duplicate_distance = 6 +; elefant_foot_compensation = 0.2 +; end_filament_gcode = "; Filament-specific end gcode" +; end_gcode = G4 ; wait\nM221 S100 ; reset flow\nM900 K0 ; reset LA\n{if print_settings_id=~/.*(DETAIL @MK3|QUALITY @MK3|@0.25 nozzle MK3).*/}M907 E538 ; reset extruder motor current{endif}\nM104 S0 ; turn off temperature\nM140 S0 ; turn off heatbed\nM107 ; turn off fan\n{if max_layer_z < max_print_height}G1 Z{z_offset+min(max_layer_z+30, max_print_height)}{endif} ; Move print head up\nG1 X0 Y200 F3000 ; home X axis\nM84 ; disable motors +; ensure_vertical_shell_thickness = 1 +; external_perimeter_extrusion_width = 0.45 +; external_perimeter_speed = 25 +; external_perimeters_first = 0 +; extra_loading_move = -2 +; extra_perimeters = 0 +; extruder_clearance_height = 20 +; extruder_clearance_radius = 45 +; extruder_colour = "" +; extruder_offset = 0x0 +; extrusion_axis = E +; extrusion_multiplier = 1 +; extrusion_width = 0.45 +; fan_always_on = 1 +; fan_below_layer_time = 20 +; filament_colour = #FF8000 +; filament_cooling_final_speed = 3.4 +; filament_cooling_initial_speed = 2.2 +; filament_cooling_moves = 4 +; filament_cost = 27.82 +; filament_density = 1.27 +; filament_diameter = 1.75 +; filament_load_time = 0 +; filament_loading_speed = 28 +; filament_loading_speed_start = 3 +; filament_max_volumetric_speed = 8 +; filament_minimal_purge_on_wipe_tower = 15 +; filament_notes = "" +; filament_ramming_parameters = "120 100 6.6 6.8 7.2 7.6 7.9 8.2 8.7 9.4 9.9 10.0| 0.05 6.6 0.45 6.8 0.95 7.8 1.45 8.3 1.95 9.7 2.45 10 2.95 7.6 3.45 7.6 3.95 7.6 4.45 7.6 4.95 7.6" +; filament_retract_length = 1 +; filament_retract_lift = 0.2 +; filament_settings_id = "Prusa PETG" +; filament_soluble = 0 +; filament_spool_weight = 230 +; filament_toolchange_delay = 0 +; filament_type = PETG +; filament_unload_time = 0 +; filament_unloading_speed = 90 +; filament_unloading_speed_start = 100 +; filament_vendor = Made for Prusa +; fill_angle = 45 +; fill_density = 15% +; fill_pattern = gyroid +; first_layer_acceleration = 1000 +; first_layer_bed_temperature = 85 +; first_layer_extrusion_width = 0.42 +; first_layer_height = 0.2 +; first_layer_speed = 20 +; first_layer_temperature = 230 +; full_fan_speed_layer = 5 +; gap_fill_speed = 40 +; gcode_comments = 0 +; gcode_flavor = marlin +; gcode_label_objects = 1 +; high_current_on_filament_swap = 0 +; host_type = octoprint +; infill_acceleration = 1000 +; infill_anchor = 2.5 +; infill_anchor_max = 12 +; infill_every_layers = 1 +; infill_extruder = 1 +; infill_extrusion_width = 0.45 +; infill_first = 0 +; infill_only_where_needed = 0 +; infill_overlap = 25% +; infill_speed = 80 +; interface_shells = 0 +; ironing = 0 +; ironing_flowrate = 15% +; ironing_spacing = 0.1 +; ironing_speed = 15 +; ironing_type = top +; layer_gcode = ;AFTER_LAYER_CHANGE\n;[layer_z] +; layer_height = 0.2 +; machine_limits_usage = emit_to_gcode +; machine_max_acceleration_e = 5000,5000 +; machine_max_acceleration_extruding = 1250,1250 +; machine_max_acceleration_retracting = 1250,1250 +; machine_max_acceleration_x = 1000,960 +; machine_max_acceleration_y = 1000,960 +; machine_max_acceleration_z = 200,200 +; machine_max_feedrate_e = 120,120 +; machine_max_feedrate_x = 200,100 +; machine_max_feedrate_y = 200,100 +; machine_max_feedrate_z = 12,12 +; machine_max_jerk_e = 4.5,4.5 +; machine_max_jerk_x = 8,8 +; machine_max_jerk_y = 8,8 +; machine_max_jerk_z = 0.4,0.4 +; machine_min_extruding_rate = 0,0 +; machine_min_travel_rate = 0,0 +; max_fan_speed = 50 +; max_layer_height = 0.25 +; max_print_height = 210 +; max_print_speed = 200 +; max_volumetric_speed = 0 +; min_fan_speed = 30 +; min_layer_height = 0.07 +; min_print_speed = 15 +; min_skirt_length = 4 +; notes = +; nozzle_diameter = 0.4 +; only_retract_when_crossing_perimeters = 0 +; ooze_prevention = 0 +; output_filename_format = {input_filename_base}_{layer_height}mm_{filament_type[0]}_{printer_model}_{print_time}.gcode +; overhangs = 0 +; parking_pos_retraction = 92 +; pause_print_gcode = M601 +; perimeter_acceleration = 800 +; perimeter_extruder = 1 +; perimeter_extrusion_width = 0.45 +; perimeter_speed = 45 +; perimeters = 2 +; physical_printer_settings_id = +; post_process = +; print_settings_id = 0.20mm QUALITY @MK3 +; printer_model = MK3S +; printer_notes = Don't remove the following keywords! These keywords are used in the "compatible printer" condition of the print and filament profiles to link the particular print and filament profiles to this printer profile.\nPRINTER_VENDOR_PRUSA3D\nPRINTER_MODEL_MK3\n +; printer_settings_id = Original Prusa i3 MK3S & MK3S+ +; printer_technology = FFF +; printer_variant = 0.4 +; printer_vendor = +; raft_layers = 0 +; remaining_times = 1 +; resolution = 0 +; retract_before_travel = 1 +; retract_before_wipe = 0% +; retract_layer_change = 1 +; retract_length = 0.8 +; retract_length_toolchange = 4 +; retract_lift = 0.4 +; retract_lift_above = 0 +; retract_lift_below = 209 +; retract_restart_extra = 0 +; retract_restart_extra_toolchange = 0 +; retract_speed = 35 +; seam_position = nearest +; silent_mode = 1 +; single_extruder_multi_material = 0 +; single_extruder_multi_material_priming = 0 +; skirt_distance = 2 +; skirt_height = 3 +; skirts = 1 +; slice_closing_radius = 0.049 +; slowdown_below_layer_time = 15 +; small_perimeter_speed = 25 +; solid_infill_below_area = 0 +; solid_infill_every_layers = 0 +; solid_infill_extruder = 1 +; solid_infill_extrusion_width = 0.45 +; solid_infill_speed = 80 +; spiral_vase = 0 +; standby_temperature_delta = -5 +; start_filament_gcode = "M900 K{if printer_notes=~/.*PRINTER_MODEL_MINI.*/ and nozzle_diameter[0]==0.6}0.12{elsif printer_notes=~/.*PRINTER_MODEL_MINI.*/ and nozzle_diameter[0]==0.8}0.06{elsif printer_notes=~/.*PRINTER_MODEL_MINI.*/}0.2{elsif nozzle_diameter[0]==0.8}0.02{elsif nozzle_diameter[0]==0.6}0.04{else}0.08{endif} ; Filament gcode LA 1.5\n{if printer_notes=~/.*PRINTER_MODEL_MINI.*/};{elsif printer_notes=~/.*PRINTER_HAS_BOWDEN.*/}M900 K200{elsif nozzle_diameter[0]==0.6}M900 K24{elsif nozzle_diameter[0]==0.8};{else}M900 K45{endif} ; Filament gcode LA 1.0" +; start_gcode = M862.3 P "[printer_model]" ; printer model check\nM862.1 P[nozzle_diameter] ; nozzle diameter check\nM115 U3.10.0 ; tell printer latest fw version\nG90 ; use absolute coordinates\nM83 ; extruder relative mode\nM104 S[first_layer_temperature] ; set extruder temp\nM140 S[first_layer_bed_temperature] ; set bed temp\nM190 S[first_layer_bed_temperature] ; wait for bed temp\nM109 S[first_layer_temperature] ; wait for extruder temp\nG28 W ; home all without mesh bed level\nG80 ; mesh bed leveling\nG1 Y-3.0 F1000.0 ; go outside print area\nG92 E0.0\nG1 X60.0 E9.0 F1000.0 ; intro line\nG1 X100.0 E12.5 F1000.0 ; intro line\nG92 E0.0\nM221 S{if layer_height<0.075}100{else}95{endif}\n\n; Don't change E values below. Excessive value can damage the printer.\n{if print_settings_id=~/.*(DETAIL @MK3|QUALITY @MK3).*/}M907 E430 ; set extruder motor current{endif}\n{if print_settings_id=~/.*(SPEED @MK3|DRAFT @MK3).*/}M907 E538 ; set extruder motor current{endif} +; support_material = 0 +; support_material_angle = 0 +; support_material_auto = 1 +; support_material_buildplate_only = 0 +; support_material_contact_distance = 0.1 +; support_material_enforce_layers = 0 +; support_material_extruder = 0 +; support_material_extrusion_width = 0.35 +; support_material_interface_contact_loops = 0 +; support_material_interface_extruder = 0 +; support_material_interface_layers = 2 +; support_material_interface_spacing = 0.2 +; support_material_interface_speed = 80% +; support_material_pattern = rectilinear +; support_material_spacing = 2 +; support_material_speed = 50 +; support_material_synchronize_layers = 0 +; support_material_threshold = 55 +; support_material_with_sheath = 0 +; support_material_xy_spacing = 50% +; temperature = 240 +; template_custom_gcode = +; thin_walls = 0 +; threads = 4 +; thumbnails = +; toolchange_gcode = +; top_fill_pattern = monotonic +; top_infill_extrusion_width = 0.4 +; top_solid_infill_speed = 40 +; top_solid_layers = 5 +; top_solid_min_thickness = 0.7 +; travel_speed = 180 +; use_firmware_retraction = 0 +; use_relative_e_distances = 1 +; use_volumetric_e = 0 +; variable_layer_height = 1 +; wipe = 1 +; wipe_into_infill = 0 +; wipe_into_objects = 0 +; wipe_tower = 1 +; wipe_tower_bridging = 10 +; wipe_tower_no_sparse_layers = 0 +; wipe_tower_rotation_angle = 0 +; wipe_tower_width = 60 +; wipe_tower_x = 170 +; wipe_tower_y = 125 +; wiping_volumes_extruders = 70,70 +; wiping_volumes_matrix = 0 +; xy_size_compensation = 0 +; z_offset = 0 diff --git a/08_3D_Printer/HX1K-Cube_0.2mm_PLA_MK3S_2h45m.gcode b/08_3D_Printer/HX1K-Cube_0.2mm_PLA_MK3S_2h45m.gcode new file mode 100644 index 0000000..4be7263 --- /dev/null +++ b/08_3D_Printer/HX1K-Cube_0.2mm_PLA_MK3S_2h45m.gcode @@ -0,0 +1,61582 @@ +; generated by PrusaSlicer 2.5.0+linux-x64-GTK3 on 2022-11-11 at 16:32:44 UTC + +; + +; external perimeters extrusion width = 0.45mm +; perimeters extrusion width = 0.45mm +; infill extrusion width = 0.45mm +; solid infill extrusion width = 0.45mm +; top infill extrusion width = 0.40mm +; first layer extrusion width = 0.42mm + +; external perimeters extrusion width = 0.45mm +; perimeters extrusion width = 0.45mm +; infill extrusion width = 0.45mm +; solid infill extrusion width = 0.45mm +; top infill extrusion width = 0.40mm +; first layer extrusion width = 0.42mm + +M73 P0 R165 +M73 Q0 S165 +M201 X1000 Y1000 Z200 E5000 ; sets maximum accelerations, mm/sec^2 +M203 X200 Y200 Z12 E120 ; sets maximum feedrates, mm / sec +M204 P1250 R1250 T1250 ; sets acceleration (P, T) and retract acceleration (R), mm/sec^2 +M205 X8.00 Y8.00 Z0.40 E4.50 ; sets the jerk limits, mm/sec +M205 S0 T0 ; sets the minimum extruding and travel feed rate, mm/sec +M107 +;TYPE:Custom +M862.3 P "MK3S" ; printer model check +M862.1 P0.4 ; nozzle diameter check +M115 U3.10.1 ; tell printer latest fw version +G90 ; use absolute coordinates +M83 ; extruder relative mode +M104 S215 ; set extruder temp +M140 S60 ; set bed temp +M190 S60 ; wait for bed temp +M109 S215 ; wait for extruder temp +G28 W ; home all without mesh bed level +G80 ; mesh bed leveling +G1 Y-3.0 F1000.0 ; go outside print area +G92 E0.0 +G1 X60.0 E9.0 F1000.0 ; intro line +G1 X100.0 E12.5 F1000.0 ; intro line +G92 E0.0 +M221 S95 + +; Don't change E values below. Excessive value can damage the printer. +M907 E430 ; set extruder motor current +G21 ; set units to millimeters +G90 ; use absolute coordinates +M83 ; use relative distances for extrusion +M900 K0.05 ; Filament gcode LA 1.5 +M900 K30 ; Filament gcode LA 1.0 +M107 +;LAYER_CHANGE +;Z:0.2 +;HEIGHT:0.2 +;BEFORE_LAYER_CHANGE +G92 E0.0 +;0.2 + + +G1 E-.8 F2100 +G1 Z.4 F10800 +;AFTER_LAYER_CHANGE +;0.2 +G1 X61.587 Y57.319 +G1 Z.2 +G1 E.8 F2100 +M204 S1000 +;TYPE:Skirt/Brim +;WIDTH:0.42 +G1 F1200 +G1 X62.319 Y56.587 E.03246 +G1 X63.385 Y55.972 E.03858 +G1 X64.385 Y55.704 E.03246 +G1 X65 Y55.623 E.01946 +G1 X185 Y55.623 E3.76252 +G1 X185.615 Y55.704 E.01946 +M73 P0 R164 +G1 X186.615 Y55.972 E.03246 +G1 X187.681 Y56.587 E.03858 +G1 X188.413 Y57.319 E.03246 +G1 X189.028 Y58.385 E.03858 +G1 X189.296 Y59.385 E.03246 +G1 X189.377 Y60 E.01946 +G1 X189.377 Y150 E2.82189 +G1 X189.296 Y150.615 E.01946 +G1 X189.028 Y151.615 E.03246 +G1 X188.413 Y152.681 E.03858 +G1 X187.681 Y153.413 E.03246 +G1 X186.615 Y154.028 E.03858 +G1 X185.615 Y154.296 E.03246 +G1 X185 Y154.377 E.01946 +G1 X65 Y154.377 E3.76252 +G1 X64.385 Y154.296 E.01946 +G1 X63.385 Y154.028 E.03246 +G1 X62.319 Y153.413 E.03858 +G1 X61.587 Y152.681 E.03246 +G1 X60.972 Y151.615 E.03858 +G1 X60.704 Y150.615 E.03246 +G1 X60.623 Y150 E.01946 +G1 X60.623 Y60 E2.82189 +G1 X60.704 Y59.385 E.01946 +G1 X60.972 Y58.385 E.03246 +G1 X61.557 Y57.371 E.0367 +; printing object front_HX1K-Cube.stl id:0 copy 0 +;WIPE_START +G1 F8640 +G1 X62.319 Y56.587 E-.25246 +G1 X63.385 Y55.972 E-.28411 +G1 X64.319 Y55.721 E-.22343 +;WIPE_END +G1 E-.04 F2100 +G1 Z.6 F10800 +G1 X128.974 Y59.407 +G1 Z.2 +G1 E.8 F2100 +;TYPE:Perimeter +;WIDTH:0.419999 +G1 F1200 +G1 X129.407 Y58.974 E.01924 +G1 X130.104 Y58.787 E.0226 +G1 X184.896 Y58.787 E1.71799 +G1 X185.593 Y58.974 E.0226 +G1 X186.026 Y59.407 E.01924 +G1 X186.213 Y60.104 E.0226 +G1 X186.213 Y149.896 E2.81538 +G1 X186.026 Y150.593 E.0226 +G1 X185.593 Y151.026 E.01924 +G1 X184.896 Y151.213 E.0226 +G1 X130.104 Y151.213 E1.71799 +G1 X129.407 Y151.026 E.0226 +G1 X128.974 Y150.593 E.01924 +G1 X128.787 Y149.896 E.0226 +G1 X128.787 Y60.104 E2.81538 +G1 X128.958 Y59.465 E.02072 +G1 X128.636 Y59.212 F10800 +;TYPE:External perimeter +G1 F1200 +G1 X129.212 Y58.636 E.02557 +G1 X130.054 Y58.41 E.02732 +G1 X184.946 Y58.41 E1.7211 +G1 X185.788 Y58.636 E.02732 +G1 X186.364 Y59.212 E.02557 +G1 X186.59 Y60.054 E.02732 +G1 X186.59 Y149.946 E2.8185 +G1 X186.364 Y150.788 E.02732 +G1 X185.788 Y151.364 E.02557 +G1 X184.946 Y151.59 E.02732 +G1 X130.054 Y151.59 E1.7211 +G1 X129.212 Y151.364 E.02732 +G1 X128.636 Y150.788 E.02557 +G1 X128.41 Y149.946 E.02732 +G1 X128.41 Y60.054 E2.8185 +G1 X128.62 Y59.27 E.02544 +M73 Q0 S164 +G1 X129.036 Y59.213 F10800 +;WIPE_START +G1 F8640 +G1 X129.212 Y58.636 E-.20043 +G1 X130.054 Y58.41 E-.20122 +G1 X131.606 Y58.41 E-.35835 +;WIPE_END +G1 E-.04 F2100 +G1 Z.6 F10800 +G1 X133.733 Y75.698 +G1 Z.2 +G1 E.8 F2100 +;TYPE:Perimeter +G1 F1200 +G1 X133.779 Y75.512 E.006 +G1 X133.939 Y75.326 E.00769 +G1 X134.203 Y75.218 E.00895 +G1 X134.279 Y75.213 E.00236 +G1 X180.721 Y75.213 E1.45618 +G1 X180.969 Y75.27 E.00798 +G1 X181.148 Y75.407 E.00704 +G1 X181.27 Y75.639 E.00824 +G1 X181.287 Y75.779 E.0044 +G1 X181.287 Y138.221 E1.95785 +G1 X181.221 Y138.488 E.0086 +G1 X181.061 Y138.674 E.00769 +G1 X180.797 Y138.782 E.00895 +G1 X180 Y138.787 E.02498 +G1 X134.279 Y138.787 E1.43356 +G1 X134.12 Y138.764 E.00502 +G1 X133.939 Y138.674 E.00634 +G1 X133.779 Y138.488 E.00769 +G1 X133.713 Y138.221 E.0086 +G1 X133.718 Y75.756 E1.95855 +G1 X134.09 Y75.779 F10800 +;TYPE:External perimeter +M73 P0 R163 +G1 F1200 +G1 X134.136 Y75.655 E.00415 +G1 X134.279 Y75.59 E.00489 +G1 X180.721 Y75.59 E1.45618 +G1 X180.864 Y75.655 E.00489 +G1 X180.91 Y75.779 E.00415 +G1 X180.91 Y138.221 E1.95785 +G1 X180.863 Y138.345 E.00415 +G1 X180.721 Y138.41 E.00489 +G1 X134.279 Y138.41 E1.45618 +G1 X134.226 Y138.402 E.00167 +G1 X134.112 Y138.31 E.00459 +G1 X134.09 Y138.221 E.00287 +G1 X134.09 Y75.839 E1.95597 +G1 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object rear_HX1K-Cube.stl id:1 copy 0 +G1 X64.846 Y150.21 +G1 Z20 +G1 E.8 F2100 +M204 S800 +;WIDTH:0.52146 +G1 F1500 +G1 X65.066 Y150.261 E.00897 +G1 X73.239 Y150.261 E.32523 +G1 X73.239 Y150.739 E.01904 +G1 X65.066 Y150.739 E.32523 +G1 X64.632 Y150.638 E.01774 +;WIDTH:0.508968 +G1 X64.362 Y150.368 E.01477 +;WIDTH:0.521462 +G1 X64.261 Y149.966 E.01652 +G1 X64.261 Y60.034 E3.57845 +;WIDTH:0.521461 +G1 X64.362 Y59.632 E.01652 +;WIDTH:0.508968 +G1 X64.632 Y59.362 E.01477 +;WIDTH:0.521454 +G1 X65.066 Y59.261 E.01774 +G1 X119.955 Y59.265 E2.18404 +;WIDTH:0.51878 +G1 X120.368 Y59.362 E.01682 +;WIDTH:0.508967 +G1 X120.638 Y59.632 E.01477 +;WIDTH:0.52146 +G1 X120.739 Y60.034 E.01652 +G1 X120.739 Y149.934 E3.57718 +G1 X120.638 Y150.368 E.01774 +;WIDTH:0.508968 +G1 X120.368 Y150.638 E.01477 +;WIDTH:0.521459 +G1 X119.966 Y150.739 E.01652 +G1 X82.761 Y150.739 E1.48041 +G1 X82.761 Y150.261 E.01904 +G1 X119.934 Y150.261 E1.47916 +G1 X120.081 Y150.243 E.00588 +;WIDTH:0.508967 +G1 X120.225 Y150.135 E.007 +;WIDTH:0.52146 +G1 X120.261 Y149.934 E.0081 +G1 X120.261 Y60.066 E3.57593 +G1 X120.243 Y59.919 E.00588 +;WIDTH:0.508963 +G1 X120.135 Y59.775 E.007 +;WIDTH:0.51878 +G1 X119.954 Y59.741 E.00725 +;WIDTH:0.521454 +G1 X65.066 Y59.739 E2.18404 +G1 X64.919 Y59.757 E.00588 +;WIDTH:0.503441 +G1 X64.79 Y59.846 E.00601 +;WIDTH:0.521462 +G1 X64.739 Y60.066 E.00897 +G1 X64.739 Y149.934 E3.57595 +G1 X64.757 Y150.081 E.00588 +;WIDTH:0.503443 +G1 X64.812 Y150.161 E.00372 +M204 S1000 +; stop printing object rear_HX1K-Cube.stl id:1 copy 0 +;WIPE_START +G1 F8640;_WIPE +G1 X65.066 Y150.261 E-.06297 +G1 F8640;_WIPE +G1 X68.085 Y150.261 E-.69703 +;WIPE_END +G1 E-.04 F2100 +G1 Z20.4 F10800 +M107 +;TYPE:Custom +; Filament-specific end gcode +G4 ; wait +M221 S100 ; reset flow +M900 K0 ; reset LA +M907 E538 ; reset extruder motor current +M104 S0 ; turn off temperature +M140 S0 ; turn off heatbed +M107 ; turn off fan +G1 Z50 ; Move print head up +G1 X0 Y200 F3000 ; home X axis +M84 ; disable motors +M73 P100 R0 +M73 Q100 S0 +; filament used [mm] = 12486.54 +; filament used [cm3] = 30.03 +; filament used [g] = 37.24 +; filament cost = 0.95 +; total filament used [g] = 37.24 +; total filament cost = 0.95 +; estimated printing time (normal mode) = 2h 45m 8s +; estimated printing time (silent mode) = 2h 45m 58s + +; prusaslicer_config = begin +; avoid_crossing_perimeters = 0 +; avoid_crossing_perimeters_max_detour = 0 +; bed_custom_model = +; bed_custom_texture = +; bed_shape = 0x0,250x0,250x210,0x210 +; bed_temperature = 60 +; before_layer_gcode = ;BEFORE_LAYER_CHANGE\nG92 E0.0\n;[layer_z]\n\n +; between_objects_gcode = +; bottom_fill_pattern = monotonic +; bottom_solid_layers = 4 +; bottom_solid_min_thickness = 0.5 +; bridge_acceleration = 1000 +; bridge_angle = 0 +; bridge_fan_speed = 100 +; bridge_flow_ratio = 0.95 +; bridge_speed = 30 +; brim_separation = 0 +; brim_type = outer_only +; brim_width = 0 +; clip_multipart_objects = 1 +; color_change_gcode = M600\nG1 E0.4 F1500 ; prime after color change +; compatible_printers_condition_cummulative = "printer_notes=~/.*PRINTER_VENDOR_PRUSA3D.*/ and printer_notes=~/.*PRINTER_MODEL_MK3.*/ and nozzle_diameter[0]==0.4";"nozzle_diameter[0]!=0.8 and ! (printer_notes=~/.*PRINTER_VENDOR_PRUSA3D.*/ and printer_notes=~/.*PRINTER_MODEL_MK(2.5|3).*/ and single_extruder_multi_material)" +; complete_objects = 0 +; cooling = 1 +; cooling_tube_length = 5 +; cooling_tube_retraction = 91.5 +; default_acceleration = 1000 +; default_filament_profile = "Prusament PLA" +; default_print_profile = 0.15mm QUALITY @MK3 +; deretract_speed = 0 +; disable_fan_first_layers = 1 +; dont_support_bridges = 1 +; draft_shield = disabled +; duplicate_distance = 6 +; elefant_foot_compensation = 0.2 +; end_filament_gcode = "; Filament-specific end gcode" +; end_gcode = G4 ; wait\nM221 S100 ; reset flow\nM900 K0 ; reset LA\n{if print_settings_id=~/.*(DETAIL @MK3|QUALITY @MK3|@0.25 nozzle MK3).*/}M907 E538 ; reset extruder motor current{endif}\nM104 S0 ; turn off temperature\nM140 S0 ; turn off heatbed\nM107 ; turn off fan\n{if max_layer_z < max_print_height}G1 Z{z_offset+min(max_layer_z+30, max_print_height)}{endif} ; Move print head up\nG1 X0 Y200 F3000 ; home X axis\nM84 ; disable motors +; ensure_vertical_shell_thickness = 1 +; external_perimeter_extrusion_width = 0.45 +; external_perimeter_speed = 25 +; external_perimeters_first = 0 +; extra_loading_move = -2 +; extra_perimeters = 0 +; extruder_clearance_height = 20 +; extruder_clearance_radius = 45 +; extruder_colour = "" +; extruder_offset = 0x0 +; extrusion_axis = E +; extrusion_multiplier = 1 +; extrusion_width = 0.45 +; fan_always_on = 1 +; fan_below_layer_time = 100 +; filament_colour = #FF8000 +; filament_cooling_final_speed = 3.4 +; filament_cooling_initial_speed = 2.2 +; filament_cooling_moves = 4 +; filament_cost = 25.4 +; filament_density = 1.24 +; filament_diameter = 1.75 +; filament_load_time = 0 +; filament_loading_speed = 28 +; filament_loading_speed_start = 3 +; filament_max_volumetric_speed = 15 +; filament_minimal_purge_on_wipe_tower = 15 +; filament_notes = "" +; filament_ramming_parameters = "120 100 6.6 6.8 7.2 7.6 7.9 8.2 8.7 9.4 9.9 10.0| 0.05 6.6 0.45 6.8 0.95 7.8 1.45 8.3 1.95 9.7 2.45 10 2.95 7.6 3.45 7.6 3.95 7.6 4.45 7.6 4.95 7.6" +; filament_settings_id = "Generic PLA" +; filament_soluble = 0 +; filament_spool_weight = 0 +; filament_toolchange_delay = 0 +; filament_type = PLA +; filament_unload_time = 0 +; filament_unloading_speed = 90 +; filament_unloading_speed_start = 100 +; filament_vendor = Generic +; fill_angle = 45 +; fill_density = 15% +; fill_pattern = gyroid +; first_layer_acceleration = 1000 +; first_layer_acceleration_over_raft = 0 +; first_layer_bed_temperature = 60 +; first_layer_extrusion_width = 0.42 +; first_layer_height = 0.2 +; first_layer_speed = 20 +; first_layer_speed_over_raft = 30 +; first_layer_temperature = 215 +; full_fan_speed_layer = 4 +; fuzzy_skin = none +; fuzzy_skin_point_dist = 0.8 +; fuzzy_skin_thickness = 0.3 +; gap_fill_enabled = 1 +; gap_fill_speed = 40 +; gcode_comments = 0 +; gcode_flavor = marlin +; gcode_label_objects = 1 +; gcode_resolution = 0.0125 +; gcode_substitutions = +; high_current_on_filament_swap = 0 +; host_type = octoprint +; infill_acceleration = 1000 +; infill_anchor = 2.5 +; infill_anchor_max = 12 +; infill_every_layers = 1 +; infill_extruder = 1 +; infill_extrusion_width = 0.45 +; infill_first = 0 +; infill_only_where_needed = 0 +; infill_overlap = 25% +; infill_speed = 80 +; interface_shells = 0 +; ironing = 0 +; ironing_flowrate = 15% +; ironing_spacing = 0.1 +; ironing_speed = 15 +; ironing_type = top +; layer_gcode = ;AFTER_LAYER_CHANGE\n;[layer_z] +; layer_height = 0.2 +; machine_limits_usage = emit_to_gcode +; machine_max_acceleration_e = 5000,5000 +; machine_max_acceleration_extruding = 1250,1250 +; machine_max_acceleration_retracting = 1250,1250 +; machine_max_acceleration_travel = 1500,1250 +; machine_max_acceleration_x = 1000,960 +; machine_max_acceleration_y = 1000,960 +; machine_max_acceleration_z = 200,200 +; machine_max_feedrate_e = 120,120 +; machine_max_feedrate_x = 200,100 +; machine_max_feedrate_y = 200,100 +; machine_max_feedrate_z = 12,12 +; machine_max_jerk_e = 4.5,4.5 +; machine_max_jerk_x = 8,8 +; machine_max_jerk_y = 8,8 +; machine_max_jerk_z = 0.4,0.4 +; machine_min_extruding_rate = 0,0 +; machine_min_travel_rate = 0,0 +; max_fan_speed = 100 +; max_layer_height = 0.25 +; max_print_height = 210 +; max_print_speed = 200 +; max_volumetric_extrusion_rate_slope_negative = 0 +; max_volumetric_extrusion_rate_slope_positive = 0 +; max_volumetric_speed = 0 +; min_bead_width = 85% +; min_fan_speed = 100 +; min_feature_size = 25% +; min_layer_height = 0.07 +; min_print_speed = 15 +; min_skirt_length = 4 +; mmu_segmented_region_max_width = 0 +; notes = +; nozzle_diameter = 0.4 +; only_retract_when_crossing_perimeters = 0 +; ooze_prevention = 0 +; output_filename_format = {input_filename_base}_{layer_height}mm_{filament_type[0]}_{printer_model}_{print_time}.gcode +; overhangs = 0 +; parking_pos_retraction = 92 +; pause_print_gcode = M601 +; perimeter_acceleration = 800 +; perimeter_extruder = 1 +; perimeter_extrusion_width = 0.45 +; perimeter_generator = arachne +; perimeter_speed = 45 +; perimeters = 2 +; physical_printer_settings_id = +; post_process = +; print_settings_id = 0.20mm QUALITY @MK3 +; printer_model = MK3S +; printer_notes = Don't remove the following keywords! These keywords are used in the "compatible printer" condition of the print and filament profiles to link the particular print and filament profiles to this printer profile.\nPRINTER_VENDOR_PRUSA3D\nPRINTER_MODEL_MK3\n +; printer_settings_id = Original Prusa i3 MK3S & MK3S+ +; printer_technology = FFF +; printer_variant = 0.4 +; printer_vendor = +; raft_contact_distance = 0.1 +; raft_expansion = 1.5 +; raft_first_layer_density = 90% +; raft_first_layer_expansion = 3 +; raft_layers = 0 +; remaining_times = 1 +; resolution = 0 +; retract_before_travel = 1 +; retract_before_wipe = 0% +; retract_layer_change = 1 +; retract_length = 0.8 +; retract_length_toolchange = 4 +; retract_lift = 0.4 +; retract_lift_above = 0 +; retract_lift_below = 209 +; retract_restart_extra = 0 +; retract_restart_extra_toolchange = 0 +; retract_speed = 35 +; seam_position = nearest +; silent_mode = 1 +; single_extruder_multi_material = 0 +; single_extruder_multi_material_priming = 0 +; skirt_distance = 2 +; skirt_height = 3 +; skirts = 1 +; slice_closing_radius = 0.049 +; slicing_mode = regular +; slowdown_below_layer_time = 15 +; small_perimeter_speed = 25 +; solid_infill_below_area = 0 +; solid_infill_every_layers = 0 +; solid_infill_extruder = 1 +; solid_infill_extrusion_width = 0.45 +; solid_infill_speed = 80 +; spiral_vase = 0 +; standby_temperature_delta = -5 +; start_filament_gcode = "M900 K{if printer_notes=~/.*PRINTER_MODEL_MINI.*/ and nozzle_diameter[0]==0.6}0.12{elsif printer_notes=~/.*PRINTER_MODEL_MINI.*/ and nozzle_diameter[0]==0.8}0.06{elsif printer_notes=~/.*PRINTER_MODEL_MINI.*/}0.2{elsif nozzle_diameter[0]==0.8}0.01{elsif nozzle_diameter[0]==0.6}0.04{else}0.05{endif} ; Filament gcode LA 1.5\n{if printer_notes=~/.*PRINTER_MODEL_MINI.*/};{elsif printer_notes=~/.*PRINTER_HAS_BOWDEN.*/}M900 K200{elsif nozzle_diameter[0]==0.6}M900 K18{elsif nozzle_diameter[0]==0.8};{else}M900 K30{endif} ; Filament gcode LA 1.0" +; start_gcode = M862.3 P "[printer_model]" ; printer model check\nM862.1 P[nozzle_diameter] ; nozzle diameter check\nM115 U3.10.1 ; tell printer latest fw version\nG90 ; use absolute coordinates\nM83 ; extruder relative mode\nM104 S[first_layer_temperature] ; set extruder temp\nM140 S[first_layer_bed_temperature] ; set bed temp\nM190 S[first_layer_bed_temperature] ; wait for bed temp\nM109 S[first_layer_temperature] ; wait for extruder temp\nG28 W ; home all without mesh bed level\nG80 ; mesh bed leveling\nG1 Y-3.0 F1000.0 ; go outside print area\nG92 E0.0\nG1 X60.0 E9.0 F1000.0 ; intro line\nG1 X100.0 E12.5 F1000.0 ; intro line\nG92 E0.0\nM221 S{if layer_height<0.075}100{else}95{endif}\n\n; Don't change E values below. Excessive value can damage the printer.\n{if print_settings_id=~/.*(DETAIL @MK3|QUALITY @MK3).*/}M907 E430 ; set extruder motor current{endif}\n{if print_settings_id=~/.*(SPEED @MK3|DRAFT @MK3).*/}M907 E538 ; set extruder motor current{endif} +; support_material = 0 +; support_material_angle = 0 +; support_material_auto = 1 +; support_material_bottom_contact_distance = 0 +; support_material_bottom_interface_layers = -1 +; support_material_buildplate_only = 0 +; support_material_closing_radius = 2 +; support_material_contact_distance = 0.1 +; support_material_enforce_layers = 0 +; support_material_extruder = 0 +; support_material_extrusion_width = 0.35 +; support_material_interface_contact_loops = 0 +; support_material_interface_extruder = 0 +; support_material_interface_layers = 2 +; support_material_interface_pattern = rectilinear +; support_material_interface_spacing = 0.2 +; support_material_interface_speed = 80% +; support_material_pattern = rectilinear +; support_material_spacing = 2 +; support_material_speed = 50 +; support_material_style = grid +; support_material_synchronize_layers = 0 +; support_material_threshold = 55 +; support_material_with_sheath = 0 +; support_material_xy_spacing = 50% +; temperature = 210 +; template_custom_gcode = +; thick_bridges = 1 +; thin_walls = 0 +; threads = 16 +; thumbnails = +; thumbnails_format = PNG +; toolchange_gcode = +; top_fill_pattern = monotonic +; top_infill_extrusion_width = 0.4 +; top_solid_infill_speed = 40 +; top_solid_layers = 5 +; top_solid_min_thickness = 0.7 +; travel_speed = 180 +; travel_speed_z = 0 +; use_firmware_retraction = 0 +; use_relative_e_distances = 1 +; use_volumetric_e = 0 +; variable_layer_height = 1 +; wall_distribution_count = 1 +; wall_transition_angle = 10 +; wall_transition_filter_deviation = 25% +; wall_transition_length = 100% +; wipe = 1 +; wipe_into_infill = 0 +; wipe_into_objects = 0 +; wipe_tower = 1 +; wipe_tower_bridging = 10 +; wipe_tower_brim_width = 2 +; wipe_tower_no_sparse_layers = 0 +; wipe_tower_rotation_angle = 0 +; wipe_tower_width = 60 +; wipe_tower_x = 170 +; wipe_tower_y = 125 +; wiping_volumes_extruders = 70,70 +; wiping_volumes_matrix = 0 +; xy_size_compensation = 0 +; z_offset = 0 +; prusaslicer_config = end diff --git a/08_3D_Printer/Readme.md b/08_3D_Printer/Readme.md new file mode 100644 index 0000000..f6d2c54 --- /dev/null +++ b/08_3D_Printer/Readme.md @@ -0,0 +1,8 @@ +# 3D printed case + +Finally we print case with a 3d-Printer. All the parts are modelled with free software tools. + +- [blender](https://blender.org) is a very powerfull 3D modelling software. All parts of the cube are modelled with blender. You can edit the blender files and change details on the design. The blender-design files can than be exported to STL-format, a common 3D-file format used for 3D-printing. +- [prusa-slic3r](https://www.prusa3d.com). This is the slicer software for 3D-Printers from the manufacturer Prusa. This programm is used to convert the STL-files to printerspecific gcode-files. + +The subfolder `files/` containes the blender files, the corresponging STL-files and the already sliced gcodes for Prusa-MK3S printer. diff --git a/08_3D_Printer/Readme.md.backup b/08_3D_Printer/Readme.md.backup new file mode 100644 index 0000000..d9bef9b --- /dev/null +++ b/08_3D_Printer/Readme.md.backup @@ -0,0 +1,25 @@ +# 3D printed case + +Finally we print case with a 3d-Printer. All the parts are modelled with free software tools. + +- [blender](https://blender.org) is a very powerfull 3D modelling software. All parts of the cube are modelled with blender. You can edit the blender files and change details on the design. The blender-design files can than be exported to STL-format, a common 3D-file format used for 3D-printing. +- [prusa-slic3r](https://www.prusa3d.com). This is the slicer software for 3D-Printers from the manufacturer Prusa. This programm is used to convert the STL-files to printerspecific gcode-files. + +The subfolder `files/` containes the blender files, the corresponging STL-files and the already sliced gcodes for Prusa-MK3S printer. + + +### inside +A look inide: All the modules fit nicely inside. +![](pics/cube_inside.jpg) + +### rear +On the rear cover you see connectors for power supply (5V), RJ45 Ethernet connector and the USB connector which has dual usage: +1. upload bitstream files to iCE40 fpga +2. communicate to Hack-Computer over UART +![](pics/cube_rear.jpg) + +### front + +On the front side you see the screen (MOD-LCD2.8RTP) and a slit to insert the SD-card. +![](pics/cube_front.jpg) + diff --git a/08_3D_Printer/front_HX1K-Cube.stl b/08_3D_Printer/front_HX1K-Cube.stl new file mode 100644 index 0000000..e76a492 Binary files /dev/null and b/08_3D_Printer/front_HX1K-Cube.stl differ diff --git a/08_3D_Printer/front_HX1K.blend b/08_3D_Printer/front_HX1K.blend new file mode 100644 index 0000000..029bce4 Binary files /dev/null and b/08_3D_Printer/front_HX1K.blend differ diff --git a/08_3D_Printer/front_HX1K.blend1 b/08_3D_Printer/front_HX1K.blend1 new file mode 100644 index 0000000..cef7f5d Binary files /dev/null and b/08_3D_Printer/front_HX1K.blend1 differ diff --git a/08_3D_Printer/nothing.blend b/08_3D_Printer/nothing.blend new file mode 100644 index 0000000..a5fe88d Binary files /dev/null and b/08_3D_Printer/nothing.blend differ diff --git a/08_3D_Printer/rear_HX1K-Cube.stl b/08_3D_Printer/rear_HX1K-Cube.stl new file mode 100644 index 0000000..e305c0f Binary files /dev/null and b/08_3D_Printer/rear_HX1K-Cube.stl differ diff --git a/08_3D_Printer/rear_HX1K.blend b/08_3D_Printer/rear_HX1K.blend new file mode 100644 index 0000000..d8f86ec Binary files /dev/null and b/08_3D_Printer/rear_HX1K.blend differ diff --git a/08_3D_Printer/rear_HX1K.blend1 b/08_3D_Printer/rear_HX1K.blend1 new file mode 100644 index 0000000..38f6f4c Binary files /dev/null and b/08_3D_Printer/rear_HX1K.blend1 differ diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..3cbc930 --- /dev/null +++ b/LICENSE @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. We, the Free Software Foundation, use the +GNU General Public License for most of our software; it applies also to +any other work released this way by its authors. You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +them if you wish), that you receive source code or can get it if you +want it, that you can change the software or use pieces of it in new +free programs, and that you know you can do these things. + + To protect your rights, we need to prevent others from denying you +these rights or asking you to surrender the rights. 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It is safest +to attach them to the start of each source file to most effectively +state the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + nand2tetris-13 + Copyright (C) 2020 Michael Schröder + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + nand2tetris-13 Copyright (C) 2020 Michael Schröder + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/Readme.md b/Readme.md index e69de29..56babe6 100644 --- a/Readme.md +++ b/Readme.md @@ -0,0 +1,107 @@ +# nand2tetris-FPGA (v2.0) + +> ... _Would'nt it be nice to make Hack or Jack also run on some "real platform," made from some "real stuff"?_ ... +> +> ---Noam Nisan and Shimon Schocken + +This project is about building HACK on real hardware as proposed in Chapter 13 of the course [nand2tetris](https://www.nand2tetris.org/) using only FOSS, free and open source hard- and software. + + ![](doc/inside.jpg) + +Our final implementation of HACK will have the following specs: + +* original CPU/ALU design of HACK from nand2tetris + +* implemented on iCE40HX1K-EVB from Olimex + +* clocked at 25 MHz + +* RAM 3840 x 16 bit (R0-R15/static/stack/heap) + +* SRAM 64K x 16 bit (instruction memory) + +* bootloader boots HACK-code from SPI-Flash into SRAM + +* 2.8 inch color LCD with 320x240 pixel + +* touch-panel support + +* powerfull enough to run Tetris! + + ![](doc/tetris2.jpg) + +*** + +## Roadmap + +In every project folder you find a file `Readme.md` containing specifications and implementation details. + +> _... This is your last chance. After this, there is no turning back. You take the blue pill — the story ends, you wake up in your bed and believe whatever you want to believe. You take the red pill — you stay in Wonderland and I show you how deep the rabbit-hole goes. ..._ +> +> ---Morpheus + +### [00 Requirement](00_Requirement) + +Get the hardware and install the tools. + +### [01 Boolean Logic](01_Boolean_Logic) + +Start with a simple `Nand` gate and build the logic chips: `Not`, `Buffer`, `And`, `Or`, `Xor`, `Mux`, `DMux`, and theire multibit versions `Not16`, `Buffer16`, `And16`, `Or16`, `Mux16`, `Or8Way`, `Mux4Way16`, `Mux8Way16`, `DMux4Way` and `DMux8Way`. + +### [02 Boolean Arithmetic](02_Boolean_Arithmetic) + +Proceed and build `HalfAdder`, `FullAdder`, `Add16`, `Inc16` and the `ALU`. + +### [03 Sequential Logic](03_Sequential_Logic) + +Build sequential chips `Bit` , `Register` and `PC`, that make use of the data flip flop (DFF) to store the state. `DFF` is considered primitive, so it's not necessary to implement it. The memory chips `RAM512` and `RAM3840` are based on the primitive `RAM256`, which uses block ram structures integrated in iCE40HX1K. `BitShift9R` and `BitShift8L` are new chips not explained in the original nand2tetris course. They serve to connect HACK to different IO-Devices, which are connected using a serial protocol, where data is transmitted bitwise. + +### [04 Machine Language](04_Machine_Language) + +Write two little machine language programms to run on HACK. The first programm `leds.asm` will test I/O capability of HACK. Every time the user presses the buttons BUT1/2 on the iCE40HX1K-EVB board the LEDs will change accordingly. With the second programm `mult.asm` we will calculate the product of two numbers to test the arithmetic capabilities of the CPU/ALU. + +### [05 Computer Architecture](05_Computer_Architecture) + +Build `HACK` computer system consisting of the chips `CPU`, `Memory`, `Clock25_Reset20`, `RAM` and `ROM`. `ROM` uses a block ram structure (256 words) of iCE40HX1K and can be considered primitive. It can be preloaded with the instructions of the assembler programs implemented in `04_Machine_Language` . + +### [06 IO Devices](06_IO_Devices) + +We will expand HACK computer platform by adding chips to handle communication to I/O devices, which we connect to HACK. + +* UART communicates with 115200 baud 8N1 to computer +* SPI reads the 2MByte flash memory on iCE40HX1K-EVB +* SRAM writes data to the external SRAM chip +* GO enables booting JACK-OS software +* LCD connects a little color screen with 320x240 pixel +* RTP connects the resistive touch panel + +### [07 Operating System](07_Operating_System) + +Implement the operating system JACK-OS, written in the high level language JACK consisting of the classes `GPIO.jack`, `UART.jack`, `Memory.jack`, `Math.jack`, `Array.jack`, `String.jack`, `Screen.jack`, `Output.jack`, `Touch.jack` and `Sys.jack` + +Finally you can compile and run Tetris! + +### [08 3D Printer](08_3D_Printer) + +We provide construction files to print a little case for your HACK computer with a 3D-Printer. The case is designed with FOSS software blender. + +## Credits + +* Noam Nisan and Shimon Schocken, "The Elements of Computing Systems", MIT Press + +* Noam Nisan and Shimon Schocken: Visit [nand2tetris](https://nand2tetris.org) and learn to build a modern general-purpose computer system from ground up. + +* [Olimex Ltd](https://www.olimex.com/): Buy your hardware from the Company with highest number of registered OSHW projects :) + +* Wolf Clifford: The master of open source FPGA with iCE40 and [Project IceStorm](http://www.clifford.at/icestorm/) + +* Jesús Arroyo Torrens, Juan González (Obijuan): Open source ecosystem for open FPGA boards [APIO](https://github.com/FPGAwars/apio) + +* Juan González-Gomez (Obijuan): Lern verilog with [open-fpga-verilog-tutorial](https://github.com/Obijuan/open-fpga-verilog-tutorial/), best tutorial! + +* Icons made by Those Icons from www.flaticon.com + +--- + +For questions or comments write an email to +mi.schroeder@netcologne.de diff --git a/Revision.md b/Revision.md new file mode 100644 index 0000000..9d5c220 --- /dev/null +++ b/Revision.md @@ -0,0 +1,30 @@ +# Revision V2.0 + +## update 18.10.2022 + +### correct typos: +* `Hack/CPU.v`: Replace `loadM` with `writeM` +* update diagramms + +### update tools to python3.10: +* `tools/Assembler/assembler.pyc`: update tools to python 3.10 +* `tools/Jack/JackCompiler.pyc`: update tools to python 3.10 +* `tools/Jack/VMTranslator.pyc`: update tools to python 3.10 + +### update Jack-OS: +* `Jack/UART.jack`: replace `init()` with `init(int addr)` + +### wierd behaviour of iCE40HX8K-EVB: + +* `Hack/RAM.v`: replace `always @(negedge clk)` to `always @(posedge clk)` +* `Hack/DFF.v`: replace `always @(negedge clk)` to `always @(posedge clk)` +* `Hack/Clock.v`: 25MHz? + +### iceprog: programmer.ino +* set default to `bridge` (led green on). + +### consistency: +* `Hack/Reset.v`: + +### boot from spi +* 04_Hack-FLASH diff --git a/doc/AR1000.pdf b/doc/AR1000.pdf new file mode 100644 index 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+ sys.exit(0) + +fbin=open(sys.argv[1].replace('.hack','.bin'),'w+b') +fhack=open(sys.argv[1],'r') +lines=fhack.readlines() +for line in lines: + binary=int(line.strip(),2) + byte=bytearray([(binary>>8),binary&0xff]) + fbin.write(byte) diff --git a/tools/Assembler/assembler.pyc b/tools/Assembler/assembler.pyc new file mode 100755 index 0000000..49e4a7d Binary files /dev/null and b/tools/Assembler/assembler.pyc differ diff --git a/tools/Assembler/code.pyc b/tools/Assembler/code.pyc new file mode 100644 index 0000000..5d6635c Binary files /dev/null and b/tools/Assembler/code.pyc differ diff --git a/tools/Assembler/parser.pyc b/tools/Assembler/parser.pyc new file mode 100644 index 0000000..0ed86ef Binary files /dev/null and b/tools/Assembler/parser.pyc differ diff --git a/tools/Assembler/symbolTable.pyc b/tools/Assembler/symbolTable.pyc new file mode 100644 index 0000000..6897c99 Binary files /dev/null and b/tools/Assembler/symbolTable.pyc differ diff --git a/tools/JackCompiler/CompilationEngine.pyc b/tools/JackCompiler/CompilationEngine.pyc new file mode 100644 index 0000000..984b580 Binary files /dev/null and b/tools/JackCompiler/CompilationEngine.pyc differ diff --git a/tools/JackCompiler/JackAnalyser.pyc b/tools/JackCompiler/JackAnalyser.pyc new file mode 100755 index 0000000..d589e74 Binary files /dev/null and b/tools/JackCompiler/JackAnalyser.pyc differ diff --git a/tools/JackCompiler/JackCompiler.pyc b/tools/JackCompiler/JackCompiler.pyc new file mode 100755 index 0000000..88b00ae Binary files /dev/null and b/tools/JackCompiler/JackCompiler.pyc differ diff --git a/tools/JackCompiler/JackTokenizer.pyc b/tools/JackCompiler/JackTokenizer.pyc new file mode 100644 index 0000000..b2d2d1e Binary files /dev/null and b/tools/JackCompiler/JackTokenizer.pyc differ diff --git a/tools/JackCompiler/SymbolTable.pyc b/tools/JackCompiler/SymbolTable.pyc new file mode 100644 index 0000000..a4e557c Binary files /dev/null and b/tools/JackCompiler/SymbolTable.pyc differ diff --git a/tools/JackCompiler/VMCodeWriter.pyc b/tools/JackCompiler/VMCodeWriter.pyc new file mode 100644 index 0000000..723f542 Binary files /dev/null and b/tools/JackCompiler/VMCodeWriter.pyc differ diff --git a/tools/Readme.md b/tools/Readme.md new file mode 100644 index 0000000..65f5972 --- /dev/null +++ b/tools/Readme.md @@ -0,0 +1,55 @@ +# tools + +This folder contains the toolchain for Hack/Jack development. + +## vim + +vim configuration file to highlight syntax of jack/hack-files, when editing with vim. Copy the content of the subfolders into the appropriate vim configuration directory situated in your home directory `~/.vim`. + +``` +$ cp vim/syntax/* ~/.vim/syntax/ +$ cp vim/ftdetect/* ~/.vim/ftdetect/ +``` + +## Assembler + +Assembler translates Hack-Assembly-files to Machnine-code. Outputs the machine code to filename.hack. + +`usage: ./Assembler/assembler.pyc [filename.asm]` + +## JackCompiler + +Compiles Jack classes (single file or all *.jack files in directory) to virtualmachine code. + +`usage: ./JackCompiler/JackCompiler.pyc [filename.jack] or [dir]` + +## VMTranslator + +Translates vm code (single file or all files with ending *.vm in directory)to Assembler. + +`usage: ./VMTranslator/VMTranslator.pyc [filename.vm] or [dir]` + +## AsciiToBin.py + +Translates .hack files to binary files that can be uploaded with iecprogduino. + +`usage: ./AsciiToBin.py [filename.hack]` + +## iceprogduino + +iceprogduino is the programmer to upload bitstream files to iCE40 boards of olimex over olimexino-32u4 (arduino like board). + +For this you first have to upload firmware to olimexino-32u4. + +iceprogduino is supportes from apio (fpgawars) + +connect: + +1. ice40-HX1/8K-EVB to olimexino-32u4 (over UEXT) +2. olimexino-32u4 (with installed firmware) to PC over USB. + +## olimexino-32u4-firmware + +Firmware to run olimexino-32u4 as programmer/UART bridge. + +# diff --git a/tools/VMTranslator/VMTranslator.pyc b/tools/VMTranslator/VMTranslator.pyc new file mode 100755 index 0000000..8cc497a Binary files /dev/null and b/tools/VMTranslator/VMTranslator.pyc differ diff --git a/tools/VMTranslator/codeWriter.pyc b/tools/VMTranslator/codeWriter.pyc new file mode 100644 index 0000000..25ced8c Binary files /dev/null and b/tools/VMTranslator/codeWriter.pyc differ diff --git a/tools/VMTranslator/parser.pyc b/tools/VMTranslator/parser.pyc new file mode 100644 index 0000000..644ac75 Binary files /dev/null and b/tools/VMTranslator/parser.pyc differ diff --git a/tools/iceprogduino/Makefile b/tools/iceprogduino/Makefile new file mode 100644 index 0000000..b5e99dd --- /dev/null +++ b/tools/iceprogduino/Makefile @@ -0,0 +1,17 @@ +CC = gcc +CFLAG = -c -Wall +EXECUTE = iceprogduino +NAME = iceprogduino + +all: $(EXECUTE) + +$(EXECUTE): $(NAME).o + $(CC) $(NAME).o -o $(EXECUTE) + +clean: + rm -rf *.o $(EXECUTE) + +install: + cp $(EXECUTE) /usr/local/bin/$(EXECUTE) + + diff --git a/tools/iceprogduino/iceprogduino b/tools/iceprogduino/iceprogduino new file mode 100755 index 0000000..e551dc9 Binary files /dev/null and b/tools/iceprogduino/iceprogduino differ diff --git a/tools/iceprogduino/iceprogduino.c b/tools/iceprogduino/iceprogduino.c new file mode 100644 index 0000000..f56a574 --- /dev/null +++ b/tools/iceprogduino/iceprogduino.c @@ -0,0 +1,824 @@ +/* + * iceprogduino -- simple programming tool for FTDI-based Lattice iCE programmers + * and Olinuxino based programmers for iCE40HX1K-EVB + * + * Copyright (C) 2015 Clifford Wolf + * Olimexino Nano edition by Chris B. @ Olimex Ltd. 2016 + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Relevant Documents: + * ------------------- + * http://www.latticesemi.com/~/media/Documents/UserManuals/EI/icestickusermanual.pdf + * http://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_32mb_3v_65nm.pdf + * https://www.olimex.com/ iCE40HX1K-EVB + */ + +//#define Olinuxino +//#define FTDI +#define Nano + +#define READ_ID 0x9F +#define PWR_UP 0xAB +#define PWR_DOWN 0xB9 +#define WR_EN 0x06 +#define BULK_ERASE 0xC7 +#define SEC_ERASE 0xd8 +#define PROG 0x02 +#define READ 0x03 +#define READY 0x44 +#define READ_ALL 0x83 +#define EMPTY 0x45 + + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#pragma GCC diagnostic ignored "-Wdeprecated-declarations" + + + + + +void serial_read(int x); + +#define FEND 0xc0 +#define FESC 0xdb +#define TFEND 0xdc +#define TFESC 0xdd +bool newframe; +bool timeout; +bool escaped; +#include +#define SerialPort "/dev/ttyACM0" +int fd; +uint8_t rxframe[512], txframe[512], fcs, tfcs; +uint16_t txp,rxp; +uint8_t membuf[0x200000]; +uint8_t pages[0x2000]; + + + + + + +bool verbose = false; + + + + + + +int set_interface_attribs (int fd, int speed, int parity) +{ + struct termios tty; + memset (&tty, 0, sizeof tty); + if (tcgetattr (fd, &tty) != 0) + { + fprintf(stderr,"error %d from tcgetattr", errno); + return -1; + } + + cfsetospeed (&tty, speed); + cfsetispeed (&tty, speed); + + tty.c_cflag = (tty.c_cflag & ~CSIZE) | CS8; // 8-bit chars + tty.c_iflag &= ~IGNBRK; // disable break processing + tty.c_lflag = 0; // no signaling chars, no echo, + // no canonical processing + tty.c_oflag = 0; // no remapping, no delays + tty.c_cc[VMIN] = 0; // read doesn't block + tty.c_cc[VTIME] = 0; // no read timeout + + tty.c_iflag &= ~(IXON | IXOFF | IXANY); // shut off xon/xoff ctrl + + tty.c_cflag |= (CLOCAL | CREAD);// ignore modem controls, + // enable reading + tty.c_cflag &= ~(PARENB | PARODD); // shut off parity + tty.c_cflag |= parity; + tty.c_cflag |= parity; + tty.c_cflag &= ~CSTOPB; + tty.c_cflag &= ~CRTSCTS; + + if (tcsetattr (fd, TCSANOW, &tty) != 0) + { + fprintf(stderr,"error %d from tcsetattr", errno); + return -1; + } + return 0; +} + +void set_blocking (int fd, int should_block) +{ + struct termios tty; + memset (&tty, 0, sizeof tty); + if (tcgetattr (fd, &tty) != 0) + { + fprintf(stderr,"error %d from tggetattr", errno); + return; + } + + tty.c_cc[VMIN] = should_block ? 1 : 0; + tty.c_cc[VTIME] = 0; + + if (tcsetattr (fd, TCSANOW, &tty) != 0) + fprintf(stderr,"error %d setting term attributes", errno); +} + +void startframe(uint8_t command){ + txframe[0]=FEND; + txframe[1]=command; + tfcs = command; + txp = 2; +} + +void addbyte(uint8_t newbyte){ + tfcs+=newbyte; + + switch(newbyte){ + case FEND: + txframe[txp++] = FESC; + txframe[txp++] = TFEND; + break; + case FESC: + txframe[txp++] = FESC; + txframe[txp++] = TFESC; + break; + + default: + txframe[txp++] = newbyte; + break; + } +} + +void sendframe(){ + tfcs=0xff-tfcs; + addbyte(tfcs); + txframe[txp++] = FEND; +#ifdef frdebug +printf("%02X-L:%04X/%02X\n",txframe[txp-1],txp,tfcs); +#endif +if (fd>=0) + write(fd,txframe,txp); +} + + + +void error() +{ + exit(1); +} + + + + +bool waitframe(uint8_t cmd) +{ + rxp = 0; + newframe = false; + fcs = 0; + +uint32_t addr; + +for (uint32_t to=0;to<5000;to++) +{ +serial_read(0); +usleep(50); + +if (newframe){ +// int rxpp = rxp; + rxp = 0; + newframe = false; + usleep(10); + + + if ((rxframe[0]==READ_ID) && (cmd == READ_ID)){ + + if (rxframe[1]==0xef) fprintf(stderr, "Winbond Serial Flash "); + else fprintf(stderr, "Manufacturer ID: 0x%02X",rxframe[1]); + if ((rxframe[2]==0x40) && (rxframe[3]==0x15)) fprintf(stderr, "- W25Q16BV\n"); + else fprintf(stderr, " / Device ID: 0x%02X%02X\n",rxframe[2],rxframe[3]); + + return true; + + } + + if (rxframe[0]==READ) + + { + + addr = (rxframe[1]<<16) | (rxframe[2]<<8); + pages[addr>>8]=0; + + for (int x=3; x < 259;x++) + { + + membuf[addr++]=rxframe[x]; + } + } + + if (rxframe[0]==READY) if (cmd==READY) return true; else to = 0; + + if (rxframe[0]==EMPTY) pages[(rxframe[1]<<8) | rxframe[2]]=0; + + if ((rxframe[0]==READ)||(rxframe[0]==EMPTY)) if (cmd==READ) return true; else to = 0; +rxframe[0]=0; +fcs = 0; +} + +} +return false; +} + + + + +void flash_read_id() +{ + startframe(READ_ID); + sendframe(); + waitframe(READ_ID); + return; + + fprintf(stderr, "\n"); +} + + +void flash_bulk_erase() +{ + fprintf(stderr, "\nbulk erase.."); + + + startframe(BULK_ERASE); + sendframe(); + waitframe(BULK_ERASE); + fprintf(stderr, "\rbulk erased\n"); + +} + +void flash_64kB_sector_erase(int addr) +{ + fprintf(stderr, "erase 64kB sector at 0x%06X..", addr); + + startframe(SEC_ERASE); + addbyte(addr>>16); + addbyte(addr>>8); + sendframe(); + waitframe(READY); + fprintf(stderr, "erased\n"); + +} + +void flash_read_all(void){ + + fprintf(stderr, "read 0x%06X +0x%06X..\n", 0, 0x200000); + memset(&membuf,0xff,sizeof(membuf)); + memset(&pages,0xff,sizeof(pages)); + startframe(READ_ALL); + sendframe(); + if (!waitframe(READY)) + { + error(); + + } + + fprintf(stderr, "Requesting missmatched frames..."); + bool notready=false; + while (1){ + notready = false; + int s = 0; + for(int x = 0; x < 0x2000;x++) + { + + if (pages[x]>0){ + if (s++ > 25) + { + fprintf(stderr, "ERROR Reading..\n"); + notready = false; + break; + } + notready=true; + fprintf(stderr, "."); + startframe(READ); + addbyte(x >> 8); + addbyte(x >> 0); + sendframe(); + waitframe(READ); + + + } + + } + + if (!notready) break; + + + } + fprintf(stderr, "\n"); + uint32_t i; + if (verbose) + for (i = 0; i < 1024; i++) + fprintf(stderr, "%02x%c", membuf[i], i == 0 || i % 32 == 31 ? '\n' : ' '); + + + + + +} + + + + +void help(const char *progname) +{ + + fprintf(stderr, "\n"); + fprintf(stderr, "iceprog -- simple programming tool for Olinuxino Nano-based Lattice iCE programmers\n"); + fprintf(stderr, "\n"); + fprintf(stderr, "\n"); + fprintf(stderr, "Usage: %s [options] \n", progname); + fprintf(stderr, "\n"); + fprintf(stderr, " -e\n"); + fprintf(stderr, " bulk erase entire flash only\n"); + fprintf(stderr, "\n"); + fprintf(stderr, " -w\n"); + fprintf(stderr, " write only, do not verify\n\n"); + fprintf(stderr, " -f\n"); + fprintf(stderr, " write all data, including 0xFF's pages\n\n"); + fprintf(stderr, " -I\n"); + fprintf(stderr, " port to connect Arduino (default /dev/ttyACM0)\n"); + fprintf(stderr, "\n"); + fprintf(stderr, " -r\n"); + fprintf(stderr, " read entire flash (2MB) and write to file\n"); + fprintf(stderr, "\n"); + + + fprintf(stderr, " -c\n"); + fprintf(stderr, " do not write flash, only verify (check)\n"); + fprintf(stderr, "\n"); + fprintf(stderr, " -b\n"); + fprintf(stderr, " bulk erase entire flash before writing\n"); + fprintf(stderr, "\n"); + fprintf(stderr, " -n\n"); + fprintf(stderr, " do not erase flash before writing\n"); + fprintf(stderr, "\n"); + fprintf(stderr, " -o start address for write [default: 0]\n"); + fprintf(stderr, " (append 'k' to the argument for size in kilobytes,\n"); + fprintf(stderr, " or 'M' for size in megabytes)\n"); + fprintf(stderr, " this feature works not with all options.\n"); + fprintf(stderr, " tested with -b, -v\n"); + fprintf(stderr, " -t\n"); + fprintf(stderr, " just read the flash ID sequence\n"); + fprintf(stderr, "\n"); + fprintf(stderr, " -v\n"); + fprintf(stderr, " verbose output\n"); + fprintf(stderr, "\n"); + exit(1); +} + + +void serial_read(int x) +{ + + +while (1) +{ + if (rxp>512) + { + newframe = 0; + rxp = 0; + escaped = false; + fcs = 0; + break; + } + usleep(5); + uint8_t buf[1]; + int n; + + if (fd < 0) + { + printf("."); + break; + } + else + { + n=read(fd, buf, 1); + if (n==1){ + + switch(buf[0]){ + case FEND: + if (fcs==0xff) + { + newframe = 1; + return; + } + newframe = 0; + rxp = 0; + escaped = false; + fcs = 0; + + break; + + case FESC: + escaped = true; + break; + + case TFESC: + if (escaped) + { + rxframe[rxp++]=FESC; + fcs+=FESC; + escaped = false; + } + else + { + rxframe[rxp++]=TFESC; + fcs += TFESC; + } + + break; + + case TFEND: + if (escaped) + { + rxframe[rxp++]=FEND; + fcs += FEND; + escaped=false; + } + else + { + rxframe[rxp++]=TFEND; + fcs += TFEND; + } + break; + + default: + escaped=false; + rxframe[rxp++]=buf[0]; + fcs+=buf[0]; + break; + } + } + else break; + } +} +} + +int main(int argc, char **argv) +{ + int addr; + int max_read_size = 0x200000; + bool read_mode = false; + bool check_mode = false; + bool bulk_erase = false; + bool dont_erase = false; + bool prog_sram = false; + bool test_mode = false; + + bool noverify = true; // verify performs by arduino board + bool ff_mode = false; + bool bulk_erase_only = false; + const char *filename = NULL; + const char *devstr = NULL; + int rw_offset = 0; + + int opt; + char *endptr; + + +char *portname = SerialPort; + while ((opt = getopt(argc, argv, "I:o:rcbntvwfeh")) != -1) + + + { + switch (opt) + { + case 'd': + devstr = optarg; + break; + + + case 'I': + portname = optarg; + break; + + case 'r': + read_mode = true; + noverify=false; + break; + case 'e': + bulk_erase_only = true; + break; + case 'f': + ff_mode = true; + break; + case 'R': + read_mode = true; + max_read_size = 256 * 1024; + break; + case 'c': + check_mode = true; + noverify=false; + break; + case 'b': + bulk_erase = true; + break; + case 'n': + + dont_erase = true; + break; + case 'S': + prog_sram = true; + break; + case 't': + test_mode = true; + printf("\nTest mode\n"); + break; + case 'v': + verbose = true; + break; + case 'w': + noverify = true; + break; + case 'o': /* set address offset */ + rw_offset = strtol(optarg, &endptr, 0); + if (*endptr == '\0') + /* ok */; + else if (!strcmp(endptr, "k")) + rw_offset *= 1024; + else if (!strcmp(endptr, "M")) + rw_offset *= 1024 * 1024; + else { + fprintf(stderr, "'%s' is not a valid offset\n", optarg); + return EXIT_FAILURE; + } + break; + default: + help(argv[0]); + } + } + + + + + if (read_mode + check_mode + prog_sram + test_mode > 1) + help(argv[0]); + + if (bulk_erase && dont_erase) + help(argv[0]); + + if (optind+1 != argc && !test_mode && !bulk_erase_only) + help(argv[0]); + + filename = argv[optind]; + + //bulk_erase = true; // comment this line if you do not want to bulk erase by default + + + + +/* open serial port */ + fd = open(portname, O_RDWR | O_NOCTTY); +// fd = open(portname, O_RDWR | O_ASYNC | O_NDELAY); +if (fd < 0) +{ + fprintf(stderr,"error %d opening %s: %s\n", errno, portname, strerror (errno)); + return -1; +} + +set_interface_attribs (fd, B57600, 0); // set speed to 57600 bps, 8n1 (no parity) +set_blocking (fd, 0); // set no blocking + + + + fprintf(stderr,"Serial: %s: %s\n", portname, strerror (errno)); + + + + + rxp = 0; + + if (test_mode) + { + + + flash_read_id(); + + + + + + } + else if (prog_sram) + { + fprintf(stderr, "\nprogramming SRAM is not supported!\n"); + } + else + { + + // --------------------------------------------------------- + // Program + // --------------------------------------------------------- + + if (!read_mode && !check_mode && !bulk_erase_only) + { + + FILE *f = (strcmp(filename, "-") == 0) ? stdin : + fopen(filename, "r"); + if (f == NULL) { + fprintf(stderr, "Error: Can't open '%s' for reading: %s\n", filename, strerror(errno)); + error(); + } + + if (!dont_erase) + { + if (bulk_erase) + { + + flash_bulk_erase(); + sleep(1); + flash_read_id(); + usleep(10000); + } + else + { + struct stat st_buf; + if (stat(filename, &st_buf)) { + fprintf(stderr, "Error: Can't stat '%s': %s\n", filename, strerror(errno)); + error(); + } + + fprintf(stderr, "file size: %d\n", (int)st_buf.st_size); + /* 64 k */ + int begin_addr = rw_offset & ~0xffff; + int end_addr = (rw_offset + st_buf.st_size + 0xffff) & ~0xffff; + for (addr = begin_addr; addr < end_addr; addr += 0x10000) { + + flash_64kB_sector_erase(addr); + + } + } + } + + fprintf(stderr, "\nprogramming..\n"); +int ccc; + + flash_read_id(); + + + /* page is 256 */ + for (int rc, addr = 0; true; addr += rc) { + uint8_t buffer[256]; + int page_size = 256 - (rw_offset + addr) % 256; + rc = fread(buffer, 1, page_size, f); + + int offset_addr = addr + rw_offset; + if (rc <= 0) break; + if (verbose) + fprintf(stderr, "prog 0x%06X +0x%03X..\n", offset_addr, rc); + else + fprintf(stderr, "\rprog 0x%06X +0x%03X..", offset_addr, rc); + for (ccc=0;ccc>16); + addbyte(offset_addr>>8); + for (x=0;x" +syn match jackNumber "\<[1-9][0-9]*\>" +syn keyword jackType void int boolean String char Array +syn keyword jackConditional if else +syn keyword jackRepeat while +syn keyword jackKeyword var field static +syn keyword jackFunction return let do + + +highlight link jackTodo Todo +highlight link jackComment Comment +highlight link jackConstant Constant +highlight link jackBoolean Boolean +highlight link jackString String +highlight link jackNumber Number +highlight link jackType Type +highlight link jackConditional Conditional +highlight link jackRepeat Repeat +highlight link jackKeyword Keyword +highlight link jackFunction Function diff --git a/tools/olimexino-32u4 firmware/README.md b/tools/olimexino-32u4 firmware/README.md new file mode 100644 index 0000000..f01b382 --- /dev/null +++ b/tools/olimexino-32u4 firmware/README.md @@ -0,0 +1,26 @@ +This firmware has to be uploaded to OLIMEXINO-32u4 in order to use it as an iCE40 programmer. + + +### Using Arduino IDE ### + +This firmware can be uploaded via Arduino IDE. Just go to iceprog folder and load iceprog.ino. + +We used SPIFlash 2.2.0 library for Winbond Flash Memory by Prajwal Bhattaram - Marzogh (the +project is now called "SPIMemory". The files we used are already inside the project, no need to +install it separately. But our advice is to the check the full project. It is availalbe here: + +https://github.com/Marzogh/SPIMemory/tree/v2.2.0 + + +### Using PlatformIO ### + +Install PlatformIO, use this guide for details http://docs.platformio.org/en/stable/installation.html + +Build & Upload: + + platformio run + platformio run --target upload + +Alternatively you can use SPI programmer to burn firmware into OLIMEXINO-32u4, e.g.: + + avrdude -p atmega32u4 -P /dev/ttyUSB0 -c buspirate -b115200 -D -Uflash:w:[.pioenvs/leonardo/firmware.hex]:i diff --git a/tools/olimexino-32u4 firmware/iceprog-nano/SPIFlash.cpp b/tools/olimexino-32u4 firmware/iceprog-nano/SPIFlash.cpp new file mode 100644 index 0000000..d6b61fd --- /dev/null +++ b/tools/olimexino-32u4 firmware/iceprog-nano/SPIFlash.cpp @@ -0,0 +1,1961 @@ +/* Arduino SPIFlash Library v.2.2.0 + * Copyright (C) 2015 by Prajwal Bhattaram + * Modified by Prajwal Bhattaram - 24/11/2015 + * + * This file is part of the Arduino SPIFlash Library. This library is for + * Winbond NOR flash memory modules. In its current form it enables reading + * and writing individual data variables, structs and arrays from and to various locations; + * reading and writing pages; continuous read functions; sector, block and chip erase; + * suspending and resuming programming/erase and powering down for low power operation. + * + * This Library is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This Library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License v3.0 + * along with the Arduino SPIFlash Library. If not, see + * . + */ + +#include "SPIFlash.h" + +#if defined (__arm__) && defined (__SAM3X8E__) + #define _delay_us(us) delayMicroseconds(us) +#else + #include +#endif + +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +// Uncomment the code below to run a diagnostic if your flash // +// does not respond // +// // +// Error codes will be generated and returned on functions // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +//#define RUNDIAGNOSTIC // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +// Uncomment the code below to increase the speed of the library // +// by disabling _notPrevWritten() // +// // +// Make sure the sectors being written to have been erased beforehand // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +#if defined (__SAM3X8E__) +//#define HIGHSPEED +#elif defined (__AVR__) +//#define HIGHSPEED +#endif +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + +#define _MANID 0xEF +#define PAGESIZE 0x100 + +#define MANID 0x90 +#define PAGEPROG 0x02 +#define READDATA 0x03 +#define FASTREAD 0x0B +#define WRITEDISABLE 0x04 +#define READSTAT1 0x05 +#define READSTAT2 0x35 +#define WRITEENABLE 0x06 +#define SECTORERASE 0x20 +#define BLOCK32ERASE 0x52 +#define CHIPERASE 0x60 +#define SUSPEND 0x75 +#define ID 0x90 +#define RESUME 0x7A +#define JEDECID 0x9f +#define RELEASE 0xAB +#define POWERDOWN 0xB9 +#define BLOCK64ERASE 0xD8 + +#define BUSY 0x01 +#define WRTEN 0x02 +#define SUS 0x40 +#define DUMMYBYTE 0xEE + +#define arrayLen(x) (sizeof(x) / sizeof(*x)) +#define lengthOf(x) (sizeof(x))/sizeof(byte) +#define maxAddress capacity +#define NO_CONTINUE 0x00 +#define PASS 0x01 +#define FAIL 0x00 + +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +// List of Error codes // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + #ifdef RUNDIAGNOSTIC + + #define SUCCESS 0x00 + #define CALLBEGIN 0x01 + #define UNKNOWNCHIP 0x02 + #define UNKNOWNCAP 0x03 + #define CHIPBUSY 0x04 + #define OUTOFBOUNDS 0x05 + #define CANTENWRITE 0x06 + #define PREVWRITTEN 0x07 + #define UNKNOWNERROR 0xFF + + #endif + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + +#if defined (__arm__) && defined (__SAM3X8E__) + #include +#elif defined (__AVR__) + #ifdef __AVR_ATtiny85__ + #define CHIP_SELECT PORTB &= ~cs_mask; + #define CHIP_DESELECT PORTB |= cs_mask; + #define SPIBIT \ + USICR = ((1< + #define CHIP_SELECT *cs_port &= ~cs_mask; + #define CHIP_DESELECT *cs_port |= cs_mask; + #define xfer(n) SPI.transfer(n) + #endif +#endif + +// Constructor +#if defined (__arm__) && defined (__SAM3X8E__) +SPIFlash::SPIFlash(uint8_t cs, bool overflow) { + csPin = cs; + pageOverflow = overflow; +} +#elif defined (__AVR__) +SPIFlash::SPIFlash(uint8_t cs, bool overflow) { + csPin = cs; +#ifndef __AVR_ATtiny85__ + cs_port = portOutputRegister(digitalPinToPort(csPin)); +#endif + cs_mask = digitalPinToBitMask(csPin); + SPI.begin(); + SPI.setDataMode(0); + SPI.setBitOrder(MSBFIRST); + //SPI.setClockDivider(SPI_CLOCK_DIV2); + pageOverflow = overflow; + pinMode(cs, OUTPUT); +} +#endif + +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +// Private functions used by read, write and erase operations // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + +// Select chip and issue command - data to follow +void SPIFlash::_cmd(uint8_t cmd, bool _continue, uint8_t cs) { + cs = csPin; + #if defined (__arm__) && defined (__SAM3X8E__) + if (!_continue) + SPI.transfer(cs, cmd); + else + SPI.transfer(cs, cmd, SPI_CONTINUE); + #else + CHIP_SELECT + (void)xfer(cmd); + #endif +} + +// Checks if status register 1 can be accessed - used during powerdown and power up and for debugging +uint8_t SPIFlash::_readStat1(void) { + uint8_t stat1; + _cmd(READSTAT1); + #if defined (__SAM3X8E__) + stat1 = SPI.transfer(csPin, 0x00); + #else + stat1 = xfer(0); + CHIP_DESELECT + #endif + return stat1; +} + +// Checks the erase/program suspend flag before enabling/disabling a program/erase suspend operation +bool SPIFlash::_noSuspend(void) { + uint8_t state; + + _cmd(READSTAT2); + #if defined (__arm__) && defined (__SAM3X8E__) + state = SPI.transfer(csPin, 0x00); + #else + state = xfer(0); + CHIP_DESELECT + #endif + + if(state & SUS) + return false; + return true; +} + +// Polls the status register 1 until busy flag is cleared or timeout +bool SPIFlash::_notBusy(uint32_t timeout) { + uint8_t state; + uint32_t startTime = millis(); + + do { + _cmd(READSTAT1); + #if defined (__arm__) && defined (__SAM3X8E__) + state = SPI.transfer(csPin, 0x00); + #else + state = xfer(0); + CHIP_DESELECT + #endif + if((millis()-startTime) > timeout){ + #ifdef RUNDIAGNOSTIC + errorcode = CHIPBUSY; + _troubleshoot(errorcode); + #endif + return false; + } + } while(state & BUSY); + return true; +} + +//Enables writing to chip by setting the WRITEENABLE bit +bool SPIFlash::_writeEnable(void) { + uint8_t state; + + #if defined (__arm__) && (__SAM3X8E__) + SPI.transfer(csPin, WRITEENABLE); + #else + _cmd(WRITEENABLE); + CHIP_DESELECT + #endif + + //verifies that WRITE is enabled + #if defined (__arm__) && (__SAM3X8E__) + SPI.transfer(csPin, READSTAT1, SPI_CONTINUE); + state = SPI.transfer(csPin, 0x00); + #else + _cmd(READSTAT1); + state = xfer(0); + CHIP_DESELECT + #endif + if(state & WRTEN) + return true; + else { + #ifdef RUNDIAGNOSTIC + errorcode = CANTENWRITE; + _troubleshoot(errorcode); + #endif + + return false; + } +} + +//Disables writing to chip by setting the Write Enable Latch (WEL) bit in the Status Register to 0 +//_writeDisable() is not required under the following conditions because the Write Enable Latch (WEL) flag is cleared to 0 +// i.e. to write disable state: +// Power-up, Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, +// Erase Security Register and Program Security register +bool SPIFlash::_writeDisable(void) { + _cmd(WRITEDISABLE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + + return true; +} + +//Gets address from page number and offset. Takes two arguments: +// 1. page_number --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +uint32_t SPIFlash::_getAddress(uint16_t page_number, uint8_t offset) { + uint32_t address = page_number; + address = (address << 8) + offset; + + if (!_addressCheck(address)){ + #ifdef RUNDIAGNOSTIC + errorcode = OUTOFBOUNDS; + _troubleshoot(errorcode); + #endif + return false; + } + else + return address; +} + +//Checks the device ID to establish storage parameters +bool SPIFlash::_getManId(uint8_t *b1, uint8_t *b2) { + if(!_notBusy()) + return false; + _cmd(MANID); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, 0x00, SPI_CONTINUE); + SPI.transfer(csPin, 0x00, SPI_CONTINUE); + SPI.transfer(csPin, 0x00, SPI_CONTINUE); + *b1 = SPI.transfer(csPin, 0x00, SPI_CONTINUE); + *b2 = SPI.transfer(csPin, 0x00); + #else + xfer(0); + xfer(0); + xfer(0); + *b1 = xfer(0); + *b2 = xfer(0); + CHIP_DESELECT + #endif + return true; +} + +//Checks for presence of chip by requesting JEDEC ID +bool SPIFlash::_getJedecId(uint8_t *b1, uint8_t *b2, uint8_t *b3) { + if(!_notBusy()) + return false; + _cmd(JEDECID); + #if defined (__arm__) && defined (__SAM3X8E__) + *b1 = SPI.transfer(csPin, 0x00, SPI_CONTINUE); // manufacturer id + *b2 = SPI.transfer(csPin, 0x00, SPI_CONTINUE); // manufacturer id + *b3 = SPI.transfer(csPin, 0x00); // capacity + #else + *b1 = xfer(0); // manufacturer id + *b2 = xfer(0); // memory type + *b3 = xfer(0); // capacity + CHIP_DESELECT + #endif + return true; +} + +//Identifies the chip +bool SPIFlash::_chipID(void) { + //Get Manfucturer/Device ID so the library can identify the chip + uint8_t manID, devID ; + _getManId(&manID, &devID); + + if (manID != _MANID){ //If the chip is not a Winbond Chip + #ifdef RUNDIAGNOSTIC + errorcode = UNKNOWNCHIP; //Error code for unidentified chip + _troubleshoot(errorcode); + #endif + while(1); + } + + //Check flash memory type and identify capacity + uint8_t i; + //capacity & chip name + for (i = 0; i < sizeof(devType); i++) + { + if (devID == devType[i]) { + capacity = memSize[i]; + name = chipName[i]; + } + } + if (capacity == 0) { + #ifdef RUNDIAGNOSTIC + errorcode = UNKNOWNCAP; //Error code for unidentified capacity + _troubleshoot(errorcode); + #endif + while(1); + } + + maxPage = capacity/PAGESIZE; + + /*#ifdef RUNDIAGNOSTIC + char buffer[64]; + sprintf(buffer, "Manufacturer ID: %02xh\nMemory Type: %02xh\nCapacity: %lu\nmaxPage: %d", manID, devID, capacity, maxPage); + Serial.println(buffer); + #endif*/ + return true; +} + +//Checks to see if pageOverflow is permitted and assists with determining next address to read/write. +//Sets the global address variable +bool SPIFlash::_addressCheck(uint32_t address) { + #ifdef RUNDIAGNOSTIC + if (capacity == 0) { + errorcode = CALLBEGIN; + _troubleshoot(errorcode); + } + #endif + if (address >= capacity) { + if (!pageOverflow) { + #ifdef RUNDIAGNOSTIC + errorcode = OUTOFBOUNDS; + _troubleshoot(errorcode); + #endif + return false; // At end of memory - (!pageOverflow) + } + else { + address = 0x00; // At end of memory - (pageOverflow) + return true; + } + } + return true; // Not at end of memory if (address < capacity) +} + +//Double checks all parameters before calling a Read +//Has two variants: +// A. Takes address and returns the address if true, else returns false. Throws an error if there is a problem. +// B. Takes page_number and offset and returns address. Throws an error if there is a problem +// Variant A +uint32_t SPIFlash::_prepRead(uint32_t address) { + if(!_notBusy()) + return false; + if (!_addressCheck(address)) + return false; + else + return address; +} +// Variant B +uint32_t SPIFlash::_prepRead(uint16_t page_number, uint8_t offset) { + uint32_t address = _getAddress(page_number, offset); + return _prepRead(address); +} + +//Initiates read operation - but data is not read yet +void SPIFlash::_beginRead(uint32_t address) { + _cmd(READDATA); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, address, SPI_CONTINUE); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(address); + #endif + //SPI data lines are left open until _endProcess() is called +} + +//Initiates fast read operation (can operate at the highest possible freq of 104 MHz (at 3.0-3.6V) of 80 MHz (at 2.5-3.6V)) +//- but data is not read yet +void SPIFlash::_beginFastRead(uint32_t address) { + _cmd(FASTREAD); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, address, SPI_CONTINUE); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(address); + #endif + //SPI data lines are left open until _endProcess() is called +} + +//Reads next byte. Call 'n' times to read 'n' number of bytes. Should be called after _beginRead() +uint8_t SPIFlash::_readNextByte(bool _continue) { + uint8_t result; + #if defined (__arm__) && defined (__SAM3X8E__) + if (!_continue) + result = SPI.transfer(csPin, 0x00); + else + result = SPI.transfer(csPin, 0x00, SPI_CONTINUE); + #else + result = xfer(0x00); + #endif + return result; +} + +//Double checks all parameters before initiating a write +//Has two variants: +// A. Takes address and returns address if true or 'false' if false. Throws an error if there is a problem. +// B. Takes page_number and offset and returns address. Throws an error if there is a problem +// Variant A +uint32_t SPIFlash::_prepWrite(uint32_t address) { + if(!_notBusy()||!_writeEnable()) + return false; + if (!_addressCheck(address)) { + #ifdef RUNDIAGNOSTIC + errorcode = OUTOFBOUNDS; + _troubleshoot(errorcode); + #endif + return false; + } + else + return address; +} +// Variant B +uint32_t SPIFlash::_prepWrite(uint16_t page_number, uint8_t offset) { + uint32_t address = _getAddress(page_number, offset); + return _prepWrite(address); +} + +//Initiates write operation - but data is not written yet +bool SPIFlash::_beginWrite(uint32_t address) { + _cmd(PAGEPROG); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, address, SPI_CONTINUE); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(address); + #endif + //SPI data lines are left open until _endProcess() is called + return true; +} + +//Writes next byte. Call 'n' times to read 'n' number of bytes. Should be called after _beginWrite() +bool SPIFlash::_writeNextByte(uint8_t b, bool _continue) { + #if defined (__arm__) && defined (__SAM3X8E__) + if (!_continue) + SPI.transfer(csPin, b); + else + SPI.transfer(csPin, b, SPI_CONTINUE); + #else + xfer(b); + #endif + return true; +} + +//Stops all operations. Should be called after all the required data is read/written from repeated _readNextByte()/_writeNextByte() calls +void SPIFlash::_endProcess(void) { + #if defined (__arm__) && defined (__SAM3X8E__) + _delay_us(3); + #else + CHIP_DESELECT + #endif + _delay_us(3); +} + +#ifndef HIGHSPEED +bool SPIFlash::_notPrevWritten(uint32_t address, uint8_t size) { + uint32_t _size = size; + + /*uint8_t databyte1, databyte2, databyte3; + databyte1 = readByte(address, true); + databyte2 = readByte((address + (size/2)), true); + databyte3 = readByte((address+size), true); + if (databyte1 != 255 || databyte2 != 255 || databyte3 != 255) { + #ifdef RUNDIAGNOSTIC + errorcode = PREVWRITTEN; + _troubleshoot(errorcode); + #endif + return false; + } + _delay_us(3); + return true;*/ + uint32_t sampleSize; + if (_size <= 10) { + sampleSize = _size; + } + + if (_size > 10) { + do { + sampleSize++; + _size/=10; + } while((_size/10) >= 1); + } + + uint32_t addresses[sampleSize]; + + for (uint16_t i = 0; i < sampleSize; i++) { + addresses[i] = (rand() % size) + address; + } + + for (uint16_t i = 0; i < sampleSize; i++) { + uint8_t databyte = readByte(addresses[i]); + if (databyte != 0xFF) { + #ifdef RUNDIAGNOSTIC + errorcode = PREVWRITTEN; + _troubleshoot(errorcode); + #endif + return false; + } + } + return true; +} +#endif + +#ifdef RUNDIAGNOSTIC +//Troubleshooting function. Called when #ifdef RUNDIAGNOSTIC is uncommented at the top of this file. +void SPIFlash::_troubleshoot(uint8_t error) { + + switch (error) { + case SUCCESS: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(SUCCESS, HEX); + #else + Serial.println("Action completed successfully"); + #endif + break; + + case CALLBEGIN: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(CALLBEGIN, HEX); + #else + Serial.println("*constructor_of_choice*.begin() was not called in void setup()"); + #endif + break; + + case UNKNOWNCHIP: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(UNKNOWNCHIP, HEX); + #else + Serial.println("Unable to identify chip. Are you shure this is a Winbond Flash chip"); + Serial.println("Please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with your chip type and I will try to add support to your chip"); + #endif + + break; + + case UNKNOWNCAP: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(UNKNOWNCAP, HEX); + #else + Serial.println("Unable to identify capacity."); + Serial.println("Please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with your chip type and I will work on adding support to your chip"); + #endif + break; + + case CHIPBUSY: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(CHIPBUSY, HEX); + #else + Serial.println("Chip is busy."); + Serial.println("Make sure all pins have been connected properly"); + Serial.print("If it still doesn't work, "); + Serial.println("please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with the details of what your were doing when this error occured"); + #endif + break; + + case OUTOFBOUNDS: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(OUTOFBOUNDS, HEX); + #else + Serial.println("Page overflow has been disabled and the address called exceeds the memory"); + #endif + break; + + case CANTENWRITE: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(CANTENWRITE, HEX); + #else + Serial.println("Unable to Enable Writing to chip."); + Serial.println("Please make sure the HOLD & WRITEPROTECT pins are connected properly to VCC & GND respectively"); + Serial.print("If you are still facing issues, "); + Serial.println("please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with the details of what your were doing when this error occured"); + #endif + break; + + case PREVWRITTEN: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(PREVWRITTEN, HEX); + #else + Serial.println("This sector already contains data."); + Serial.println("Please make sure the sectors being written to are erased."); + Serial.print("If you are still facing issues, "); + Serial.println("please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with the details of what your were doing when this error occured"); + #endif + break; + + default: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x"); + Serial.println(UNKNOWNERROR, HEX); + #else + Serial.println("Unknown error"); + Serial.println("Please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with the details of what your were doing when this error occured"); + #endif + break; + } +} +#endif + + +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +// Public functions used for read, write and erase operations // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + +//Identifies chip and establishes parameters +void SPIFlash::begin() { + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.begin(csPin); + SPI.setClockDivider(csPin, 21); + SPI.setDataMode(csPin, SPI_MODE0); + #endif + _chipID(); +} + +//Returns capacity of chip +uint32_t SPIFlash::getCapacity() { + return capacity; +} + +//Returns maximum number of pages +uint32_t SPIFlash::getMaxPage() { + return maxPage; +} + + +//Returns identifying name of the chip +uint16_t SPIFlash::getChipName() { + return name; +} + +//Checks for and initiates the chip by requesting JEDEC ID which is returned as a 32 bit int +uint16_t SPIFlash::getManID() { + uint8_t b1, b2; + _getManId(&b1, &b2); + uint32_t id = b1; + id = (id << 8)|(b2 << 0); + return id; +} + +//Checks for and initiates the chip by requesting JEDEC ID which is returned as a 32 bit int +uint32_t SPIFlash::getJEDECID() { + uint8_t b1, b2, b3; + _getJedecId(&b1, &b2, &b3); + uint32_t id = b1; + id = (id << 8)|(b2 << 0); + id = (id << 8)|(b3 << 0); + return id; +} + +//Gets the next available address for use. Has two variants: +// A. Takes the size of the data as an argument and returns a 32-bit address +// B. Takes a three variables, the size of the data and two other variables to return a page number value & an offset into. +// All addresses in the in the sketch must be obtained via this function or not at all. +// Variant A +uint32_t SPIFlash::getAddress(uint16_t size) { + if (!_addressCheck(currentAddress)){ + #ifdef RUNDIAGNOSTIC + errorcode = OUTOFBOUNDS; + _troubleshoot(errorcode); + #endif + return false; + } + else { + uint32_t address = currentAddress; + /*Serial.print("Current Address: "); + Serial.println(currentAddress);*/ + currentAddress+=size; + return address; + } +} +// Variant B +bool SPIFlash::getAddress(uint16_t size, uint16_t &page_number, uint8_t &offset) { + uint32_t address = getAddress(size); + offset = (address >> 0); + page_number = (address >> 8); + return true; +} + +//Function for returning the size of the string (only to be used for the getAddress() function) +uint16_t SPIFlash::sizeofStr(String &inputStr) { + uint16_t inStrLen = inputStr.length() + 1; + uint16_t size; + + //inputStr.toCharArray(inputChar, inStrLen); + + size=(sizeof(char)*inStrLen); + size+=sizeof(inStrLen); + + return size; +} + +// Reads a byte of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +uint8_t SPIFlash::readByte(uint32_t address, bool fastRead) { + uint8_t data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + data = _readNextByte(NO_CONTINUE); + _endProcess(); + return data; + } +} +// Variant B +uint8_t SPIFlash::readByte(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readByte(address, fastRead); +} + +// Reads a char of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +int8_t SPIFlash::readChar(uint32_t address, bool fastRead) { + int8_t data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + data = _readNextByte(NO_CONTINUE); + _endProcess(); + return data; + } +} +// Variant B +int8_t SPIFlash::readChar(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readChar(address, fastRead); +} + +// Reads an array of bytes starting from a specific location in a page.// Has two variants: +// A. Takes three arguments +// 1. address --> Any address from 0 to maxAddress +// 2. data_buffer --> The array of bytes to be read from the flash memory - starting at the address indicated +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes four arguments +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data_buffer --> The array of bytes to be read from the flash memory - starting at the offset on the page indicated +// 4. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +uint8_t SPIFlash::readByteArray(uint32_t address, uint8_t *data_buffer, uint16_t bufferSize, bool fastRead) { + if (!_prepRead(address)) { + + } + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t a = 0; a < bufferSize; a++) { + if (a == (bufferSize-1)) + data_buffer[a] = _readNextByte(NO_CONTINUE); + else + data_buffer[a] = _readNextByte(); + _addressCheck(address++); + } + _endProcess(); + } + return true; +} +// Variant B +uint8_t SPIFlash::readByteArray(uint16_t page_number, uint8_t offset, uint8_t *data_buffer, uint16_t bufferSize, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readByteArray(address, data_buffer, bufferSize, fastRead); +} + +// Reads an array of bytes starting from a specific location in a page.// Has two variants: +// A. Takes three arguments +// 1. address --> Any address from 0 to maxAddress +// 2. data_buffer --> The array of bytes to be read from the flash memory - starting at the address indicated +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes four arguments +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data_buffer --> The array of bytes to be read from the flash memory - starting at the offset on the page indicated +// 4. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +uint8_t SPIFlash::readCharArray(uint32_t address, char *data_buffer, uint16_t bufferSize, bool fastRead) { + if (_prepRead(address)) { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t a = 0; a < bufferSize; a++) { + _addressCheck(address+a); + if (a == (bufferSize-1)) + data_buffer[a] = _readNextByte(NO_CONTINUE); + else + data_buffer[a] = _readNextByte(); + } + _endProcess(); + return true; + } + else + return false; +} +// Variant B +uint8_t SPIFlash::readCharArray(uint16_t page_number, uint8_t offset, char *data_buffer, uint16_t bufferSize, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readCharArray(address, data_buffer, bufferSize, fastRead); +} + +// Reads an unsigned int of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +uint16_t SPIFlash::readWord(uint32_t address, bool fastRead) { + union + { + byte b[sizeof(uint16_t)]; + uint16_t I; + } data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t i=0; i < (sizeof(int16_t)); i++) { + if (i == (sizeof(uint16_t)-1)) + data.b[i] = _readNextByte(NO_CONTINUE); + else + data.b[i] = _readNextByte(); + } + _endProcess(); + return data.I; + } +} +// Variant B +uint16_t SPIFlash::readWord(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readWord(address, fastRead); +} + +// Reads a signed int of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +int16_t SPIFlash::readShort(uint32_t address, bool fastRead) { + union + { + byte b[sizeof(int16_t)]; + int16_t s; + } data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t i=0; i < (sizeof(int16_t)); i++) { + if (i == (sizeof(int16_t)-1)) + data.b[i] = _readNextByte(NO_CONTINUE); + else + data.b[i] = _readNextByte(); + } + _endProcess(); + return data.s; + } +} +// Variant B +int16_t SPIFlash::readShort(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readShort(address, fastRead); +} + +// Reads an unsigned long of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +uint32_t SPIFlash::readULong(uint32_t address, bool fastRead) { + union + { + byte b[sizeof(uint32_t)]; + uint32_t l; + } data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t i=0; i < (sizeof(uint32_t)); i++) { + if (i == (sizeof(uint32_t)-1)) + data.b[i] = _readNextByte(NO_CONTINUE); + else + data.b[i] = _readNextByte(); + } + _endProcess(); + return data.l; + } +} +// Variant B +uint32_t SPIFlash::readULong(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readULong(address, fastRead); +} + +// Reads a signed long of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +int32_t SPIFlash::readLong(uint32_t address, bool fastRead) { + union + { + byte b[sizeof(int32_t)]; + int32_t l; + } data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t i=0; i < (sizeof(int32_t)); i++) { + if (i == (sizeof(int32_t)-1)) + data.b[i] = _readNextByte(NO_CONTINUE); + else + data.b[i] = _readNextByte(); + } + _endProcess(); + return data.l; + } +} +// Variant B +int32_t SPIFlash::readLong(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readLong(address, fastRead); +} + +// Reads a signed long of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +float SPIFlash::readFloat(uint32_t address, bool fastRead) { + union + { + byte b[(sizeof(float))]; + float f; + } data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t i=0; i < (sizeof(float)); i++) { + if (i == (sizeof(float)-1)) + data.b[i] = _readNextByte(NO_CONTINUE); + else + data.b[i] = _readNextByte(); + } + _endProcess(); + return data.f; + } +} +// Variant B +float SPIFlash::readFloat(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readFloat(address, fastRead); +} + +// Reads a string from a specific location on a page. +// Has two variants: +// A. Takes three arguments +// 1. address --> Any address from 0 to maxAddress +// 2. outputString --> String variable to write the output to +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes four arguments +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. outputString --> String variable to write the output to +// 4. fastRead --> defaults to false - executes _beginFastRead() if set to true +// This function first reads a short from the address to figure out the size of the String object stored and +// then reads the String object data +// Variant A +bool SPIFlash::readStr(uint32_t address, String &outStr, bool fastRead) { + if (!_prepRead(address)) + return false; + uint16_t strLen; + + strLen = readShort(address); + address+=(sizeof(strLen)); + + char outputChar[strLen]; + + readCharArray(address, outputChar, strLen, fastRead); + + outStr = String(outputChar); + return true; +} +// Variant B +bool SPIFlash::readStr(uint16_t page_number, uint8_t offset, String &outStr, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + return readStr(address, outStr, fastRead); +} + +// Reads a page of data into a page buffer. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. data_buffer --> a data buffer to read the data into (This HAS to be an array of 256 bytes) +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +bool SPIFlash::readPage(uint16_t page_number, uint8_t *data_buffer, bool fastRead) { + uint32_t address = _prepRead(page_number); + + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (int a = 0; a < 256; ++a) { + if (a == (255)) + data_buffer[a] = _readNextByte(NO_CONTINUE); + else + data_buffer[a] = _readNextByte(); + } + _endProcess(); + return true; +} + +// Writes a byte of data to a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One byte of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One byte of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeByte(uint32_t address, uint8_t data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + _beginWrite(address); + _writeNextByte(data, NO_CONTINUE); + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeByte(uint16_t page_number, uint8_t offset, uint8_t data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeByte(address, data, errorCheck); +} + +// Writes a char of data to a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One char of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One char of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeChar(uint32_t address, int8_t data, bool errorCheck) { + if (!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + _beginWrite(address); + _writeNextByte(data, NO_CONTINUE); + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); + +} +// Variant B +bool SPIFlash::writeChar(uint16_t page_number, uint8_t offset, int8_t data, bool errorCheck) { + uint32_t address = _prepWrite(page_number, offset); + + return writeChar(address, data, errorCheck); + +} + +// Writes an array of bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> An array of bytes to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> An array of bytes to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeByteArray(uint32_t address, uint8_t *data_buffer, uint16_t bufferSize, bool errorCheck) { + if (!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data_buffer))) + return false; + #endif + + _beginWrite(address); + + for (int i = 0; i < bufferSize; i++) { + _addressCheck(address+i); + if (i == (bufferSize-1)) + _writeNextByte(data_buffer[i], NO_CONTINUE); + else + _writeNextByte(data_buffer[i]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data_buffer); +} +// Variant B +bool SPIFlash::writeByteArray(uint16_t page_number, uint8_t offset, uint8_t *data_buffer, uint16_t bufferSize, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeByteArray(address, data_buffer, bufferSize, errorCheck); +} + +// Writes an array of bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> An array of chars to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> An array of chars to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeCharArray(uint32_t address, char *data_buffer, uint16_t bufferSize, bool errorCheck) { + if (!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data_buffer))) + return false; + #endif + + _beginWrite(address); + + for (int i = 0; i < bufferSize; i++) { + _addressCheck(address+i); + if (i == (bufferSize-1)) + _writeNextByte(data_buffer[i], NO_CONTINUE); + else + _writeNextByte(data_buffer[i]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data_buffer); +} +// Variant B +bool SPIFlash::writeCharArray(uint16_t page_number, uint8_t offset, char *data_buffer, uint16_t bufferSize, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeCharArray(address, data_buffer, bufferSize, errorCheck); +} + +// Writes an unsigned int as two bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One unsigned int of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One unsigned int of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeWord(uint32_t address, uint16_t data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + union + { + uint8_t b[sizeof(data)]; + uint16_t w; + } var; + var.w = data; + + _beginWrite(address); + for (uint16_t j = 0; j < sizeof(data); j++) { + if (j == (sizeof(data)-1)) + _writeNextByte(var.b[j], NO_CONTINUE); + else + _writeNextByte(var.b[j]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeWord(uint16_t page_number, uint8_t offset, uint16_t data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeWord(address, data, errorCheck); +} + +// Writes a signed int as two bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One signed int of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One signed int of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeShort(uint32_t address, int16_t data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + union + { + uint8_t b[sizeof(data)]; + int16_t s; + } var; + var.s = data; + _beginWrite(address); + for (uint16_t j = 0; j < (sizeof(data)); j++) { + if (j == (sizeof(data)-1)) + _writeNextByte(var.b[j], NO_CONTINUE); + else + _writeNextByte(var.b[j]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeShort(uint16_t page_number, uint8_t offset, int16_t data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeShort(address, data, errorCheck); +} + +// Writes an unsigned long as four bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One unsigned long of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One unsigned long of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeULong(uint32_t address, uint32_t data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + union + { + uint8_t b[sizeof(data)]; + uint32_t l; + } var; + var.l = data; + _beginWrite(address); + for (uint16_t j = 0; j < (sizeof(data)); j++) { + if (j == (sizeof(data)-1)) + _writeNextByte(var.b[j], NO_CONTINUE); + else + _writeNextByte(var.b[j]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeULong(uint16_t page_number, uint8_t offset, uint32_t data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeULong(address, data, errorCheck); +} + +// Writes a signed long as four bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One signed long of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One signed long of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeLong(uint32_t address, int32_t data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + union + { + uint8_t b[sizeof(data)]; + int32_t l; + } var; + var.l = data; + _beginWrite(address); + for (uint16_t j = 0; j < (sizeof(data)); j++) { + if (j == (sizeof(data)-1)) + _writeNextByte(var.b[j], NO_CONTINUE); + else + _writeNextByte(var.b[j]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeLong(uint16_t page_number, uint8_t offset, int32_t data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeLong(address, data, errorCheck); +} + +// Writes a float as four bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One float of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One float of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeFloat(uint32_t address, float data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + union + { + uint8_t b[sizeof(data)]; + float f; + } var; + var.f = data; + _beginWrite(address); + for (uint16_t j = 0; j < (sizeof(data)); j++) { + if (j == (sizeof(data)-1)) + _writeNextByte(var.b[j], NO_CONTINUE); + else + _writeNextByte(var.b[j]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeFloat(uint16_t page_number, uint8_t offset, float data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeFloat(address, data, errorCheck); +} + +// Reads a string from a specific location on a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. inputString --> String variable to write the data from +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. inputString --> String variable to write the data from +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// This function first writes the size of the string as an unsigned int to the address to figure out the size of the String object stored and +// then writes the String object data. Therefore it takes up two bytes more than the size of the String itself. +// Variant A +bool SPIFlash::writeStr(uint32_t address, String &inputStr, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(inputStr))) + return false; + #endif + + uint16_t inStrLen = inputStr.length() + 1; + char inputChar[inStrLen]; + writeWord(address, inStrLen, errorCheck); + + address+=sizeof(inStrLen); + + inputStr.toCharArray(inputChar, inStrLen); + writeCharArray(address, inputChar, inStrLen, errorCheck); + return true; +} +// Variant B +bool SPIFlash::writeStr(uint16_t page_number, uint8_t offset, String &inputStr, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + return writeStr(address, inputStr, errorCheck); +} + +// Writes a page of data from a data_buffer array. Make sure the sizeOf(uint8_t data_buffer[]) == 256. +// errorCheck --> Turned on by default. Checks for writing errors. +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +bool SPIFlash::writePage(uint16_t page_number, uint8_t *data_buffer, bool errorCheck) { + uint32_t address = _prepWrite(page_number); + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data_buffer))) + return false; + #endif + + _beginWrite(address); + for (uint16_t i = 0; i < PAGESIZE; ++i){ + if (i == (PAGESIZE-1)) + _writeNextByte(data_buffer[i], NO_CONTINUE); + else + _writeNextByte(data_buffer[i]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, *data_buffer); +} + + +//Erases one 4k sector. Has two variants: +// A. Takes the address as the argument and erases the sector containing the address. +// B. Takes page to be erased as the argument and erases the sector containing the page. +// The sectors are numbered 0 - 255 containing 16 pages each. +// Page 0-15 --> Sector 0; Page 16-31 --> Sector 1;......Page 4080-4095 --> Sector 255 +// Variant A +bool SPIFlash::eraseSector(uint32_t address) { + if(!_notBusy()||!_writeEnable()) + return false; + + _cmd(SECTORERASE); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, 0x00); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(0); + CHIP_DESELECT + #endif + + if(!_notBusy(410L)) + return false; //Datasheet says erasing a sector takes 400ms max + + //_writeDisable(); //_writeDisable() is not required because the Write Enable Latch (WEL) flag is cleared to 0 + // i.e. to write disable state upon the following conditions: + // Power-up, Write Disable, Page Program, Quad Page Program, ``Sector Erase``, Block Erase, Chip Erase, Write Status Register, + // Erase Security Register and Program Security register + + return true; +} +// Variant B +bool SPIFlash::eraseSector(uint16_t page_number, uint8_t offset) { + uint32_t address = _getAddress(page_number, offset); + return eraseSector(address); +} + +//Erases one 32k block. Has two variants: +// A. Takes the address as the argument and erases the block containing the address. +// B. Takes page to be erased as the argument and erases the block containing the page. +// The blocks are numbered 0 - 31 containing 128 pages each. +// Page 0-127 --> Block 0; Page 128-255 --> Block 1;......Page 3968-4095 --> Block 31 +// Variant A +bool SPIFlash::eraseBlock32K(uint32_t address) { + if(!_notBusy()||!_writeEnable()) + return false; + + _cmd(BLOCK32ERASE); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, 0x00); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(0); + CHIP_DESELECT + #endif + + if(!_notBusy(410L)) + return false; //Datasheet says erasing a sector takes 400ms max + + //_writeDisable(); //_writeDisable() is not required because the Write Enable Latch (WEL) flag is cleared to 0 + // i.e. to write disable state upon the following conditions: + // Power-up, Write Disable, Page Program, Quad Page Program, Sector Erase, ``Block Erase``, Chip Erase, Write Status Register, + // Erase Security Register and Program Security register + + return true; +} +// Variant B +bool SPIFlash::eraseBlock32K(uint16_t page_number, uint8_t offset) { + uint32_t address = _getAddress(page_number, offset); + return eraseBlock32K(address); +} + +//Erases one 64k block. Has two variants: +// A. Takes the address as the argument and erases the block containing the address. +// B. Takes page to be erased as the argument and erases the block containing the page. +// The blocks are numbered 0 - 15 containing 256 pages each. +// Page 0-255 --> Block 0; Page 256-511 --> Block 1;......Page 3840-4095 --> Block 15 +// Variant A +bool SPIFlash::eraseBlock64K(uint32_t address) { + if(!_notBusy()||!_writeEnable()) + return false; + + _cmd(BLOCK64ERASE); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, 0x00); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(0); + CHIP_DESELECT + #endif + + if(!_notBusy(410L)) + return false; //Datasheet says erasing a sector takes 400ms max + + //_writeDisable(); //_writeDisable() is not required because the Write Enable Latch (WEL) flag is cleared to 0 + // i.e. to write disable state upon the following conditions: + // Power-up, Write Disable, Page Program, Quad Page Program, Sector Erase, ``Block Erase``, Chip Erase, Write Status Register, + // Erase Security Register and Program Security register + + return true; +} +// Variant B +bool SPIFlash::eraseBlock64K(uint16_t page_number, uint8_t offset) { + uint32_t address = _getAddress(page_number, offset); + return eraseBlock64K(address); +} + +//Erases whole chip. Think twice before using. +bool SPIFlash::eraseChip(void) { + if(!_notBusy()||!_writeEnable()) + return false; + + _cmd(CHIPERASE, NO_CONTINUE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + + if(!_notBusy(7000L)) + return false; //Datasheet says erasing chip takes 6s max + + //_writeDisable(); //_writeDisable() is not required because the Write Enable Latch (WEL) flag is cleared to 0 + // i.e. to write disable state upon the following conditions: + // Power-up, Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, ``Chip Erase``, Write Status Register, + // Erase Security Register and Program Security register + + return true; + +} + +//Suspends current Block Erase/Sector Erase/Page Program. Does not suspend chipErase(). +//Page Program, Write Status Register, Erase instructions are not allowed. +//Erase suspend is only allowed during Block/Sector erase. +//Program suspend is only allowed during Page/Quad Page Program +bool SPIFlash::suspendProg(void) { + if(_notBusy() || !_noSuspend()) + return false; + + _cmd(SUSPEND, NO_CONTINUE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + + _delay_us(20); + + if(!_notBusy() || _noSuspend()) //Max suspend Enable time according to datasheet + return false; + return true; +} + +//Resumes previously suspended Block Erase/Sector Erase/Page Program. +bool SPIFlash::resumeProg(void) { + if(!_notBusy() || _noSuspend()) + return false; + + _cmd(RESUME, NO_CONTINUE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + + _delay_us(20); + + if(_notBusy() || !_noSuspend()) + return false; + return true; + +} + +//Puts device in low power state. Good for battery powered operations. +//Typical current consumption during power-down is 1mA with a maximum of 5mA. (Datasheet 7.4) +//In powerDown() the chip will only respond to powerUp() +bool SPIFlash::powerDown(void) { + if(!_notBusy()) + return false; + + _cmd(POWERDOWN, NO_CONTINUE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + _delay_us(3); //Max powerDown enable time according to the Datasheet + + uint8_t status1 = _readStat1(); + uint8_t status2 = _readStat1(); + status1 = _readStat1(); + + if (status1 != 255 && status2 != 255) { + if (status1 == status2 || status1 == 0 || status2 == 0) { + status1 = _readStat1(); + status2 = _readStat1(); + } + else if (status1 != status2) + return true; + } + else if (status1 == 255 && status2 == 255) + return true; + else if (status1 == 0 && status2 == 0) + return false; + return true; +} + +//Wakes chip from low power state. +bool SPIFlash::powerUp(void) { + + _cmd(RELEASE, NO_CONTINUE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + _delay_us(3); //Max release enable time according to the Datasheet + + if (_readStat1() == 255) + return false; + return true; +} + +/************************************************************************************************************************ + These functions are deprecated to enable compatibility with various AVR chips. They can be used by uncommenting + this block of code. However, be warned, this particular block of code has only been tested with the Arduino + IDE (1.6.5) and only with 8-bit AVR based Arduino boards and is not supported from library version 2.0 onward + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + // These functions work with data to/from Serial stream. // + // Declares Serial.begin() if not previously declared. // + // Initiates Serial at 115200 baud. // + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + + + This function is deprecated to enable compatibility with various AVR chips. It can be used by uncommenting + this block of code. However, be warned, this particular block of code has only been tested with the Arduino + IDE and only with 8-bit AVR based Arduino boards. + +//Prints hex/dec formatted data from page reads - for debugging +void SPIFlash::_printPageBytes(uint8_t *data_buffer, uint8_t outputType) { + char buffer[10]; + for (int a = 0; a < 16; ++a) { + for (int b = 0; b < 16; ++b) { + if (outputType == 1) { + sprintf(buffer, "%02x", data_buffer[a * 16 + b]); + Serial.print(buffer); + } + else if (outputType == 2) { + uint8_t x = data_buffer[a * 16 + b]; + if (x < 10) Serial.print("0"); + if (x < 100) Serial.print("0"); + Serial.print(x); + Serial.print(','); + } + } + Serial.println(); + } +} + +//Reads a string from Serial +bool SPIFlash::readSerialStr(String &inputStr) { + if(!Serial) + Serial.begin(115200); + while (Serial.available()) { + inputStr = Serial.readStringUntil('\n'); + return true; + } + return false; +} + +//Reads a page of data and prints it to Serial stream. Make sure the sizeOf(uint8_t data_buffer[]) == 256. +void SPIFlash::printPage(uint16_t page_number, uint8_t outputType, bool fastRead) { + if(!Serial) + Serial.begin(115200); + + char buffer[24]; + sprintf(buffer, "Reading page (%04x)", page_number); + Serial.println(buffer); + + uint8_t data_buffer[256]; + readPage(page_number, data_buffer, fastRead); + _printPageBytes(data_buffer, outputType); +} + +//Reads all pages on Flash chip and dumps it to Serial stream. +//This function is useful when extracting data from a flash chip onto a computer as a text file. +void SPIFlash::printAllPages(uint8_t outputType, bool fastRead) { + if(!Serial) + Serial.begin(115200); + + Serial.println("Reading all pages"); + uint8_t data_buffer[256]; + + for (int a = 0; a < maxPage; a++) { + readPage(a, data_buffer, fastRead); + _printPageBytes(data_buffer, outputType); + } +} +************************************************************************************************************************/ diff --git a/tools/olimexino-32u4 firmware/iceprog-nano/SPIFlash.h b/tools/olimexino-32u4 firmware/iceprog-nano/SPIFlash.h new file mode 100644 index 0000000..5158d5f --- /dev/null +++ b/tools/olimexino-32u4 firmware/iceprog-nano/SPIFlash.h @@ -0,0 +1,267 @@ +/* Arduino SPIFlash Library v.2.2.0 + * Copyright (C) 2015 by Prajwal Bhattaram + * Modified by Prajwal Bhattaram - 24/11/2015 + * + * This file is part of the Arduino SPIFlash Library. This library is for + * Winbond NOR flash memory modules. In its current form it enables reading + * and writing individual data variables, structs and arrays from and to various locations; + * reading and writing pages; continuous read functions; sector, block and chip erase; + * suspending and resuming programming/erase and powering down for low power operation. + * + * This Library is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This Library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License v3.0 + * along with the Arduino SPIFlash Library. If not, see + * . + */ + +#ifndef SPIFLASH_H +#define SPIFLASH_H + +#include + +class SPIFlash { +public: + //----------------------------------------------Constructor-----------------------------------------------// + SPIFlash(uint8_t cs = 10, bool overflow = true); + //----------------------------------------Initial / Chip Functions----------------------------------------// + void begin(); + uint16_t getManID(); + uint32_t getJEDECID(); + bool getAddress(uint16_t size, uint16_t &page_number, uint8_t &offset); + uint32_t getAddress(uint16_t size); + uint16_t getChipName(); + uint16_t sizeofStr(String &inputStr); + uint32_t getCapacity(); + uint32_t getMaxPage(); + //-------------------------------------------Write / Read Bytes-------------------------------------------// + bool writeByte(uint32_t address, uint8_t data, bool errorCheck = true); + bool writeByte(uint16_t page_number, uint8_t offset, uint8_t data, bool errorCheck = true); + uint8_t readByte(uint16_t page_number, uint8_t offset, bool fastRead = false); + uint8_t readByte(uint32_t address, bool fastRead = false); + //----------------------------------------Write / Read Byte Arrays----------------------------------------// + bool writeByteArray(uint32_t address, uint8_t *data_buffer, uint16_t bufferSize, bool errorCheck = true); + bool writeByteArray(uint16_t page_number, uint8_t offset, uint8_t *data_buffer, uint16_t bufferSize, bool errorCheck = true); + uint8_t readByteArray(uint32_t address, uint8_t *data_buffer, uint16_t bufferSize, bool fastRead = false); + uint8_t readByteArray(uint16_t page_number, uint8_t offset, uint8_t *data_buffer, uint16_t bufferSize, bool fastRead = false); + //-------------------------------------------Write / Read Chars-------------------------------------------// + bool writeChar(uint32_t address, int8_t data, bool errorCheck = true); + bool writeChar(uint16_t page_number, uint8_t offset, int8_t data, bool errorCheck = true); + int8_t readChar(uint32_t address, bool fastRead = false); + int8_t readChar(uint16_t page_number, uint8_t offset, bool fastRead = false); + //----------------------------------------Write / Read Char Arrays----------------------------------------// + bool writeCharArray(uint32_t address, char *data_buffer, uint16_t bufferSize, bool errorCheck = true); + bool writeCharArray(uint16_t page_number, uint8_t offset, char *data_buffer, uint16_t bufferSize, bool errorCheck = true); + uint8_t readCharArray(uint32_t address, char *data_buffer, uint16_t buffer_size, bool fastRead = false); + uint8_t readCharArray(uint16_t page_number, uint8_t offset, char *data_buffer, uint16_t buffer_size, bool fastRead = false); + //------------------------------------------Write / Read Shorts------------------------------------------// + bool writeShort(uint32_t address, int16_t data, bool errorCheck = true); + bool writeShort(uint16_t page_number, uint8_t offset, int16_t data, bool errorCheck = true); + int16_t readShort(uint32_t address, bool fastRead = false); + int16_t readShort(uint16_t page_number, uint8_t offset, bool fastRead = false); + //-------------------------------------------Write / Read Words-------------------------------------------// + bool writeWord(uint32_t address, uint16_t data, bool errorCheck = true); + bool writeWord(uint16_t page_number, uint8_t offset, uint16_t data, bool errorCheck = true); + uint16_t readWord(uint32_t address, bool fastRead = false); + uint16_t readWord(uint16_t page_number, uint8_t offset, bool fastRead = false); + //-------------------------------------------Write / Read Longs-------------------------------------------// + bool writeLong(uint32_t address, int32_t data, bool errorCheck = true); + bool writeLong(uint16_t page_number, uint8_t offset, int32_t data, bool errorCheck = true); + int32_t readLong(uint32_t address, bool fastRead = false); + int32_t readLong(uint16_t page_number, uint8_t offset, bool fastRead = false); + //--------------------------------------Write / Read Unsigned Longs---------------------------------------// + bool writeULong(uint32_t address, uint32_t data, bool errorCheck = true); + bool writeULong(uint16_t page_number, uint8_t offset, uint32_t data, bool errorCheck = true); + uint32_t readULong(uint32_t address, bool fastRead = false); + uint32_t readULong(uint16_t page_number, uint8_t offset, bool fastRead = false); + //-------------------------------------------Write / Read Floats------------------------------------------// + bool writeFloat(uint32_t address, float data, bool errorCheck = true); + bool writeFloat(uint16_t page_number, uint8_t offset, float data, bool errorCheck = true); + float readFloat(uint32_t address, bool fastRead = false); + float readFloat(uint16_t page_number, uint8_t offset, bool fastRead = false); + //------------------------------------------Write / Read Strings------------------------------------------// + bool writeStr(uint32_t address, String &inputStr, bool errorCheck = true); + bool writeStr(uint16_t page_number, uint8_t offset, String &inputStr, bool errorCheck = true); + bool readStr(uint32_t address, String &outStr, bool fastRead = false); + bool readStr(uint16_t page_number, uint8_t offset, String &outStr, bool fastRead = false); + //-------------------------------------------Write / Read Pages-------------------------------------------// + bool writePage(uint16_t page_number, uint8_t *data_buffer, bool errorCheck = true); + bool readPage(uint16_t page_number, uint8_t *data_buffer, bool fastRead = false); + //------------------------------------------Write / Read Anything-----------------------------------------// + template bool writeAnything(uint32_t address, const T& value, bool errorCheck = true); + template bool writeAnything(uint16_t page_number, uint8_t offset, const T& value, bool errorCheck = true); + template bool readAnything(uint32_t address, T& value, bool fastRead = false); + template bool readAnything(uint16_t page_number, uint8_t offset, T& value, bool fastRead = false); + //--------------------------------------------Erase functions---------------------------------------------// + bool eraseSector(uint32_t address); + bool eraseSector(uint16_t page_number, uint8_t offset); + bool eraseBlock32K(uint32_t address); + bool eraseBlock32K(uint16_t page_number, uint8_t offset); + bool eraseBlock64K(uint32_t address); + bool eraseBlock64K(uint16_t page_number, uint8_t offset); + bool eraseChip(void); + //---------------------------------------------Power functions--------------------------------------------// + bool suspendProg(void); + bool resumeProg(void); + bool powerDown(void); + bool powerUp(void); + //--------------------------------------------Private functions-------------------------------------------// +private: + void _troubleshoot(uint8_t error); + void _cmd(uint8_t cmd, bool _continue = true, uint8_t cs = 0); + void _endProcess(void); + void _errorCodeCheck(void); + void _beginRead(uint32_t address); + void _beginFastRead(uint32_t address); + bool _noSuspend(void); + bool _notBusy(uint32_t timeout = 10L); + bool _notPrevWritten(uint32_t address, uint8_t size = 1); + bool _addressCheck(uint32_t address); + bool _beginWrite(uint32_t address); + bool _writeNextByte(uint8_t c, bool _continue = true); + bool _writeEnable(void); + bool _writeDisable(void); + bool _getJedecId(uint8_t *b1, uint8_t *b2, uint8_t *b3); + bool _getManId(uint8_t *b1, uint8_t *b2); + bool _chipID(void); + uint8_t _readStat1(void); + uint8_t _readNextByte(bool _continue = true); + uint32_t _getAddress(uint16_t page_number, uint8_t offset = 0); + uint32_t _prepRead(uint32_t address); + uint32_t _prepRead(uint16_t page_number, uint8_t offset = 0); + uint32_t _prepWrite(uint32_t address); + uint32_t _prepWrite(uint16_t page_number, uint8_t offset = 0); + template bool _writeErrorCheck(uint32_t address, const T& value); + //-------------------------------------------Private variables------------------------------------------// + bool pageOverflow; + volatile uint8_t *cs_port; + uint8_t cs_mask, csPin, errorcode; + uint16_t name; + uint32_t capacity, maxPage; + uint32_t currentAddress = 1; + const uint8_t devType[10] = {0x5, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17}; + const uint32_t memSize[10] = {64L * 1024L, 128L * 1024L, 256L * 1024L, 512L * 1024L, 1L * 1024L * 1024L, + 2L * 1024L * 1024L, 4L * 1024L * 1024L, 8L * 1024L * 1024L, 16L * 1024L * 1024L}; + const uint16_t chipName[10] = {05, 10, 20, 40, 80, 16, 32, 64, 128, 256}; +}; + + + //--------------------------------------------Templates-------------------------------------------// + +// Writes any type of data to a specific location in the flash memory. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. T& value --> Variable to return data into +// 4. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. const T& value --> Variable with the data to be written +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +template bool SPIFlash::writeAnything(uint32_t address, const T& value, bool errorCheck) { + if (!_prepWrite(address)) + return false; + else { + const byte* p = (const byte*)(const void*)&value; + _beginWrite(address); + for (uint16_t i = 0; i < sizeof(value); i++) { + #if defined (__arm__) && defined (__SAM3X8E__) + if (i == sizeof(value)-1) + _writeNextByte(*p++, false); + #endif + _writeNextByte(*p++); + } + _endProcess(); + } + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, value); +} +// Variant B +template bool SPIFlash::writeAnything(uint16_t page_number, uint8_t offset, const T& value, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + return writeAnything(address, value, errorCheck); +} + +// Reads any type of data from a specific location in the flash memory. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. T& value --> Variable to return data into +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. T& value --> Variable to return data into +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +template bool SPIFlash::readAnything(uint32_t address, T& value, bool fastRead) { + if (!_prepRead(address)) + return false; + + byte* p = (byte*)(void*)&value; + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + for (uint16_t i = 0; i < sizeof(value); i++) { + #if defined (__arm__) && defined (__SAM3X8E__) + if (i == sizeof(value)-1) + *p++ = _readNextByte(false); + #endif + *p++ =_readNextByte(); + } + _endProcess(); + return true; +} +// Variant B +template bool SPIFlash::readAnything(uint16_t page_number, uint8_t offset, T& value, bool fastRead) +{ + uint32_t address = _getAddress(page_number, offset); + return readAnything(address, value, fastRead); +} + +// Private template to check for errors in writing to flash memory +template bool SPIFlash::_writeErrorCheck(uint32_t address, const T& value) { +if (!_prepRead(address)) + return false; + + const byte* p = (const byte*)(const void*)&value; + _beginRead(address); + for(uint16_t i = 0; i < sizeof(value);i++) + { + #if defined (__arm__) && defined (__SAM3X8E__) + if (i == sizeof(value)-1) { + if (*p++ != _readNextByte(false)) + return false; + else + return true; + } + else + if (*p++ != _readNextByte()) + return false; + #elif defined (__AVR__) + if (*p++ != _readNextByte()) + return false; + #endif + } + _endProcess(); + return true; +} + + +#endif // _SPIFLASH_H_ diff --git a/tools/olimexino-32u4 firmware/iceprog-nano/iceprog-nano.ino b/tools/olimexino-32u4 firmware/iceprog-nano/iceprog-nano.ino new file mode 100644 index 0000000..2ee2d9b --- /dev/null +++ b/tools/olimexino-32u4 firmware/iceprog-nano/iceprog-nano.ino @@ -0,0 +1,399 @@ +/* + * iceprog -- firmware scetch for Arduino based Lattice iCE programmers + * + * Chris B. @ Olimex Ltd. 2017 + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Relevant Documents: + * ------------------- + * http://www.latticesemi.com/~/media/Documents/UserManuals/EI/icestickusermanual.pdf + * http://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_32mb_3v_65nm.pdf + * http://www.ftdichip.com/Support/Documents/AppNotes/AN_108_Command_Processor_for_MPSSE_and_MCU_Host_Bus_Emulation_Modes.pdf + * https://www.olimex.com/Products/FPGA/iCE40/iCE40HX1K-EVB/ + * https://github.com/Marzogh/SPIFlash + */ + +#include + +// The demo uses SPIFlash v2.2.0, its files are included in the project folders the author is Prajwal Bhattaram - Marzogh + +#include "SPIFlash.h" + +#define LED 17 +#define CDONE 3 +#define RESET 2 +#define UEXT_POWER 8 +#define CS 13 + +//commands list +#define READ_ID 0x9F +#define PWR_UP 0xAB +#define PWR_DOWN 0xB9 +#define WR_EN 0x06 +#define BULK_ERASE 0xC7 +#define SEC_ERASE 0xd8 +#define PROG 0x02 +#define READ 0x03 +#define READ_ALL 0x83 +#define CMD_ERROR 0xee +#define READY 0x44 +#define EMPTY 0x45 + +#define FEND 0xc0 +#define FESC 0xdb +#define TFEND 0xdc +#define TFESC 0xdd + +#define cselect digitalWrite(CS,LOW) +#define deselect digitalWrite(CS,HIGH) + +//Toggle iceprogduino with serial bridge by pressing the HWB button +#define HWB (PINE & B00000100)==0 // Check if the button has been pressed +#define HWB_INPUT DDRE &= B11111011 // Initialize the port +#define HWB_PULL_UP PORTE |= B00000100 // Initialize the port + +boolean isProg; + +uint8_t rxframe[512], txframe[512], fcs,rfcs; +uint8_t membuf[256]; +uint8_t data_buffer[256]; +uint16_t txp; +uint32_t maxPage; +bool escaped; +SPIFlash flash(CS); + +void secerase(uint32_t sector); +void decodeFrame(void); +void writepage(int pagenr); +bool readSerialFrame(void); +void flash_bulk_erase(void); +void SendID(void); +void sendframe(); +void startframe(uint8_t command); +void addbyte(uint8_t newbyte); +void readAllPages(void); +void readpage(uint16_t adr); + +// FRAME: {data if any} +// if FEND, FESC in data - =; = + +void setup() { + // put your setup code here, to run once: + // Power Up UEXT + pinMode(CDONE,INPUT); + pinMode(RESET,OUTPUT); + pinMode(LED,OUTPUT); + digitalWrite(LED,0); + pinMode(CS,OUTPUT); + digitalWrite(CS,HIGH); + pinMode(UEXT_POWER, OUTPUT); + digitalWrite(UEXT_POWER, HIGH); + delay(1000); + digitalWrite(UEXT_POWER, LOW); + delay(500); + digitalWrite(RESET, HIGH); + Serial.begin(230400); + while (!Serial); + + isProg=true; + HWB_INPUT; // Initialize HWB + HWB_PULL_UP; + Serial1.begin(115200); + digitalWrite(LED,!isProg); //Yellow LED is Prog +} + +void loop(){ + if (isProg) loopProg(); + else loopBridge(); + if (HWB) { + isProg = !isProg; + digitalWrite(LED,!isProg); + delay(1000); + } +} + +void loopBridge(){ + // read from port 1, send to port 0: + if (Serial1.available()) { + int inByte = Serial1.read(); + Serial.write(inByte); + } + + // read from port 0, send to port 1: + if (Serial.available()) { + int inByte = Serial.read(); + Serial1.write(inByte); + } +} + +void loopProg() { + + if (readSerialFrame()) + { + decodeFrame(); + if (rfcs==0xff) + { + digitalWrite(RESET, LOW); + + switch (rxframe[0]){ + + case FEND: + break; + + case READ_ID: + SendID(); + break; + + case BULK_ERASE: + flash_bulk_erase(); + break; + + case SEC_ERASE: + flash.powerUp(); + secerase((rxframe[1]<<8) | rxframe[2]); + flash.powerDown(); + + break; + + case READ: + flash.powerUp(); + readpage((rxframe[1]<<8) | rxframe[2]); + flash.powerDown(); + break; + + case READ_ALL: + readAllPages(); + break; + + case PROG: + writepage((rxframe[1]<<8) | rxframe[2]); + break; + + default: + break; + + + }//switch + digitalWrite(RESET, HIGH); + + } + + } +} + + +void secerase(uint32_t sector){ + flash.eraseBlock64K(sector<<8); + startframe(READY); + sendframe(); + +} +void decodeFrame(void){ + int x,y; + escaped = false; + y = 1; + rfcs = rxframe[1]; + rxframe[0]=rxframe[1]; + for (x=2;x<512;x++) + { + switch (rxframe[x]){ + + case FEND: + x = 513; + break; + + case FESC: + escaped = true; + break; + + case TFEND: + if (escaped) + { + rxframe[y++] = FEND; + rfcs+=FEND; + escaped = false; + } + else + { + rxframe[y++]=TFEND; + rfcs+=TFEND; + } + + break; + + case TFESC: + if (escaped) + { + rxframe[y++]=FESC; + rfcs+=FESC; + escaped = false; + } + else + { + rxframe[y++]=TFESC; + rfcs+=TFESC; + } + + break; + + default: + escaped = false; + rxframe[y++] = rxframe[x]; + rfcs+=rxframe[x]; + break; + } + + } + +} + +void writepage(int pagenr){ +int x; +flash.powerUp(); + +for (x=0; x<256;x++) + membuf[x]=rxframe[x+3]; + +flash.writePage(pagenr,membuf); +flash.readPage(pagenr,data_buffer); +flash.powerDown(); + + for (int a = 0; a < 256; a++) + if (data_buffer[a] != membuf[a]) + return; + + startframe(READY); + sendframe(); + + +} + + + +//Reads a frame from Serial +bool readSerialFrame(void) +{ + Serial.setTimeout(50); + + if (!Serial) + Serial.begin(230400); + // Serial.begin(1000000); + while (Serial.available()) { + Serial.readBytesUntil(FEND,rxframe,512); + //if (rxframe[0]!=FEND) + return true; + } + return false; +} +void flash_bulk_erase(void) +{ + flash.powerUp(); + flash.eraseChip(); + flash.powerDown(); + startframe(READY); + addbyte(BULK_ERASE); + sendframe(); +} + +void SendID(void) +{ + + flash.powerUp(); + uint32_t JEDEC = flash.getJEDECID(); + flash.powerDown(); + startframe(READ_ID); + addbyte(JEDEC >> 16); + addbyte(JEDEC >> 8); + addbyte(JEDEC >> 0); + sendframe(); + + +} + + +void sendframe(){ + fcs = 0xff - fcs; + addbyte(fcs); + txframe[txp++] = FEND; + Serial.write(txframe,txp); + +} + + +void startframe(uint8_t command){ + txframe[0]=FEND; + txframe[1]=command; + txp = 2; + fcs = command; +} +void addbyte(uint8_t newbyte) +{ +fcs+=newbyte; +if (newbyte == FEND) +{ + txframe[txp++] = FESC; + txframe[txp++] = TFEND; +} else + if (newbyte == FESC) + { + txframe[txp++] = FESC; + txframe[txp++] = TFESC; + } else + txframe[txp++] = newbyte; + +} + + +void readAllPages(void){ +flash.powerUp(); +maxPage=0x2000; +delay(10); +int p; +for (p=0;p> 8); + addbyte(adr >> 0); + for (int b = 0;b<256;b++) + addbyte(data_buffer[b]); + sendframe(); + sendempty=false; + break; + + } + + } + if (sendempty){ + startframe(EMPTY); + addbyte(adr >> 8); + addbyte(adr >> 0); + sendframe(); + } +} diff --git a/tools/olimexino-32u4 firmware/iceprog.ino b/tools/olimexino-32u4 firmware/iceprog.ino new file mode 100644 index 0000000..40d9134 --- /dev/null +++ b/tools/olimexino-32u4 firmware/iceprog.ino @@ -0,0 +1,406 @@ +/* + * iceprog -- firmware scetch for Arduino based Lattice iCE programmers + * + * Chris B. @ Olimex Ltd. 2017 + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Relevant Documents: + * ------------------- + * http://www.latticesemi.com/~/media/Documents/UserManuals/EI/icestickusermanual.pdf + * http://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_32mb_3v_65nm.pdf + * http://www.ftdichip.com/Support/Documents/AppNotes/AN_108_Command_Processor_for_MPSSE_and_MCU_Host_Bus_Emulation_Modes.pdf + * https://www.olimex.com/Products/FPGA/iCE40/iCE40HX1K-EVB/ + * https://github.com/Marzogh/SPIFlash + */ + +#include + +// The demo uses SPIFlash v2.2.0, its files are included in the project folders the author is Prajwal Bhattaram - Marzogh + +#include "SPIFlash.h" + +#define LED 17 +#define CDONE 3 +#define RESET 2 +#define UEXT_POWER 8 +#define CS 13 + +//commands list +#define READ_ID 0x9F +#define PWR_UP 0xAB +#define PWR_DOWN 0xB9 +#define WR_EN 0x06 +#define BULK_ERASE 0xC7 +#define SEC_ERASE 0xd8 +#define PROG 0x02 +#define READ 0x03 +#define READ_ALL 0x83 +#define CMD_ERROR 0xee +#define READY 0x44 +#define EMPTY 0x45 + +#define FEND 0xc0 +#define FESC 0xdb +#define TFEND 0xdc +#define TFESC 0xdd + +#define cselect digitalWrite(CS,LOW) +#define deselect digitalWrite(CS,HIGH) + +//Toggle iceprogduino with serial bridge by pressing the HWB button +#define HWB (PINE & B00000100)==0 // Check if the button has been pressed +#define HWB_INPUT DDRE &= B11111011 // Initialize the port +#define LED_G 7 // The GREEN LED is on Pin 7 +#define LED_Y 9 // The YELLOW LED is on Pin 9 +boolean isProg; + +uint8_t rxframe[512], txframe[512], fcs,rfcs; +uint8_t membuf[256]; +uint8_t data_buffer[256]; +uint16_t txp; +uint32_t maxPage; +bool escaped; +SPIFlash flash(CS); + +void secerase(uint32_t sector); +void decodeFrame(void); +void writepage(int pagenr); +bool readSerialFrame(void); +void flash_bulk_erase(void); +void SendID(void); +void sendframe(); +void startframe(uint8_t command); +void addbyte(uint8_t newbyte); +void readAllPages(void); +void readpage(uint16_t adr); +void loopProg(void); +void loopBridge(void); + + +// FRAME: {data if any} +// if FEND, FESC in data - =; = + +void setup() { + // put your setup code here, to run once: + // Power Up UEXT + pinMode(CDONE,INPUT); + pinMode(RESET,OUTPUT); + pinMode(LED,OUTPUT); + digitalWrite(LED,0); + pinMode(CS,OUTPUT); + digitalWrite(CS,HIGH); + pinMode(UEXT_POWER, OUTPUT); + digitalWrite(UEXT_POWER, HIGH); + delay(1000); + digitalWrite(UEXT_POWER, LOW); + delay(500); + digitalWrite(RESET, HIGH); + Serial.begin(230400); + while (!Serial); + + isProg=true; + HWB_INPUT; // Initialize HWB + Serial1.begin(115200); + pinMode(LED_Y,OUTPUT); + digitalWrite(LED_Y,isProg); //Yellow LED is Prog + pinMode(LED_G,OUTPUT); + digitalWrite(LED_G,!isProg); //Green LED is Bridge + +} + +void loop(){ + if (isProg) loopProg(); + else loopBridge(); + if (HWB) { + isProg = !isProg; + digitalWrite(LED_Y,isProg); + digitalWrite(LED_G,!isProg); + delay(1000); + } +} + +void loopBridge(){ + // read from port 1, send to port 0: + if (Serial1.available()) { + int inByte = Serial1.read(); + Serial.write(inByte); + } + + // read from port 0, send to port 1: + if (Serial.available()) { + int inByte = Serial.read(); + Serial1.write(inByte); + } +} + +void loopProg() { + + if (readSerialFrame()) + { + decodeFrame(); + if (rfcs==0xff) + { + digitalWrite(RESET, LOW); + + switch (rxframe[0]){ + + case FEND: + break; + + case READ_ID: + SendID(); + break; + + case BULK_ERASE: + flash_bulk_erase(); + break; + + case SEC_ERASE: + flash.powerUp(); + secerase((rxframe[1]<<8) | rxframe[2]); + flash.powerDown(); + + break; + + case READ: + flash.powerUp(); + readpage((rxframe[1]<<8) | rxframe[2]); + flash.powerDown(); + break; + + case READ_ALL: + readAllPages(); + break; + + case PROG: + writepage((rxframe[1]<<8) | rxframe[2]); + break; + + default: + break; + + + }//switch + digitalWrite(RESET, HIGH); + + } + + } +} + + +void secerase(uint32_t sector){ + flash.eraseBlock64K(sector<<8); + startframe(READY); + sendframe(); + +} +void decodeFrame(void){ + int x,y; + escaped = false; + y = 1; + rfcs = rxframe[1]; + rxframe[0]=rxframe[1]; + for (x=2;x<512;x++) + { + switch (rxframe[x]){ + + case FEND: + x = 513; + break; + + case FESC: + escaped = true; + break; + + case TFEND: + if (escaped) + { + rxframe[y++] = FEND; + rfcs+=FEND; + escaped = false; + } + else + { + rxframe[y++]=TFEND; + rfcs+=TFEND; + } + + break; + + case TFESC: + if (escaped) + { + rxframe[y++]=FESC; + rfcs+=FESC; + escaped = false; + } + else + { + rxframe[y++]=TFESC; + rfcs+=TFESC; + } + + break; + + default: + escaped = false; + rxframe[y++] = rxframe[x]; + rfcs+=rxframe[x]; + break; + } + + } + +} + +void writepage(int pagenr){ +int x; +flash.powerUp(); + +for (x=0; x<256;x++) + membuf[x]=rxframe[x+3]; + +flash.writePage(pagenr,membuf); +flash.readPage(pagenr,data_buffer); +flash.powerDown(); + + for (int a = 0; a < 256; a++) + if (data_buffer[a] != membuf[a]) + return; + + startframe(READY); + sendframe(); + + +} + + + +//Reads a frame from Serial +bool readSerialFrame(void) +{ + Serial.setTimeout(50); + + if (!Serial) + Serial.begin(230400); + // Serial.begin(1000000); + while (Serial.available()) { + Serial.readBytesUntil(FEND,rxframe,512); + //if (rxframe[0]!=FEND) + return true; + } + return false; +} +void flash_bulk_erase(void) +{ + flash.powerUp(); + flash.eraseChip(); + flash.powerDown(); + startframe(READY); + addbyte(BULK_ERASE); + sendframe(); +} + +void SendID(void) +{ + + flash.powerUp(); + uint32_t JEDEC = flash.getJEDECID(); + flash.powerDown(); + startframe(READ_ID); + addbyte(JEDEC >> 16); + addbyte(JEDEC >> 8); + addbyte(JEDEC >> 0); + sendframe(); + + +} + + +void sendframe(){ + fcs = 0xff - fcs; + addbyte(fcs); + txframe[txp++] = FEND; + Serial.write(txframe,txp); + +} + + +void startframe(uint8_t command){ + txframe[0]=FEND; + txframe[1]=command; + txp = 2; + fcs = command; +} +void addbyte(uint8_t newbyte) +{ +fcs+=newbyte; +if (newbyte == FEND) +{ + txframe[txp++] = FESC; + txframe[txp++] = TFEND; +} else + if (newbyte == FESC) + { + txframe[txp++] = FESC; + txframe[txp++] = TFESC; + } else + txframe[txp++] = newbyte; + +} + + +void readAllPages(void){ +flash.powerUp(); +maxPage=0x2000; +delay(10); +int p; +for (p=0;p> 8); + addbyte(adr >> 0); + for (int b = 0;b<256;b++) + addbyte(data_buffer[b]); + sendframe(); + sendempty=false; + break; + + } + + } + if (sendempty){ + startframe(EMPTY); + addbyte(adr >> 8); + addbyte(adr >> 0); + sendframe(); + } +} diff --git a/tools/olimexino-32u4 firmware/iceprog/SPIFlash.cpp b/tools/olimexino-32u4 firmware/iceprog/SPIFlash.cpp new file mode 100644 index 0000000..858481f --- /dev/null +++ b/tools/olimexino-32u4 firmware/iceprog/SPIFlash.cpp @@ -0,0 +1,1961 @@ +/* Arduino SPIFlash Library v.2.2.0 + * Copyright (C) 2015 by Prajwal Bhattaram + * Modified by Prajwal Bhattaram - 24/11/2015 + * + * This file is part of the Arduino SPIFlash Library. This library is for + * Winbond NOR flash memory modules. In its current form it enables reading + * and writing individual data variables, structs and arrays from and to various locations; + * reading and writing pages; continuous read functions; sector, block and chip erase; + * suspending and resuming programming/erase and powering down for low power operation. + * + * This Library is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This Library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License v3.0 + * along with the Arduino SPIFlash Library. If not, see + * . + */ + +#include "SPIFlash.h" + +#if defined (__arm__) && defined (__SAM3X8E__) + #define _delay_us(us) delayMicroseconds(us) +#else + #include +#endif + +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +// Uncomment the code below to run a diagnostic if your flash // +// does not respond // +// // +// Error codes will be generated and returned on functions // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +//#define RUNDIAGNOSTIC // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +// Uncomment the code below to increase the speed of the library // +// by disabling _notPrevWritten() // +// // +// Make sure the sectors being written to have been erased beforehand // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +#if defined (__SAM3X8E__) +//#define HIGHSPEED +#elif defined (__AVR__) +//#define HIGHSPEED +#endif +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + +#define _MANID 0xEF +#define PAGESIZE 0x100 + +#define MANID 0x90 +#define PAGEPROG 0x02 +#define READDATA 0x03 +#define FASTREAD 0x0B +#define WRITEDISABLE 0x04 +#define READSTAT1 0x05 +#define READSTAT2 0x35 +#define WRITEENABLE 0x06 +#define SECTORERASE 0x20 +#define BLOCK32ERASE 0x52 +#define CHIPERASE 0x60 +#define SUSPEND 0x75 +#define ID 0x90 +#define RESUME 0x7A +#define JEDECID 0x9f +#define RELEASE 0xAB +#define POWERDOWN 0xB9 +#define BLOCK64ERASE 0xD8 + +#define BUSY 0x01 +#define WRTEN 0x02 +#define SUS 0x40 +#define DUMMYBYTE 0xEE + +#define arrayLen(x) (sizeof(x) / sizeof(*x)) +#define lengthOf(x) (sizeof(x))/sizeof(byte) +#define maxAddress capacity +#define NO_CONTINUE 0x00 +#define PASS 0x01 +#define FAIL 0x00 + +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +// List of Error codes // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + #ifdef RUNDIAGNOSTIC + + #define SUCCESS 0x00 + #define CALLBEGIN 0x01 + #define UNKNOWNCHIP 0x02 + #define UNKNOWNCAP 0x03 + #define CHIPBUSY 0x04 + #define OUTOFBOUNDS 0x05 + #define CANTENWRITE 0x06 + #define PREVWRITTEN 0x07 + #define UNKNOWNERROR 0xFF + + #endif + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + +#if defined (__arm__) && defined (__SAM3X8E__) + #include +#elif defined (__AVR__) + #ifdef __AVR_ATtiny85__ + #define CHIP_SELECT PORTB &= ~cs_mask; + #define CHIP_DESELECT PORTB |= cs_mask; + #define SPIBIT \ + USICR = ((1< + #define CHIP_SELECT *cs_port &= ~cs_mask; + #define CHIP_DESELECT *cs_port |= cs_mask; + #define xfer(n) SPI.transfer(n) + #endif +#endif + +// Constructor +#if defined (__arm__) && defined (__SAM3X8E__) +SPIFlash::SPIFlash(uint8_t cs, bool overflow) { + csPin = cs; + pageOverflow = overflow; +} +#elif defined (__AVR__) +SPIFlash::SPIFlash(uint8_t cs, bool overflow) { + csPin = cs; +#ifndef __AVR_ATtiny85__ + cs_port = portOutputRegister(digitalPinToPort(csPin)); +#endif + cs_mask = digitalPinToBitMask(csPin); + SPI.begin(); + SPI.setDataMode(0); + SPI.setBitOrder(MSBFIRST); + //SPI.setClockDivider(SPI_CLOCK_DIV2); + pageOverflow = overflow; + pinMode(cs, OUTPUT); +} +#endif + +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +// Private functions used by read, write and erase operations // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + +// Select chip and issue command - data to follow +void SPIFlash::_cmd(uint8_t cmd, bool _continue, uint8_t cs) { + cs = csPin; + #if defined (__arm__) && defined (__SAM3X8E__) + if (!_continue) + SPI.transfer(cs, cmd); + else + SPI.transfer(cs, cmd, SPI_CONTINUE); + #else + CHIP_SELECT + (void)xfer(cmd); + #endif +} + +// Checks if status register 1 can be accessed - used during powerdown and power up and for debugging +uint8_t SPIFlash::_readStat1(void) { + uint8_t stat1; + _cmd(READSTAT1); + #if defined (__SAM3X8E__) + stat1 = SPI.transfer(csPin, 0x00); + #else + stat1 = xfer(0); + CHIP_DESELECT + #endif + return stat1; +} + +// Checks the erase/program suspend flag before enabling/disabling a program/erase suspend operation +bool SPIFlash::_noSuspend(void) { + uint8_t state; + + _cmd(READSTAT2); + #if defined (__arm__) && defined (__SAM3X8E__) + state = SPI.transfer(csPin, 0x00); + #else + state = xfer(0); + CHIP_DESELECT + #endif + + if(state & SUS) + return false; + return true; +} + +// Polls the status register 1 until busy flag is cleared or timeout +bool SPIFlash::_notBusy(uint32_t timeout) { + uint8_t state; + uint32_t startTime = millis(); + + do { + _cmd(READSTAT1); + #if defined (__arm__) && defined (__SAM3X8E__) + state = SPI.transfer(csPin, 0x00); + #else + state = xfer(0); + CHIP_DESELECT + #endif + if((millis()-startTime) > timeout){ + #ifdef RUNDIAGNOSTIC + errorcode = CHIPBUSY; + _troubleshoot(errorcode); + #endif + return false; + } + } while(state & BUSY); + return true; +} + +//Enables writing to chip by setting the WRITEENABLE bit +bool SPIFlash::_writeEnable(void) { + uint8_t state; + + #if defined (__arm__) && (__SAM3X8E__) + SPI.transfer(csPin, WRITEENABLE); + #else + _cmd(WRITEENABLE); + CHIP_DESELECT + #endif + + //verifies that WRITE is enabled + #if defined (__arm__) && (__SAM3X8E__) + SPI.transfer(csPin, READSTAT1, SPI_CONTINUE); + state = SPI.transfer(csPin, 0x00); + #else + _cmd(READSTAT1); + state = xfer(0); + CHIP_DESELECT + #endif + if(state & WRTEN) + return true; + else { + #ifdef RUNDIAGNOSTIC + errorcode = CANTENWRITE; + _troubleshoot(errorcode); + #endif + + return false; + } +} + +//Disables writing to chip by setting the Write Enable Latch (WEL) bit in the Status Register to 0 +//_writeDisable() is not required under the following conditions because the Write Enable Latch (WEL) flag is cleared to 0 +// i.e. to write disable state: +// Power-up, Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, +// Erase Security Register and Program Security register +bool SPIFlash::_writeDisable(void) { + _cmd(WRITEDISABLE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + + return true; +} + +//Gets address from page number and offset. Takes two arguments: +// 1. page_number --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +uint32_t SPIFlash::_getAddress(uint16_t page_number, uint8_t offset) { + uint32_t address = page_number; + address = (address << 8) + offset; + + if (!_addressCheck(address)){ + #ifdef RUNDIAGNOSTIC + errorcode = OUTOFBOUNDS; + _troubleshoot(errorcode); + #endif + return false; + } + else + return address; +} + +//Checks the device ID to establish storage parameters +bool SPIFlash::_getManId(uint8_t *b1, uint8_t *b2) { + if(!_notBusy()) + return false; + _cmd(MANID); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, 0x00, SPI_CONTINUE); + SPI.transfer(csPin, 0x00, SPI_CONTINUE); + SPI.transfer(csPin, 0x00, SPI_CONTINUE); + *b1 = SPI.transfer(csPin, 0x00, SPI_CONTINUE); + *b2 = SPI.transfer(csPin, 0x00); + #else + xfer(0); + xfer(0); + xfer(0); + *b1 = xfer(0); + *b2 = xfer(0); + CHIP_DESELECT + #endif + return true; +} + +//Checks for presence of chip by requesting JEDEC ID +bool SPIFlash::_getJedecId(uint8_t *b1, uint8_t *b2, uint8_t *b3) { + if(!_notBusy()) + return false; + _cmd(JEDECID); + #if defined (__arm__) && defined (__SAM3X8E__) + *b1 = SPI.transfer(csPin, 0x00, SPI_CONTINUE); // manufacturer id + *b2 = SPI.transfer(csPin, 0x00, SPI_CONTINUE); // manufacturer id + *b3 = SPI.transfer(csPin, 0x00); // capacity + #else + *b1 = xfer(0); // manufacturer id + *b2 = xfer(0); // memory type + *b3 = xfer(0); // capacity + CHIP_DESELECT + #endif + return true; +} + +//Identifies the chip +bool SPIFlash::_chipID(void) { + //Get Manfucturer/Device ID so the library can identify the chip + uint8_t manID, devID ; + _getManId(&manID, &devID); + + if (manID != _MANID){ //If the chip is not a Winbond Chip + #ifdef RUNDIAGNOSTIC + errorcode = UNKNOWNCHIP; //Error code for unidentified chip + _troubleshoot(errorcode); + #endif + while(1); + } + + //Check flash memory type and identify capacity + uint8_t i; + //capacity & chip name + for (i = 0; i < sizeof(devType); i++) + { + if (devID == devType[i]) { + capacity = memSize[i]; + name = chipName[i]; + } + } + if (capacity == 0) { + #ifdef RUNDIAGNOSTIC + errorcode = UNKNOWNCAP; //Error code for unidentified capacity + _troubleshoot(errorcode); + #endif + while(1); + } + + maxPage = capacity/PAGESIZE; + + /*#ifdef RUNDIAGNOSTIC + char buffer[64]; + sprintf(buffer, "Manufacturer ID: %02xh\nMemory Type: %02xh\nCapacity: %lu\nmaxPage: %d", manID, devID, capacity, maxPage); + Serial.println(buffer); + #endif*/ + return true; +} + +//Checks to see if pageOverflow is permitted and assists with determining next address to read/write. +//Sets the global address variable +bool SPIFlash::_addressCheck(uint32_t address) { + #ifdef RUNDIAGNOSTIC + if (capacity == 0) { + errorcode = CALLBEGIN; + _troubleshoot(errorcode); + } + #endif + if (address >= capacity) { + if (!pageOverflow) { + #ifdef RUNDIAGNOSTIC + errorcode = OUTOFBOUNDS; + _troubleshoot(errorcode); + #endif + return false; // At end of memory - (!pageOverflow) + } + else { + address = 0x00; // At end of memory - (pageOverflow) + return true; + } + } + return true; // Not at end of memory if (address < capacity) +} + +//Double checks all parameters before calling a Read +//Has two variants: +// A. Takes address and returns the address if true, else returns false. Throws an error if there is a problem. +// B. Takes page_number and offset and returns address. Throws an error if there is a problem +// Variant A +uint32_t SPIFlash::_prepRead(uint32_t address) { + if(!_notBusy()) + return false; + if (!_addressCheck(address)) + return false; + else + return address; +} +// Variant B +uint32_t SPIFlash::_prepRead(uint16_t page_number, uint8_t offset) { + uint32_t address = _getAddress(page_number, offset); + return _prepRead(address); +} + +//Initiates read operation - but data is not read yet +void SPIFlash::_beginRead(uint32_t address) { + _cmd(READDATA); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, address, SPI_CONTINUE); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(address); + #endif + //SPI data lines are left open until _endProcess() is called +} + +//Initiates fast read operation (can operate at the highest possible freq of 104 MHz (at 3.0-3.6V) of 80 MHz (at 2.5-3.6V)) +//- but data is not read yet +void SPIFlash::_beginFastRead(uint32_t address) { + _cmd(FASTREAD); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, address, SPI_CONTINUE); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(address); + #endif + //SPI data lines are left open until _endProcess() is called +} + +//Reads next byte. Call 'n' times to read 'n' number of bytes. Should be called after _beginRead() +uint8_t SPIFlash::_readNextByte(bool _continue) { + uint8_t result; + #if defined (__arm__) && defined (__SAM3X8E__) + if (!_continue) + result = SPI.transfer(csPin, 0x00); + else + result = SPI.transfer(csPin, 0x00, SPI_CONTINUE); + #else + result = xfer(0x00); + #endif + return result; +} + +//Double checks all parameters before initiating a write +//Has two variants: +// A. Takes address and returns address if true or 'false' if false. Throws an error if there is a problem. +// B. Takes page_number and offset and returns address. Throws an error if there is a problem +// Variant A +uint32_t SPIFlash::_prepWrite(uint32_t address) { + if(!_notBusy()||!_writeEnable()) + return false; + if (!_addressCheck(address)) { + #ifdef RUNDIAGNOSTIC + errorcode = OUTOFBOUNDS; + _troubleshoot(errorcode); + #endif + return false; + } + else + return address; +} +// Variant B +uint32_t SPIFlash::_prepWrite(uint16_t page_number, uint8_t offset) { + uint32_t address = _getAddress(page_number, offset); + return _prepWrite(address); +} + +//Initiates write operation - but data is not written yet +bool SPIFlash::_beginWrite(uint32_t address) { + _cmd(PAGEPROG); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, address, SPI_CONTINUE); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(address); + #endif + //SPI data lines are left open until _endProcess() is called + return true; +} + +//Writes next byte. Call 'n' times to read 'n' number of bytes. Should be called after _beginWrite() +bool SPIFlash::_writeNextByte(uint8_t b, bool _continue) { + #if defined (__arm__) && defined (__SAM3X8E__) + if (!_continue) + SPI.transfer(csPin, b); + else + SPI.transfer(csPin, b, SPI_CONTINUE); + #else + xfer(b); + #endif + return true; +} + +//Stops all operations. Should be called after all the required data is read/written from repeated _readNextByte()/_writeNextByte() calls +void SPIFlash::_endProcess(void) { + #if defined (__arm__) && defined (__SAM3X8E__) + _delay_us(3); + #else + CHIP_DESELECT + #endif + _delay_us(3); +} + +#ifndef HIGHSPEED +bool SPIFlash::_notPrevWritten(uint32_t address, uint8_t size) { + uint32_t _size = size; + + /*uint8_t databyte1, databyte2, databyte3; + databyte1 = readByte(address, true); + databyte2 = readByte((address + (size/2)), true); + databyte3 = readByte((address+size), true); + if (databyte1 != 255 || databyte2 != 255 || databyte3 != 255) { + #ifdef RUNDIAGNOSTIC + errorcode = PREVWRITTEN; + _troubleshoot(errorcode); + #endif + return false; + } + _delay_us(3); + return true;*/ + uint32_t sampleSize; + if (_size <= 10) { + sampleSize = _size; + } + + if (_size > 10) { + do { + sampleSize++; + _size/=10; + } while((_size/10) >= 1); + } + + uint32_t addresses[sampleSize]; + + for (uint16_t i = 0; i < sampleSize; i++) { + addresses[i] = (rand() % size) + address; + } + + for (uint16_t i = 0; i < sampleSize; i++) { + uint8_t databyte = readByte(addresses[i]); + if (databyte != 0xFF) { + #ifdef RUNDIAGNOSTIC + errorcode = PREVWRITTEN; + _troubleshoot(errorcode); + #endif + return false; + } + } + return true; +} +#endif + +#ifdef RUNDIAGNOSTIC +//Troubleshooting function. Called when #ifdef RUNDIAGNOSTIC is uncommented at the top of this file. +void SPIFlash::_troubleshoot(uint8_t error) { + + switch (error) { + case SUCCESS: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(SUCCESS, HEX); + #else + Serial.println("Action completed successfully"); + #endif + break; + + case CALLBEGIN: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(CALLBEGIN, HEX); + #else + Serial.println("*constructor_of_choice*.begin() was not called in void setup()"); + #endif + break; + + case UNKNOWNCHIP: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(UNKNOWNCHIP, HEX); + #else + Serial.println("Unable to identify chip. Are you shure this is a Winbond Flash chip"); + Serial.println("Please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with your chip type and I will try to add support to your chip"); + #endif + + break; + + case UNKNOWNCAP: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(UNKNOWNCAP, HEX); + #else + Serial.println("Unable to identify capacity."); + Serial.println("Please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with your chip type and I will work on adding support to your chip"); + #endif + break; + + case CHIPBUSY: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(CHIPBUSY, HEX); + #else + Serial.println("Chip is busy."); + Serial.println("Make sure all pins have been connected properly"); + Serial.print("If it still doesn't work, "); + Serial.println("please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with the details of what your were doing when this error occured"); + #endif + break; + + case OUTOFBOUNDS: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(OUTOFBOUNDS, HEX); + #else + Serial.println("Page overflow has been disabled and the address called exceeds the memory"); + #endif + break; + + case CANTENWRITE: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(CANTENWRITE, HEX); + #else + Serial.println("Unable to Enable Writing to chip."); + Serial.println("Please make sure the HOLD & WRITEPROTECT pins are connected properly to VCC & GND respectively"); + Serial.print("If you are still facing issues, "); + Serial.println("please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with the details of what your were doing when this error occured"); + #endif + break; + + case PREVWRITTEN: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(PREVWRITTEN, HEX); + #else + Serial.println("This sector already contains data."); + Serial.println("Please make sure the sectors being written to are erased."); + Serial.print("If you are still facing issues, "); + Serial.println("please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with the details of what your were doing when this error occured"); + #endif + break; + + default: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x"); + Serial.println(UNKNOWNERROR, HEX); + #else + Serial.println("Unknown error"); + Serial.println("Please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with the details of what your were doing when this error occured"); + #endif + break; + } +} +#endif + + +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +// Public functions used for read, write and erase operations // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + +//Identifies chip and establishes parameters +void SPIFlash::begin() { + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.begin(csPin); + SPI.setClockDivider(csPin, 21); + SPI.setDataMode(csPin, SPI_MODE0); + #endif + _chipID(); +} + +//Returns capacity of chip +uint32_t SPIFlash::getCapacity() { + return capacity; +} + +//Returns maximum number of pages +uint32_t SPIFlash::getMaxPage() { + return maxPage; +} + + +//Returns identifying name of the chip +uint16_t SPIFlash::getChipName() { + return name; +} + +//Checks for and initiates the chip by requesting JEDEC ID which is returned as a 32 bit int +uint16_t SPIFlash::getManID() { + uint8_t b1, b2; + _getManId(&b1, &b2); + uint32_t id = b1; + id = (id << 8)|(b2 << 0); + return id; +} + +//Checks for and initiates the chip by requesting JEDEC ID which is returned as a 32 bit int +uint32_t SPIFlash::getJEDECID() { + uint8_t b1, b2, b3; + _getJedecId(&b1, &b2, &b3); + uint32_t id = b1; + id = (id << 8)|(b2 << 0); + id = (id << 8)|(b3 << 0); + return id; +} + +//Gets the next available address for use. Has two variants: +// A. Takes the size of the data as an argument and returns a 32-bit address +// B. Takes a three variables, the size of the data and two other variables to return a page number value & an offset into. +// All addresses in the in the sketch must be obtained via this function or not at all. +// Variant A +uint32_t SPIFlash::getAddress(uint16_t size) { + if (!_addressCheck(currentAddress)){ + #ifdef RUNDIAGNOSTIC + errorcode = OUTOFBOUNDS; + _troubleshoot(errorcode); + #endif + return false; + } + else { + uint32_t address = currentAddress; + /*Serial.print("Current Address: "); + Serial.println(currentAddress);*/ + currentAddress+=size; + return address; + } +} +// Variant B +bool SPIFlash::getAddress(uint16_t size, uint16_t &page_number, uint8_t &offset) { + uint32_t address = getAddress(size); + offset = (address >> 0); + page_number = (address >> 8); + return true; +} + +//Function for returning the size of the string (only to be used for the getAddress() function) +uint16_t SPIFlash::sizeofStr(String &inputStr) { + uint16_t inStrLen = inputStr.length() + 1; + uint16_t size; + + //inputStr.toCharArray(inputChar, inStrLen); + + size=(sizeof(char)*inStrLen); + size+=sizeof(inStrLen); + + return size; +} + +// Reads a byte of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +uint8_t SPIFlash::readByte(uint32_t address, bool fastRead) { + uint8_t data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + data = _readNextByte(NO_CONTINUE); + _endProcess(); + return data; + } +} +// Variant B +uint8_t SPIFlash::readByte(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readByte(address, fastRead); +} + +// Reads a char of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +int8_t SPIFlash::readChar(uint32_t address, bool fastRead) { + int8_t data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + data = _readNextByte(NO_CONTINUE); + _endProcess(); + return data; + } +} +// Variant B +int8_t SPIFlash::readChar(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readChar(address, fastRead); +} + +// Reads an array of bytes starting from a specific location in a page.// Has two variants: +// A. Takes three arguments +// 1. address --> Any address from 0 to maxAddress +// 2. data_buffer --> The array of bytes to be read from the flash memory - starting at the address indicated +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes four arguments +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data_buffer --> The array of bytes to be read from the flash memory - starting at the offset on the page indicated +// 4. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +uint8_t SPIFlash::readByteArray(uint32_t address, uint8_t *data_buffer, uint16_t bufferSize, bool fastRead) { + if (!_prepRead(address)) { + + } + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t a = 0; a < bufferSize; a++) { + if (a == (bufferSize-1)) + data_buffer[a] = _readNextByte(NO_CONTINUE); + else + data_buffer[a] = _readNextByte(); + _addressCheck(address++); + } + _endProcess(); + } + return true; +} +// Variant B +uint8_t SPIFlash::readByteArray(uint16_t page_number, uint8_t offset, uint8_t *data_buffer, uint16_t bufferSize, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readByteArray(address, data_buffer, bufferSize, fastRead); +} + +// Reads an array of bytes starting from a specific location in a page.// Has two variants: +// A. Takes three arguments +// 1. address --> Any address from 0 to maxAddress +// 2. data_buffer --> The array of bytes to be read from the flash memory - starting at the address indicated +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes four arguments +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data_buffer --> The array of bytes to be read from the flash memory - starting at the offset on the page indicated +// 4. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +uint8_t SPIFlash::readCharArray(uint32_t address, char *data_buffer, uint16_t bufferSize, bool fastRead) { + if (_prepRead(address)) { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t a = 0; a < bufferSize; a++) { + _addressCheck(address+a); + if (a == (bufferSize-1)) + data_buffer[a] = _readNextByte(NO_CONTINUE); + else + data_buffer[a] = _readNextByte(); + } + _endProcess(); + return true; + } + else + return false; +} +// Variant B +uint8_t SPIFlash::readCharArray(uint16_t page_number, uint8_t offset, char *data_buffer, uint16_t bufferSize, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readCharArray(address, data_buffer, bufferSize, fastRead); +} + +// Reads an unsigned int of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +uint16_t SPIFlash::readWord(uint32_t address, bool fastRead) { + union + { + byte b[sizeof(uint16_t)]; + uint16_t I; + } data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t i=0; i < (sizeof(int16_t)); i++) { + if (i == (sizeof(uint16_t)-1)) + data.b[i] = _readNextByte(NO_CONTINUE); + else + data.b[i] = _readNextByte(); + } + _endProcess(); + return data.I; + } +} +// Variant B +uint16_t SPIFlash::readWord(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readWord(address, fastRead); +} + +// Reads a signed int of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +int16_t SPIFlash::readShort(uint32_t address, bool fastRead) { + union + { + byte b[sizeof(int16_t)]; + int16_t s; + } data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t i=0; i < (sizeof(int16_t)); i++) { + if (i == (sizeof(int16_t)-1)) + data.b[i] = _readNextByte(NO_CONTINUE); + else + data.b[i] = _readNextByte(); + } + _endProcess(); + return data.s; + } +} +// Variant B +int16_t SPIFlash::readShort(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readShort(address, fastRead); +} + +// Reads an unsigned long of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +uint32_t SPIFlash::readULong(uint32_t address, bool fastRead) { + union + { + byte b[sizeof(uint32_t)]; + uint32_t l; + } data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t i=0; i < (sizeof(uint32_t)); i++) { + if (i == (sizeof(uint32_t)-1)) + data.b[i] = _readNextByte(NO_CONTINUE); + else + data.b[i] = _readNextByte(); + } + _endProcess(); + return data.l; + } +} +// Variant B +uint32_t SPIFlash::readULong(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readULong(address, fastRead); +} + +// Reads a signed long of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +int32_t SPIFlash::readLong(uint32_t address, bool fastRead) { + union + { + byte b[sizeof(int32_t)]; + int32_t l; + } data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t i=0; i < (sizeof(int32_t)); i++) { + if (i == (sizeof(int32_t)-1)) + data.b[i] = _readNextByte(NO_CONTINUE); + else + data.b[i] = _readNextByte(); + } + _endProcess(); + return data.l; + } +} +// Variant B +int32_t SPIFlash::readLong(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readLong(address, fastRead); +} + +// Reads a signed long of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +float SPIFlash::readFloat(uint32_t address, bool fastRead) { + union + { + byte b[(sizeof(float))]; + float f; + } data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t i=0; i < (sizeof(float)); i++) { + if (i == (sizeof(float)-1)) + data.b[i] = _readNextByte(NO_CONTINUE); + else + data.b[i] = _readNextByte(); + } + _endProcess(); + return data.f; + } +} +// Variant B +float SPIFlash::readFloat(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readFloat(address, fastRead); +} + +// Reads a string from a specific location on a page. +// Has two variants: +// A. Takes three arguments +// 1. address --> Any address from 0 to maxAddress +// 2. outputString --> String variable to write the output to +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes four arguments +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. outputString --> String variable to write the output to +// 4. fastRead --> defaults to false - executes _beginFastRead() if set to true +// This function first reads a short from the address to figure out the size of the String object stored and +// then reads the String object data +// Variant A +bool SPIFlash::readStr(uint32_t address, String &outStr, bool fastRead) { + if (!_prepRead(address)) + return false; + uint16_t strLen; + + strLen = readShort(address); + address+=(sizeof(strLen)); + + char outputChar[strLen]; + + readCharArray(address, outputChar, strLen, fastRead); + + outStr = String(outputChar); + return true; +} +// Variant B +bool SPIFlash::readStr(uint16_t page_number, uint8_t offset, String &outStr, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + return readStr(address, outStr, fastRead); +} + +// Reads a page of data into a page buffer. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. data_buffer --> a data buffer to read the data into (This HAS to be an array of 256 bytes) +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +bool SPIFlash::readPage(uint16_t page_number, uint8_t *data_buffer, bool fastRead) { + uint32_t address = _prepRead(page_number); + + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (int a = 0; a < 256; ++a) { + if (a == (255)) + data_buffer[a] = _readNextByte(NO_CONTINUE); + else + data_buffer[a] = _readNextByte(); + } + _endProcess(); + return true; +} + +// Writes a byte of data to a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One byte of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One byte of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeByte(uint32_t address, uint8_t data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + _beginWrite(address); + _writeNextByte(data, NO_CONTINUE); + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeByte(uint16_t page_number, uint8_t offset, uint8_t data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeByte(address, data, errorCheck); +} + +// Writes a char of data to a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One char of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One char of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeChar(uint32_t address, int8_t data, bool errorCheck) { + if (!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + _beginWrite(address); + _writeNextByte(data, NO_CONTINUE); + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); + +} +// Variant B +bool SPIFlash::writeChar(uint16_t page_number, uint8_t offset, int8_t data, bool errorCheck) { + uint32_t address = _prepWrite(page_number, offset); + + return writeChar(address, data, errorCheck); + +} + +// Writes an array of bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> An array of bytes to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> An array of bytes to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeByteArray(uint32_t address, uint8_t *data_buffer, uint16_t bufferSize, bool errorCheck) { + if (!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data_buffer))) + return false; + #endif + + _beginWrite(address); + + for (int i = 0; i < bufferSize; i++) { + _addressCheck(address+i); + if (i == (bufferSize-1)) + _writeNextByte(data_buffer[i], NO_CONTINUE); + else + _writeNextByte(data_buffer[i]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data_buffer); +} +// Variant B +bool SPIFlash::writeByteArray(uint16_t page_number, uint8_t offset, uint8_t *data_buffer, uint16_t bufferSize, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeByteArray(address, data_buffer, bufferSize, errorCheck); +} + +// Writes an array of bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> An array of chars to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> An array of chars to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeCharArray(uint32_t address, char *data_buffer, uint16_t bufferSize, bool errorCheck) { + if (!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data_buffer))) + return false; + #endif + + _beginWrite(address); + + for (int i = 0; i < bufferSize; i++) { + _addressCheck(address+i); + if (i == (bufferSize-1)) + _writeNextByte(data_buffer[i], NO_CONTINUE); + else + _writeNextByte(data_buffer[i]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data_buffer); +} +// Variant B +bool SPIFlash::writeCharArray(uint16_t page_number, uint8_t offset, char *data_buffer, uint16_t bufferSize, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeCharArray(address, data_buffer, bufferSize, errorCheck); +} + +// Writes an unsigned int as two bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One unsigned int of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One unsigned int of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeWord(uint32_t address, uint16_t data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + union + { + uint8_t b[sizeof(data)]; + uint16_t w; + } var; + var.w = data; + + _beginWrite(address); + for (uint16_t j = 0; j < sizeof(data); j++) { + if (j == (sizeof(data)-1)) + _writeNextByte(var.b[j], NO_CONTINUE); + else + _writeNextByte(var.b[j]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeWord(uint16_t page_number, uint8_t offset, uint16_t data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeWord(address, data, errorCheck); +} + +// Writes a signed int as two bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One signed int of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One signed int of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeShort(uint32_t address, int16_t data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + union + { + uint8_t b[sizeof(data)]; + int16_t s; + } var; + var.s = data; + _beginWrite(address); + for (uint16_t j = 0; j < (sizeof(data)); j++) { + if (j == (sizeof(data)-1)) + _writeNextByte(var.b[j], NO_CONTINUE); + else + _writeNextByte(var.b[j]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeShort(uint16_t page_number, uint8_t offset, int16_t data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeShort(address, data, errorCheck); +} + +// Writes an unsigned long as four bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One unsigned long of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One unsigned long of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeULong(uint32_t address, uint32_t data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + union + { + uint8_t b[sizeof(data)]; + uint32_t l; + } var; + var.l = data; + _beginWrite(address); + for (uint16_t j = 0; j < (sizeof(data)); j++) { + if (j == (sizeof(data)-1)) + _writeNextByte(var.b[j], NO_CONTINUE); + else + _writeNextByte(var.b[j]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeULong(uint16_t page_number, uint8_t offset, uint32_t data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeULong(address, data, errorCheck); +} + +// Writes a signed long as four bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One signed long of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One signed long of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeLong(uint32_t address, int32_t data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + union + { + uint8_t b[sizeof(data)]; + int32_t l; + } var; + var.l = data; + _beginWrite(address); + for (uint16_t j = 0; j < (sizeof(data)); j++) { + if (j == (sizeof(data)-1)) + _writeNextByte(var.b[j], NO_CONTINUE); + else + _writeNextByte(var.b[j]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeLong(uint16_t page_number, uint8_t offset, int32_t data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeLong(address, data, errorCheck); +} + +// Writes a float as four bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One float of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One float of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeFloat(uint32_t address, float data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + union + { + uint8_t b[sizeof(data)]; + float f; + } var; + var.f = data; + _beginWrite(address); + for (uint16_t j = 0; j < (sizeof(data)); j++) { + if (j == (sizeof(data)-1)) + _writeNextByte(var.b[j], NO_CONTINUE); + else + _writeNextByte(var.b[j]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeFloat(uint16_t page_number, uint8_t offset, float data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeFloat(address, data, errorCheck); +} + +// Reads a string from a specific location on a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. inputString --> String variable to write the data from +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. inputString --> String variable to write the data from +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// This function first writes the size of the string as an unsigned int to the address to figure out the size of the String object stored and +// then writes the String object data. Therefore it takes up two bytes more than the size of the String itself. +// Variant A +bool SPIFlash::writeStr(uint32_t address, String &inputStr, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(inputStr))) + return false; + #endif + + uint16_t inStrLen = inputStr.length() + 1; + char inputChar[inStrLen]; + writeWord(address, inStrLen, errorCheck); + + address+=sizeof(inStrLen); + + inputStr.toCharArray(inputChar, inStrLen); + writeCharArray(address, inputChar, inStrLen, errorCheck); + return true; +} +// Variant B +bool SPIFlash::writeStr(uint16_t page_number, uint8_t offset, String &inputStr, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + return writeStr(address, inputStr, errorCheck); +} + +// Writes a page of data from a data_buffer array. Make sure the sizeOf(uint8_t data_buffer[]) == 256. +// errorCheck --> Turned on by default. Checks for writing errors. +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +bool SPIFlash::writePage(uint16_t page_number, uint8_t *data_buffer, bool errorCheck) { + uint32_t address = _prepWrite(page_number); + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data_buffer))) + return false; + #endif + + _beginWrite(address); + for (uint16_t i = 0; i < PAGESIZE; ++i){ + if (i == (PAGESIZE-1)) + _writeNextByte(data_buffer[i], NO_CONTINUE); + else + _writeNextByte(data_buffer[i]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, *data_buffer); +} + + +//Erases one 4k sector. Has two variants: +// A. Takes the address as the argument and erases the sector containing the address. +// B. Takes page to be erased as the argument and erases the sector containing the page. +// The sectors are numbered 0 - 255 containing 16 pages each. +// Page 0-15 --> Sector 0; Page 16-31 --> Sector 1;......Page 4080-4095 --> Sector 255 +// Variant A +bool SPIFlash::eraseSector(uint32_t address) { + if(!_notBusy()||!_writeEnable()) + return false; + + _cmd(SECTORERASE); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, 0x00); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(0); + CHIP_DESELECT + #endif + + if(!_notBusy(410L)) + return false; //Datasheet says erasing a sector takes 400ms max + + //_writeDisable(); //_writeDisable() is not required because the Write Enable Latch (WEL) flag is cleared to 0 + // i.e. to write disable state upon the following conditions: + // Power-up, Write Disable, Page Program, Quad Page Program, ``Sector Erase``, Block Erase, Chip Erase, Write Status Register, + // Erase Security Register and Program Security register + + return true; +} +// Variant B +bool SPIFlash::eraseSector(uint16_t page_number, uint8_t offset) { + uint32_t address = _getAddress(page_number, offset); + return eraseSector(address); +} + +//Erases one 32k block. Has two variants: +// A. Takes the address as the argument and erases the block containing the address. +// B. Takes page to be erased as the argument and erases the block containing the page. +// The blocks are numbered 0 - 31 containing 128 pages each. +// Page 0-127 --> Block 0; Page 128-255 --> Block 1;......Page 3968-4095 --> Block 31 +// Variant A +bool SPIFlash::eraseBlock32K(uint32_t address) { + if(!_notBusy()||!_writeEnable()) + return false; + + _cmd(BLOCK32ERASE); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, 0x00); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(0); + CHIP_DESELECT + #endif + + if(!_notBusy(410L)) + return false; //Datasheet says erasing a sector takes 400ms max + + //_writeDisable(); //_writeDisable() is not required because the Write Enable Latch (WEL) flag is cleared to 0 + // i.e. to write disable state upon the following conditions: + // Power-up, Write Disable, Page Program, Quad Page Program, Sector Erase, ``Block Erase``, Chip Erase, Write Status Register, + // Erase Security Register and Program Security register + + return true; +} +// Variant B +bool SPIFlash::eraseBlock32K(uint16_t page_number, uint8_t offset) { + uint32_t address = _getAddress(page_number, offset); + return eraseBlock32K(address); +} + +//Erases one 64k block. Has two variants: +// A. Takes the address as the argument and erases the block containing the address. +// B. Takes page to be erased as the argument and erases the block containing the page. +// The blocks are numbered 0 - 15 containing 256 pages each. +// Page 0-255 --> Block 0; Page 256-511 --> Block 1;......Page 3840-4095 --> Block 15 +// Variant A +bool SPIFlash::eraseBlock64K(uint32_t address) { + if(!_notBusy()||!_writeEnable()) + return false; + + _cmd(BLOCK64ERASE); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, 0x00); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(0); + CHIP_DESELECT + #endif + + if(!_notBusy(410L)) + return false; //Datasheet says erasing a sector takes 400ms max + + //_writeDisable(); //_writeDisable() is not required because the Write Enable Latch (WEL) flag is cleared to 0 + // i.e. to write disable state upon the following conditions: + // Power-up, Write Disable, Page Program, Quad Page Program, Sector Erase, ``Block Erase``, Chip Erase, Write Status Register, + // Erase Security Register and Program Security register + + return true; +} +// Variant B +bool SPIFlash::eraseBlock64K(uint16_t page_number, uint8_t offset) { + uint32_t address = _getAddress(page_number, offset); + return eraseBlock64K(address); +} + +//Erases whole chip. Think twice before using. +bool SPIFlash::eraseChip(void) { + if(!_notBusy()||!_writeEnable()) + return false; + + _cmd(CHIPERASE, NO_CONTINUE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + + if(!_notBusy(7000L)) + return false; //Datasheet says erasing chip takes 6s max + + //_writeDisable(); //_writeDisable() is not required because the Write Enable Latch (WEL) flag is cleared to 0 + // i.e. to write disable state upon the following conditions: + // Power-up, Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, ``Chip Erase``, Write Status Register, + // Erase Security Register and Program Security register + + return true; + +} + +//Suspends current Block Erase/Sector Erase/Page Program. Does not suspend chipErase(). +//Page Program, Write Status Register, Erase instructions are not allowed. +//Erase suspend is only allowed during Block/Sector erase. +//Program suspend is only allowed during Page/Quad Page Program +bool SPIFlash::suspendProg(void) { + if(_notBusy() || !_noSuspend()) + return false; + + _cmd(SUSPEND, NO_CONTINUE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + + _delay_us(20); + + if(!_notBusy() || _noSuspend()) //Max suspend Enable time according to datasheet + return false; + return true; +} + +//Resumes previously suspended Block Erase/Sector Erase/Page Program. +bool SPIFlash::resumeProg(void) { + if(!_notBusy() || _noSuspend()) + return false; + + _cmd(RESUME, NO_CONTINUE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + + _delay_us(20); + + if(_notBusy() || !_noSuspend()) + return false; + return true; + +} + +//Puts device in low power state. Good for battery powered operations. +//Typical current consumption during power-down is 1mA with a maximum of 5mA. (Datasheet 7.4) +//In powerDown() the chip will only respond to powerUp() +bool SPIFlash::powerDown(void) { + if(!_notBusy()) + return false; + + _cmd(POWERDOWN, NO_CONTINUE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + _delay_us(3); //Max powerDown enable time according to the Datasheet + + uint8_t status1 = _readStat1(); + uint8_t status2 = _readStat1(); + status1 = _readStat1(); + + if (status1 != 255 && status2 != 255) { + if (status1 == status2 || status1 == 0 || status2 == 0) { + status1 = _readStat1(); + status2 = _readStat1(); + } + else if (status1 != status2) + return true; + } + else if (status1 == 255 && status2 == 255) + return true; + else if (status1 == 0 && status2 == 0) + return false; + return true; +} + +//Wakes chip from low power state. +bool SPIFlash::powerUp(void) { + + _cmd(RELEASE, NO_CONTINUE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + _delay_us(3); //Max release enable time according to the Datasheet + + if (_readStat1() == 255) + return false; + return true; +} + +/************************************************************************************************************************ + These functions are deprecated to enable compatibility with various AVR chips. They can be used by uncommenting + this block of code. However, be warned, this particular block of code has only been tested with the Arduino + IDE (1.6.5) and only with 8-bit AVR based Arduino boards and is not supported from library version 2.0 onward + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + // These functions work with data to/from Serial stream. // + // Declares Serial.begin() if not previously declared. // + // Initiates Serial at 115200 baud. // + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + + + This function is deprecated to enable compatibility with various AVR chips. It can be used by uncommenting + this block of code. However, be warned, this particular block of code has only been tested with the Arduino + IDE and only with 8-bit AVR based Arduino boards. + +//Prints hex/dec formatted data from page reads - for debugging +void SPIFlash::_printPageBytes(uint8_t *data_buffer, uint8_t outputType) { + char buffer[10]; + for (int a = 0; a < 16; ++a) { + for (int b = 0; b < 16; ++b) { + if (outputType == 1) { + sprintf(buffer, "%02x", data_buffer[a * 16 + b]); + Serial.print(buffer); + } + else if (outputType == 2) { + uint8_t x = data_buffer[a * 16 + b]; + if (x < 10) Serial.print("0"); + if (x < 100) Serial.print("0"); + Serial.print(x); + Serial.print(','); + } + } + Serial.println(); + } +} + +//Reads a string from Serial +bool SPIFlash::readSerialStr(String &inputStr) { + if(!Serial) + Serial.begin(115200); + while (Serial.available()) { + inputStr = Serial.readStringUntil('\n'); + return true; + } + return false; +} + +//Reads a page of data and prints it to Serial stream. Make sure the sizeOf(uint8_t data_buffer[]) == 256. +void SPIFlash::printPage(uint16_t page_number, uint8_t outputType, bool fastRead) { + if(!Serial) + Serial.begin(115200); + + char buffer[24]; + sprintf(buffer, "Reading page (%04x)", page_number); + Serial.println(buffer); + + uint8_t data_buffer[256]; + readPage(page_number, data_buffer, fastRead); + _printPageBytes(data_buffer, outputType); +} + +//Reads all pages on Flash chip and dumps it to Serial stream. +//This function is useful when extracting data from a flash chip onto a computer as a text file. +void SPIFlash::printAllPages(uint8_t outputType, bool fastRead) { + if(!Serial) + Serial.begin(115200); + + Serial.println("Reading all pages"); + uint8_t data_buffer[256]; + + for (int a = 0; a < maxPage; a++) { + readPage(a, data_buffer, fastRead); + _printPageBytes(data_buffer, outputType); + } +} +************************************************************************************************************************/ \ No newline at end of file diff --git a/tools/olimexino-32u4 firmware/iceprog/SPIFlash.h b/tools/olimexino-32u4 firmware/iceprog/SPIFlash.h new file mode 100644 index 0000000..a7ae99c --- /dev/null +++ b/tools/olimexino-32u4 firmware/iceprog/SPIFlash.h @@ -0,0 +1,267 @@ +/* Arduino SPIFlash Library v.2.2.0 + * Copyright (C) 2015 by Prajwal Bhattaram + * Modified by Prajwal Bhattaram - 24/11/2015 + * + * This file is part of the Arduino SPIFlash Library. This library is for + * Winbond NOR flash memory modules. In its current form it enables reading + * and writing individual data variables, structs and arrays from and to various locations; + * reading and writing pages; continuous read functions; sector, block and chip erase; + * suspending and resuming programming/erase and powering down for low power operation. + * + * This Library is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This Library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License v3.0 + * along with the Arduino SPIFlash Library. If not, see + * . + */ + +#ifndef SPIFLASH_H +#define SPIFLASH_H + +#include + +class SPIFlash { +public: + //----------------------------------------------Constructor-----------------------------------------------// + SPIFlash(uint8_t cs = 10, bool overflow = true); + //----------------------------------------Initial / Chip Functions----------------------------------------// + void begin(); + uint16_t getManID(); + uint32_t getJEDECID(); + bool getAddress(uint16_t size, uint16_t &page_number, uint8_t &offset); + uint32_t getAddress(uint16_t size); + uint16_t getChipName(); + uint16_t sizeofStr(String &inputStr); + uint32_t getCapacity(); + uint32_t getMaxPage(); + //-------------------------------------------Write / Read Bytes-------------------------------------------// + bool writeByte(uint32_t address, uint8_t data, bool errorCheck = true); + bool writeByte(uint16_t page_number, uint8_t offset, uint8_t data, bool errorCheck = true); + uint8_t readByte(uint16_t page_number, uint8_t offset, bool fastRead = false); + uint8_t readByte(uint32_t address, bool fastRead = false); + //----------------------------------------Write / Read Byte Arrays----------------------------------------// + bool writeByteArray(uint32_t address, uint8_t *data_buffer, uint16_t bufferSize, bool errorCheck = true); + bool writeByteArray(uint16_t page_number, uint8_t offset, uint8_t *data_buffer, uint16_t bufferSize, bool errorCheck = true); + uint8_t readByteArray(uint32_t address, uint8_t *data_buffer, uint16_t bufferSize, bool fastRead = false); + uint8_t readByteArray(uint16_t page_number, uint8_t offset, uint8_t *data_buffer, uint16_t bufferSize, bool fastRead = false); + //-------------------------------------------Write / Read Chars-------------------------------------------// + bool writeChar(uint32_t address, int8_t data, bool errorCheck = true); + bool writeChar(uint16_t page_number, uint8_t offset, int8_t data, bool errorCheck = true); + int8_t readChar(uint32_t address, bool fastRead = false); + int8_t readChar(uint16_t page_number, uint8_t offset, bool fastRead = false); + //----------------------------------------Write / Read Char Arrays----------------------------------------// + bool writeCharArray(uint32_t address, char *data_buffer, uint16_t bufferSize, bool errorCheck = true); + bool writeCharArray(uint16_t page_number, uint8_t offset, char *data_buffer, uint16_t bufferSize, bool errorCheck = true); + uint8_t readCharArray(uint32_t address, char *data_buffer, uint16_t buffer_size, bool fastRead = false); + uint8_t readCharArray(uint16_t page_number, uint8_t offset, char *data_buffer, uint16_t buffer_size, bool fastRead = false); + //------------------------------------------Write / Read Shorts------------------------------------------// + bool writeShort(uint32_t address, int16_t data, bool errorCheck = true); + bool writeShort(uint16_t page_number, uint8_t offset, int16_t data, bool errorCheck = true); + int16_t readShort(uint32_t address, bool fastRead = false); + int16_t readShort(uint16_t page_number, uint8_t offset, bool fastRead = false); + //-------------------------------------------Write / Read Words-------------------------------------------// + bool writeWord(uint32_t address, uint16_t data, bool errorCheck = true); + bool writeWord(uint16_t page_number, uint8_t offset, uint16_t data, bool errorCheck = true); + uint16_t readWord(uint32_t address, bool fastRead = false); + uint16_t readWord(uint16_t page_number, uint8_t offset, bool fastRead = false); + //-------------------------------------------Write / Read Longs-------------------------------------------// + bool writeLong(uint32_t address, int32_t data, bool errorCheck = true); + bool writeLong(uint16_t page_number, uint8_t offset, int32_t data, bool errorCheck = true); + int32_t readLong(uint32_t address, bool fastRead = false); + int32_t readLong(uint16_t page_number, uint8_t offset, bool fastRead = false); + //--------------------------------------Write / Read Unsigned Longs---------------------------------------// + bool writeULong(uint32_t address, uint32_t data, bool errorCheck = true); + bool writeULong(uint16_t page_number, uint8_t offset, uint32_t data, bool errorCheck = true); + uint32_t readULong(uint32_t address, bool fastRead = false); + uint32_t readULong(uint16_t page_number, uint8_t offset, bool fastRead = false); + //-------------------------------------------Write / Read Floats------------------------------------------// + bool writeFloat(uint32_t address, float data, bool errorCheck = true); + bool writeFloat(uint16_t page_number, uint8_t offset, float data, bool errorCheck = true); + float readFloat(uint32_t address, bool fastRead = false); + float readFloat(uint16_t page_number, uint8_t offset, bool fastRead = false); + //------------------------------------------Write / Read Strings------------------------------------------// + bool writeStr(uint32_t address, String &inputStr, bool errorCheck = true); + bool writeStr(uint16_t page_number, uint8_t offset, String &inputStr, bool errorCheck = true); + bool readStr(uint32_t address, String &outStr, bool fastRead = false); + bool readStr(uint16_t page_number, uint8_t offset, String &outStr, bool fastRead = false); + //-------------------------------------------Write / Read Pages-------------------------------------------// + bool writePage(uint16_t page_number, uint8_t *data_buffer, bool errorCheck = true); + bool readPage(uint16_t page_number, uint8_t *data_buffer, bool fastRead = false); + //------------------------------------------Write / Read Anything-----------------------------------------// + template bool writeAnything(uint32_t address, const T& value, bool errorCheck = true); + template bool writeAnything(uint16_t page_number, uint8_t offset, const T& value, bool errorCheck = true); + template bool readAnything(uint32_t address, T& value, bool fastRead = false); + template bool readAnything(uint16_t page_number, uint8_t offset, T& value, bool fastRead = false); + //--------------------------------------------Erase functions---------------------------------------------// + bool eraseSector(uint32_t address); + bool eraseSector(uint16_t page_number, uint8_t offset); + bool eraseBlock32K(uint32_t address); + bool eraseBlock32K(uint16_t page_number, uint8_t offset); + bool eraseBlock64K(uint32_t address); + bool eraseBlock64K(uint16_t page_number, uint8_t offset); + bool eraseChip(void); + //---------------------------------------------Power functions--------------------------------------------// + bool suspendProg(void); + bool resumeProg(void); + bool powerDown(void); + bool powerUp(void); + //--------------------------------------------Private functions-------------------------------------------// +private: + void _troubleshoot(uint8_t error); + void _cmd(uint8_t cmd, bool _continue = true, uint8_t cs = 0); + void _endProcess(void); + void _errorCodeCheck(void); + void _beginRead(uint32_t address); + void _beginFastRead(uint32_t address); + bool _noSuspend(void); + bool _notBusy(uint32_t timeout = 10L); + bool _notPrevWritten(uint32_t address, uint8_t size = 1); + bool _addressCheck(uint32_t address); + bool _beginWrite(uint32_t address); + bool _writeNextByte(uint8_t c, bool _continue = true); + bool _writeEnable(void); + bool _writeDisable(void); + bool _getJedecId(uint8_t *b1, uint8_t *b2, uint8_t *b3); + bool _getManId(uint8_t *b1, uint8_t *b2); + bool _chipID(void); + uint8_t _readStat1(void); + uint8_t _readNextByte(bool _continue = true); + uint32_t _getAddress(uint16_t page_number, uint8_t offset = 0); + uint32_t _prepRead(uint32_t address); + uint32_t _prepRead(uint16_t page_number, uint8_t offset = 0); + uint32_t _prepWrite(uint32_t address); + uint32_t _prepWrite(uint16_t page_number, uint8_t offset = 0); + template bool _writeErrorCheck(uint32_t address, const T& value); + //-------------------------------------------Private variables------------------------------------------// + bool pageOverflow; + volatile uint8_t *cs_port; + uint8_t cs_mask, csPin, errorcode; + uint16_t name; + uint32_t capacity, maxPage; + uint32_t currentAddress = 1; + const uint8_t devType[10] = {0x5, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17}; + const uint32_t memSize[10] = {64L * 1024L, 128L * 1024L, 256L * 1024L, 512L * 1024L, 1L * 1024L * 1024L, + 2L * 1024L * 1024L, 4L * 1024L * 1024L, 8L * 1024L * 1024L, 16L * 1024L * 1024L}; + const uint16_t chipName[10] = {05, 10, 20, 40, 80, 16, 32, 64, 128, 256}; +}; + + + //--------------------------------------------Templates-------------------------------------------// + +// Writes any type of data to a specific location in the flash memory. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. T& value --> Variable to return data into +// 4. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. const T& value --> Variable with the data to be written +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +template bool SPIFlash::writeAnything(uint32_t address, const T& value, bool errorCheck) { + if (!_prepWrite(address)) + return false; + else { + const byte* p = (const byte*)(const void*)&value; + _beginWrite(address); + for (uint16_t i = 0; i < sizeof(value); i++) { + #if defined (__arm__) && defined (__SAM3X8E__) + if (i == sizeof(value)-1) + _writeNextByte(*p++, false); + #endif + _writeNextByte(*p++); + } + _endProcess(); + } + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, value); +} +// Variant B +template bool SPIFlash::writeAnything(uint16_t page_number, uint8_t offset, const T& value, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + return writeAnything(address, value, errorCheck); +} + +// Reads any type of data from a specific location in the flash memory. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. T& value --> Variable to return data into +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. T& value --> Variable to return data into +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +template bool SPIFlash::readAnything(uint32_t address, T& value, bool fastRead) { + if (!_prepRead(address)) + return false; + + byte* p = (byte*)(void*)&value; + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + for (uint16_t i = 0; i < sizeof(value); i++) { + #if defined (__arm__) && defined (__SAM3X8E__) + if (i == sizeof(value)-1) + *p++ = _readNextByte(false); + #endif + *p++ =_readNextByte(); + } + _endProcess(); + return true; +} +// Variant B +template bool SPIFlash::readAnything(uint16_t page_number, uint8_t offset, T& value, bool fastRead) +{ + uint32_t address = _getAddress(page_number, offset); + return readAnything(address, value, fastRead); +} + +// Private template to check for errors in writing to flash memory +template bool SPIFlash::_writeErrorCheck(uint32_t address, const T& value) { +if (!_prepRead(address)) + return false; + + const byte* p = (const byte*)(const void*)&value; + _beginRead(address); + for(uint16_t i = 0; i < sizeof(value);i++) + { + #if defined (__arm__) && defined (__SAM3X8E__) + if (i == sizeof(value)-1) { + if (*p++ != _readNextByte(false)) + return false; + else + return true; + } + else + if (*p++ != _readNextByte()) + return false; + #elif defined (__AVR__) + if (*p++ != _readNextByte()) + return false; + #endif + } + _endProcess(); + return true; +} + + +#endif // _SPIFLASH_H_ \ No newline at end of file diff --git a/tools/olimexino-32u4 firmware/iceprog/iceprog.ino b/tools/olimexino-32u4 firmware/iceprog/iceprog.ino new file mode 100644 index 0000000..81e4afe --- /dev/null +++ b/tools/olimexino-32u4 firmware/iceprog/iceprog.ino @@ -0,0 +1,403 @@ +/* + * iceprog -- firmware scetch for Arduino based Lattice iCE programmers + * + * Chris B. @ Olimex Ltd. 2017 + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Relevant Documents: + * ------------------- + * http://www.latticesemi.com/~/media/Documents/UserManuals/EI/icestickusermanual.pdf + * http://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_32mb_3v_65nm.pdf + * http://www.ftdichip.com/Support/Documents/AppNotes/AN_108_Command_Processor_for_MPSSE_and_MCU_Host_Bus_Emulation_Modes.pdf + * https://www.olimex.com/Products/FPGA/iCE40/iCE40HX1K-EVB/ + * https://github.com/Marzogh/SPIFlash + */ + +#include + +// The demo uses SPIFlash v2.2.0, its files are included in the project folders the author is Prajwal Bhattaram - Marzogh + +#include "SPIFlash.h" + +#define LED 17 +#define CDONE 3 +#define RESET 2 +#define UEXT_POWER 8 +#define CS 13 + +//commands list +#define READ_ID 0x9F +#define PWR_UP 0xAB +#define PWR_DOWN 0xB9 +#define WR_EN 0x06 +#define BULK_ERASE 0xC7 +#define SEC_ERASE 0xd8 +#define PROG 0x02 +#define READ 0x03 +#define READ_ALL 0x83 +#define CMD_ERROR 0xee +#define READY 0x44 +#define EMPTY 0x45 + +#define FEND 0xc0 +#define FESC 0xdb +#define TFEND 0xdc +#define TFESC 0xdd + +#define cselect digitalWrite(CS,LOW) +#define deselect digitalWrite(CS,HIGH) + +//Toggle iceprogduino with serial bridge by pressing the HWB button +#define HWB (PINE & B00000100)==0 // Check if the button has been pressed +#define HWB_INPUT DDRE &= B11111011 // Initialize the port +#define LED_G 7 // The GREEN LED is on Pin 7 +#define LED_Y 9 // The YELLOW LED is on Pin 9 +boolean isProg; + +uint8_t rxframe[512], txframe[512], fcs,rfcs; +uint8_t membuf[256]; +uint8_t data_buffer[256]; +uint16_t txp; +uint32_t maxPage; +bool escaped; +SPIFlash flash(CS); + +void secerase(uint32_t sector); +void decodeFrame(void); +void writepage(int pagenr); +bool readSerialFrame(void); +void flash_bulk_erase(void); +void SendID(void); +void sendframe(); +void startframe(uint8_t command); +void addbyte(uint8_t newbyte); +void readAllPages(void); +void readpage(uint16_t adr); + +// FRAME: {data if any} +// if FEND, FESC in data - =; = + +void setup() { + // put your setup code here, to run once: + // Power Up UEXT + pinMode(CDONE,INPUT); + pinMode(RESET,OUTPUT); + pinMode(LED,OUTPUT); + digitalWrite(LED,0); + pinMode(CS,OUTPUT); + digitalWrite(CS,HIGH); + pinMode(UEXT_POWER, OUTPUT); + digitalWrite(UEXT_POWER, HIGH); + delay(1000); + digitalWrite(UEXT_POWER, LOW); + delay(500); + digitalWrite(RESET, HIGH); + Serial.begin(230400); + while (!Serial); + + isProg=true; + HWB_INPUT; // Initialize HWB + Serial1.begin(115200); + pinMode(LED_Y,OUTPUT); + digitalWrite(LED_Y,isProg); //Yellow LED is Prog + pinMode(LED_G,OUTPUT); + digitalWrite(LED_G,!isProg); //Green LED is Bridge + +} + +void loop(){ + if (isProg) loopProg(); + else loopBridge(); + if (HWB) { + isProg = !isProg; + digitalWrite(LED_Y,isProg); + digitalWrite(LED_G,!isProg); + delay(1000); + } +} + +void loopBridge(){ + // read from port 1, send to port 0: + if (Serial1.available()) { + int inByte = Serial1.read(); + Serial.write(inByte); + } + + // read from port 0, send to port 1: + if (Serial.available()) { + int inByte = Serial.read(); + Serial1.write(inByte); + } +} + +void loopProg() { + + if (readSerialFrame()) + { + decodeFrame(); + if (rfcs==0xff) + { + digitalWrite(RESET, LOW); + + switch (rxframe[0]){ + + case FEND: + break; + + case READ_ID: + SendID(); + break; + + case BULK_ERASE: + flash_bulk_erase(); + break; + + case SEC_ERASE: + flash.powerUp(); + secerase((rxframe[1]<<8) | rxframe[2]); + flash.powerDown(); + + break; + + case READ: + flash.powerUp(); + readpage((rxframe[1]<<8) | rxframe[2]); + flash.powerDown(); + break; + + case READ_ALL: + readAllPages(); + break; + + case PROG: + writepage((rxframe[1]<<8) | rxframe[2]); + break; + + default: + break; + + + }//switch + digitalWrite(RESET, HIGH); + + } + + } +} + + +void secerase(uint32_t sector){ + flash.eraseBlock64K(sector<<8); + startframe(READY); + sendframe(); + +} +void decodeFrame(void){ + int x,y; + escaped = false; + y = 1; + rfcs = rxframe[1]; + rxframe[0]=rxframe[1]; + for (x=2;x<512;x++) + { + switch (rxframe[x]){ + + case FEND: + x = 513; + break; + + case FESC: + escaped = true; + break; + + case TFEND: + if (escaped) + { + rxframe[y++] = FEND; + rfcs+=FEND; + escaped = false; + } + else + { + rxframe[y++]=TFEND; + rfcs+=TFEND; + } + + break; + + case TFESC: + if (escaped) + { + rxframe[y++]=FESC; + rfcs+=FESC; + escaped = false; + } + else + { + rxframe[y++]=TFESC; + rfcs+=TFESC; + } + + break; + + default: + escaped = false; + rxframe[y++] = rxframe[x]; + rfcs+=rxframe[x]; + break; + } + + } + +} + +void writepage(int pagenr){ +int x; +flash.powerUp(); + +for (x=0; x<256;x++) + membuf[x]=rxframe[x+3]; + +flash.writePage(pagenr,membuf); +flash.readPage(pagenr,data_buffer); +flash.powerDown(); + + for (int a = 0; a < 256; a++) + if (data_buffer[a] != membuf[a]) + return; + + startframe(READY); + sendframe(); + + +} + + + +//Reads a frame from Serial +bool readSerialFrame(void) +{ + Serial.setTimeout(50); + + if (!Serial) + Serial.begin(230400); + // Serial.begin(1000000); + while (Serial.available()) { + Serial.readBytesUntil(FEND,rxframe,512); + //if (rxframe[0]!=FEND) + return true; + } + return false; +} +void flash_bulk_erase(void) +{ + flash.powerUp(); + flash.eraseChip(); + flash.powerDown(); + startframe(READY); + addbyte(BULK_ERASE); + sendframe(); +} + +void SendID(void) +{ + + flash.powerUp(); + uint32_t JEDEC = flash.getJEDECID(); + flash.powerDown(); + startframe(READ_ID); + addbyte(JEDEC >> 16); + addbyte(JEDEC >> 8); + addbyte(JEDEC >> 0); + sendframe(); + + +} + + +void sendframe(){ + fcs = 0xff - fcs; + addbyte(fcs); + txframe[txp++] = FEND; + Serial.write(txframe,txp); + +} + + +void startframe(uint8_t command){ + txframe[0]=FEND; + txframe[1]=command; + txp = 2; + fcs = command; +} +void addbyte(uint8_t newbyte) +{ +fcs+=newbyte; +if (newbyte == FEND) +{ + txframe[txp++] = FESC; + txframe[txp++] = TFEND; +} else + if (newbyte == FESC) + { + txframe[txp++] = FESC; + txframe[txp++] = TFESC; + } else + txframe[txp++] = newbyte; + +} + + +void readAllPages(void){ +flash.powerUp(); +maxPage=0x2000; +delay(10); +int p; +for (p=0;p> 8); + addbyte(adr >> 0); + for (int b = 0;b<256;b++) + addbyte(data_buffer[b]); + sendframe(); + sendempty=false; + break; + + } + + } + if (sendempty){ + startframe(EMPTY); + addbyte(adr >> 8); + addbyte(adr >> 0); + sendframe(); + } +} diff --git a/tools/olimexino-32u4 firmware/platformio.ini b/tools/olimexino-32u4 firmware/platformio.ini new file mode 100644 index 0000000..5134d58 --- /dev/null +++ b/tools/olimexino-32u4 firmware/platformio.ini @@ -0,0 +1,14 @@ +; PlatformIO Project Configuration File +; +; Please visit documentation for the other options and examples +; http://docs.platformio.org/page/projectconf.html + +[platformio] +env_default = leonardo + +[env:leonardo] +platform = atmelavr +framework = arduino +board = leonardo +board_build.mcu = atmega32u4 +board_build.f_cpu = 16000000L diff --git a/tools/olimexino-32u4 firmware/src/SPIFlash.cpp b/tools/olimexino-32u4 firmware/src/SPIFlash.cpp new file mode 100644 index 0000000..a866e9b --- /dev/null +++ b/tools/olimexino-32u4 firmware/src/SPIFlash.cpp @@ -0,0 +1,1961 @@ +/* Arduino SPIFlash Library v.2.2.0 + * Copyright (C) 2015 by Prajwal Bhattaram + * Modified by Prajwal Bhattaram - 24/11/2015 + * + * This file is part of the Arduino SPIFlash Library. This library is for + * Winbond NOR flash memory modules. In its current form it enables reading + * and writing individual data variables, structs and arrays from and to various locations; + * reading and writing pages; continuous read functions; sector, block and chip erase; + * suspending and resuming programming/erase and powering down for low power operation. + * + * This Library is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This Library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License v3.0 + * along with the Arduino SPIFlash Library. If not, see + * . + */ + +#include "SPIFlash.h" + +#if defined (__arm__) && defined (__SAM3X8E__) + #define _delay_us(us) delayMicroseconds(us) +#else + #include +#endif + +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +// Uncomment the code below to run a diagnostic if your flash // +// does not respond // +// // +// Error codes will be generated and returned on functions // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +//#define RUNDIAGNOSTIC // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +// Uncomment the code below to increase the speed of the library // +// by disabling _notPrevWritten() // +// // +// Make sure the sectors being written to have been erased beforehand // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +#if defined (__SAM3X8E__) +//#define HIGHSPEED +#elif defined (__AVR__) +//#define HIGHSPEED +#endif +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + +#define _MANID 0xEF +#define PAGESIZE 0x100 + +#define MANID 0x90 +#define PAGEPROG 0x02 +#define READDATA 0x03 +#define FASTREAD 0x0B +#define WRITEDISABLE 0x04 +#define READSTAT1 0x05 +#define READSTAT2 0x35 +#define WRITEENABLE 0x06 +#define SECTORERASE 0x20 +#define BLOCK32ERASE 0x52 +#define CHIPERASE 0x60 +#define SUSPEND 0x75 +#define ID 0x90 +#define RESUME 0x7A +#define JEDECID 0x9f +#define RELEASE 0xAB +#define POWERDOWN 0xB9 +#define BLOCK64ERASE 0xD8 + +#define BUSY 0x01 +#define WRTEN 0x02 +#define SUS 0x40 +#define DUMMYBYTE 0xEE + +#define arrayLen(x) (sizeof(x) / sizeof(*x)) +#define lengthOf(x) (sizeof(x))/sizeof(byte) +#define maxAddress capacity +#define NO_CONTINUE 0x00 +#define PASS 0x01 +#define FAIL 0x00 + +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +// List of Error codes // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + #ifdef RUNDIAGNOSTIC + + #define SUCCESS 0x00 + #define CALLBEGIN 0x01 + #define UNKNOWNCHIP 0x02 + #define UNKNOWNCAP 0x03 + #define CHIPBUSY 0x04 + #define OUTOFBOUNDS 0x05 + #define CANTENWRITE 0x06 + #define PREVWRITTEN 0x07 + #define UNKNOWNERROR 0xFF + + #endif + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + +#if defined (__arm__) && defined (__SAM3X8E__) + #include +#elif defined (__AVR__) + #ifdef __AVR_ATtiny85__ + #define CHIP_SELECT PORTB &= ~cs_mask; + #define CHIP_DESELECT PORTB |= cs_mask; + #define SPIBIT \ + USICR = ((1< + #define CHIP_SELECT *cs_port &= ~cs_mask; + #define CHIP_DESELECT *cs_port |= cs_mask; + #define xfer(n) SPI.transfer(n) + #endif +#endif + +// Constructor +#if defined (__arm__) && defined (__SAM3X8E__) +SPIFlash::SPIFlash(uint8_t cs, bool overflow) { + csPin = cs; + pageOverflow = overflow; +} +#elif defined (__AVR__) +SPIFlash::SPIFlash(uint8_t cs, bool overflow) { + csPin = cs; +#ifndef __AVR_ATtiny85__ + cs_port = portOutputRegister(digitalPinToPort(csPin)); +#endif + cs_mask = digitalPinToBitMask(csPin); + SPI.begin(); + SPI.setDataMode(0); + SPI.setBitOrder(MSBFIRST); + //SPI.setClockDivider(SPI_CLOCK_DIV2); + pageOverflow = overflow; + pinMode(cs, OUTPUT); +} +#endif + +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +// Private functions used by read, write and erase operations // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + +// Select chip and issue command - data to follow +void SPIFlash::_cmd(uint8_t cmd, bool _continue, uint8_t cs) { + cs = csPin; + #if defined (__arm__) && defined (__SAM3X8E__) + if (!_continue) + SPI.transfer(cs, cmd); + else + SPI.transfer(cs, cmd, SPI_CONTINUE); + #else + CHIP_SELECT + (void)xfer(cmd); + #endif +} + +// Checks if status register 1 can be accessed - used during powerdown and power up and for debugging +uint8_t SPIFlash::_readStat1(void) { + uint8_t stat1; + _cmd(READSTAT1); + #if defined (__SAM3X8E__) + stat1 = SPI.transfer(csPin, 0x00); + #else + stat1 = xfer(0); + CHIP_DESELECT + #endif + return stat1; +} + +// Checks the erase/program suspend flag before enabling/disabling a program/erase suspend operation +bool SPIFlash::_noSuspend(void) { + uint8_t state; + + _cmd(READSTAT2); + #if defined (__arm__) && defined (__SAM3X8E__) + state = SPI.transfer(csPin, 0x00); + #else + state = xfer(0); + CHIP_DESELECT + #endif + + if(state & SUS) + return false; + return true; +} + +// Polls the status register 1 until busy flag is cleared or timeout +bool SPIFlash::_notBusy(uint32_t timeout) { + uint8_t state; + uint32_t startTime = millis(); + + do { + _cmd(READSTAT1); + #if defined (__arm__) && defined (__SAM3X8E__) + state = SPI.transfer(csPin, 0x00); + #else + state = xfer(0); + CHIP_DESELECT + #endif + if((millis()-startTime) > timeout){ + #ifdef RUNDIAGNOSTIC + errorcode = CHIPBUSY; + _troubleshoot(errorcode); + #endif + return false; + } + } while(state & BUSY); + return true; +} + +//Enables writing to chip by setting the WRITEENABLE bit +bool SPIFlash::_writeEnable(void) { + uint8_t state; + + #if defined (__arm__) && (__SAM3X8E__) + SPI.transfer(csPin, WRITEENABLE); + #else + _cmd(WRITEENABLE); + CHIP_DESELECT + #endif + + //verifies that WRITE is enabled + #if defined (__arm__) && (__SAM3X8E__) + SPI.transfer(csPin, READSTAT1, SPI_CONTINUE); + state = SPI.transfer(csPin, 0x00); + #else + _cmd(READSTAT1); + state = xfer(0); + CHIP_DESELECT + #endif + if(state & WRTEN) + return true; + else { + #ifdef RUNDIAGNOSTIC + errorcode = CANTENWRITE; + _troubleshoot(errorcode); + #endif + + return false; + } +} + +//Disables writing to chip by setting the Write Enable Latch (WEL) bit in the Status Register to 0 +//_writeDisable() is not required under the following conditions because the Write Enable Latch (WEL) flag is cleared to 0 +// i.e. to write disable state: +// Power-up, Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, +// Erase Security Register and Program Security register +bool SPIFlash::_writeDisable(void) { + _cmd(WRITEDISABLE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + + return true; +} + +//Gets address from page number and offset. Takes two arguments: +// 1. page_number --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +uint32_t SPIFlash::_getAddress(uint16_t page_number, uint8_t offset) { + uint32_t address = page_number; + address = (address << 8) + offset; + + if (!_addressCheck(address)){ + #ifdef RUNDIAGNOSTIC + errorcode = OUTOFBOUNDS; + _troubleshoot(errorcode); + #endif + return false; + } + else + return address; +} + +//Checks the device ID to establish storage parameters +bool SPIFlash::_getManId(uint8_t *b1, uint8_t *b2) { + if(!_notBusy()) + return false; + _cmd(MANID); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, 0x00, SPI_CONTINUE); + SPI.transfer(csPin, 0x00, SPI_CONTINUE); + SPI.transfer(csPin, 0x00, SPI_CONTINUE); + *b1 = SPI.transfer(csPin, 0x00, SPI_CONTINUE); + *b2 = SPI.transfer(csPin, 0x00); + #else + xfer(0); + xfer(0); + xfer(0); + *b1 = xfer(0); + *b2 = xfer(0); + CHIP_DESELECT + #endif + return true; +} + +//Checks for presence of chip by requesting JEDEC ID +bool SPIFlash::_getJedecId(uint8_t *b1, uint8_t *b2, uint8_t *b3) { + if(!_notBusy()) + return false; + _cmd(JEDECID); + #if defined (__arm__) && defined (__SAM3X8E__) + *b1 = SPI.transfer(csPin, 0x00, SPI_CONTINUE); // manufacturer id + *b2 = SPI.transfer(csPin, 0x00, SPI_CONTINUE); // manufacturer id + *b3 = SPI.transfer(csPin, 0x00); // capacity + #else + *b1 = xfer(0); // manufacturer id + *b2 = xfer(0); // memory type + *b3 = xfer(0); // capacity + CHIP_DESELECT + #endif + return true; +} + +//Identifies the chip +bool SPIFlash::_chipID(void) { + //Get Manfucturer/Device ID so the library can identify the chip + uint8_t manID, devID ; + _getManId(&manID, &devID); + + if (manID != _MANID){ //If the chip is not a Winbond Chip + #ifdef RUNDIAGNOSTIC + errorcode = UNKNOWNCHIP; //Error code for unidentified chip + _troubleshoot(errorcode); + #endif + while(1); + } + + //Check flash memory type and identify capacity + uint8_t i; + //capacity & chip name + for (i = 0; i < sizeof(devType); i++) + { + if (devID == devType[i]) { + capacity = memSize[i]; + name = chipName[i]; + } + } + if (capacity == 0) { + #ifdef RUNDIAGNOSTIC + errorcode = UNKNOWNCAP; //Error code for unidentified capacity + _troubleshoot(errorcode); + #endif + while(1); + } + + maxPage = capacity/PAGESIZE; + + /*#ifdef RUNDIAGNOSTIC + char buffer[64]; + sprintf(buffer, "Manufacturer ID: %02xh\nMemory Type: %02xh\nCapacity: %lu\nmaxPage: %d", manID, devID, capacity, maxPage); + Serial.println(buffer); + #endif*/ + return true; +} + +//Checks to see if pageOverflow is permitted and assists with determining next address to read/write. +//Sets the global address variable +bool SPIFlash::_addressCheck(uint32_t address) { + #ifdef RUNDIAGNOSTIC + if (capacity == 0) { + errorcode = CALLBEGIN; + _troubleshoot(errorcode); + } + #endif + if (address >= capacity) { + if (!pageOverflow) { + #ifdef RUNDIAGNOSTIC + errorcode = OUTOFBOUNDS; + _troubleshoot(errorcode); + #endif + return false; // At end of memory - (!pageOverflow) + } + else { + address = 0x00; // At end of memory - (pageOverflow) + return true; + } + } + return true; // Not at end of memory if (address < capacity) +} + +//Double checks all parameters before calling a Read +//Has two variants: +// A. Takes address and returns the address if true, else returns false. Throws an error if there is a problem. +// B. Takes page_number and offset and returns address. Throws an error if there is a problem +// Variant A +uint32_t SPIFlash::_prepRead(uint32_t address) { + if(!_notBusy()) + return false; + if (!_addressCheck(address)) + return false; + else + return address; +} +// Variant B +uint32_t SPIFlash::_prepRead(uint16_t page_number, uint8_t offset) { + uint32_t address = _getAddress(page_number, offset); + return _prepRead(address); +} + +//Initiates read operation - but data is not read yet +void SPIFlash::_beginRead(uint32_t address) { + _cmd(READDATA); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, address, SPI_CONTINUE); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(address); + #endif + //SPI data lines are left open until _endProcess() is called +} + +//Initiates fast read operation (can operate at the highest possible freq of 104 MHz (at 3.0-3.6V) of 80 MHz (at 2.5-3.6V)) +//- but data is not read yet +void SPIFlash::_beginFastRead(uint32_t address) { + _cmd(FASTREAD); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, address, SPI_CONTINUE); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(address); + #endif + //SPI data lines are left open until _endProcess() is called +} + +//Reads next byte. Call 'n' times to read 'n' number of bytes. Should be called after _beginRead() +uint8_t SPIFlash::_readNextByte(bool _continue) { + uint8_t result; + #if defined (__arm__) && defined (__SAM3X8E__) + if (!_continue) + result = SPI.transfer(csPin, 0x00); + else + result = SPI.transfer(csPin, 0x00, SPI_CONTINUE); + #else + result = xfer(0x00); + #endif + return result; +} + +//Double checks all parameters before initiating a write +//Has two variants: +// A. Takes address and returns address if true or 'false' if false. Throws an error if there is a problem. +// B. Takes page_number and offset and returns address. Throws an error if there is a problem +// Variant A +uint32_t SPIFlash::_prepWrite(uint32_t address) { + if(!_notBusy()||!_writeEnable()) + return false; + if (!_addressCheck(address)) { + #ifdef RUNDIAGNOSTIC + errorcode = OUTOFBOUNDS; + _troubleshoot(errorcode); + #endif + return false; + } + else + return address; +} +// Variant B +uint32_t SPIFlash::_prepWrite(uint16_t page_number, uint8_t offset) { + uint32_t address = _getAddress(page_number, offset); + return _prepWrite(address); +} + +//Initiates write operation - but data is not written yet +bool SPIFlash::_beginWrite(uint32_t address) { + _cmd(PAGEPROG); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, address, SPI_CONTINUE); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(address); + #endif + //SPI data lines are left open until _endProcess() is called + return true; +} + +//Writes next byte. Call 'n' times to read 'n' number of bytes. Should be called after _beginWrite() +bool SPIFlash::_writeNextByte(uint8_t b, bool _continue) { + #if defined (__arm__) && defined (__SAM3X8E__) + if (!_continue) + SPI.transfer(csPin, b); + else + SPI.transfer(csPin, b, SPI_CONTINUE); + #else + xfer(b); + #endif + return true; +} + +//Stops all operations. Should be called after all the required data is read/written from repeated _readNextByte()/_writeNextByte() calls +void SPIFlash::_endProcess(void) { + #if defined (__arm__) && defined (__SAM3X8E__) + _delay_us(3); + #else + CHIP_DESELECT + #endif + _delay_us(3); +} + +#ifndef HIGHSPEED +bool SPIFlash::_notPrevWritten(uint32_t address, uint8_t size) { + uint32_t _size = size; + + /*uint8_t databyte1, databyte2, databyte3; + databyte1 = readByte(address, true); + databyte2 = readByte((address + (size/2)), true); + databyte3 = readByte((address+size), true); + if (databyte1 != 255 || databyte2 != 255 || databyte3 != 255) { + #ifdef RUNDIAGNOSTIC + errorcode = PREVWRITTEN; + _troubleshoot(errorcode); + #endif + return false; + } + _delay_us(3); + return true;*/ + uint32_t sampleSize; + if (_size <= 10) { + sampleSize = _size; + } + + if (_size > 10) { + do { + sampleSize++; + _size/=10; + } while((_size/10) >= 1); + } + + uint32_t addresses[sampleSize]; + + for (uint16_t i = 0; i < sampleSize; i++) { + addresses[i] = (rand() % size) + address; + } + + for (uint16_t i = 0; i < sampleSize; i++) { + uint8_t databyte = readByte(addresses[i]); + if (databyte != 0xFF) { + #ifdef RUNDIAGNOSTIC + errorcode = PREVWRITTEN; + _troubleshoot(errorcode); + #endif + return false; + } + } + return true; +} +#endif + +#ifdef RUNDIAGNOSTIC +//Troubleshooting function. Called when #ifdef RUNDIAGNOSTIC is uncommented at the top of this file. +void SPIFlash::_troubleshoot(uint8_t error) { + + switch (error) { + case SUCCESS: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(SUCCESS, HEX); + #else + Serial.println("Action completed successfully"); + #endif + break; + + case CALLBEGIN: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(CALLBEGIN, HEX); + #else + Serial.println("*constructor_of_choice*.begin() was not called in void setup()"); + #endif + break; + + case UNKNOWNCHIP: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(UNKNOWNCHIP, HEX); + #else + Serial.println("Unable to identify chip. Are you shure this is a Winbond Flash chip"); + Serial.println("Please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with your chip type and I will try to add support to your chip"); + #endif + + break; + + case UNKNOWNCAP: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(UNKNOWNCAP, HEX); + #else + Serial.println("Unable to identify capacity."); + Serial.println("Please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with your chip type and I will work on adding support to your chip"); + #endif + break; + + case CHIPBUSY: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(CHIPBUSY, HEX); + #else + Serial.println("Chip is busy."); + Serial.println("Make sure all pins have been connected properly"); + Serial.print("If it still doesn't work, "); + Serial.println("please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with the details of what your were doing when this error occured"); + #endif + break; + + case OUTOFBOUNDS: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(OUTOFBOUNDS, HEX); + #else + Serial.println("Page overflow has been disabled and the address called exceeds the memory"); + #endif + break; + + case CANTENWRITE: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(CANTENWRITE, HEX); + #else + Serial.println("Unable to Enable Writing to chip."); + Serial.println("Please make sure the HOLD & WRITEPROTECT pins are connected properly to VCC & GND respectively"); + Serial.print("If you are still facing issues, "); + Serial.println("please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with the details of what your were doing when this error occured"); + #endif + break; + + case PREVWRITTEN: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x0"); + Serial.println(PREVWRITTEN, HEX); + #else + Serial.println("This sector already contains data."); + Serial.println("Please make sure the sectors being written to are erased."); + Serial.print("If you are still facing issues, "); + Serial.println("please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with the details of what your were doing when this error occured"); + #endif + break; + + default: + #if defined (__AVR_ATmega328P__) || defined (__AVR_ATmega32U4__) || defined (__AVR_ATtiny85__) + Serial.print("Error code: 0x"); + Serial.println(UNKNOWNERROR, HEX); + #else + Serial.println("Unknown error"); + Serial.println("Please raise an issue at http://www.github.com/Marzogh/SPIFlash/issues with the details of what your were doing when this error occured"); + #endif + break; + } +} +#endif + + +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// +// Public functions used for read, write and erase operations // +//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + +//Identifies chip and establishes parameters +void SPIFlash::begin() { + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.begin(csPin); + SPI.setClockDivider(csPin, 21); + SPI.setDataMode(csPin, SPI_MODE0); + #endif + _chipID(); +} + +//Returns capacity of chip +uint32_t SPIFlash::getCapacity() { + return capacity; +} + +//Returns maximum number of pages +uint32_t SPIFlash::getMaxPage() { + return maxPage; +} + + +//Returns identifying name of the chip +uint16_t SPIFlash::getChipName() { + return name; +} + +//Checks for and initiates the chip by requesting JEDEC ID which is returned as a 32 bit int +uint16_t SPIFlash::getManID() { + uint8_t b1, b2; + _getManId(&b1, &b2); + uint32_t id = b1; + id = (id << 8)|(b2 << 0); + return id; +} + +//Checks for and initiates the chip by requesting JEDEC ID which is returned as a 32 bit int +uint32_t SPIFlash::getJEDECID() { + uint8_t b1, b2, b3; + _getJedecId(&b1, &b2, &b3); + uint32_t id = b1; + id = (id << 8)|(b2 << 0); + id = (id << 8)|(b3 << 0); + return id; +} + +//Gets the next available address for use. Has two variants: +// A. Takes the size of the data as an argument and returns a 32-bit address +// B. Takes a three variables, the size of the data and two other variables to return a page number value & an offset into. +// All addresses in the in the sketch must be obtained via this function or not at all. +// Variant A +uint32_t SPIFlash::getAddress(uint16_t size) { + if (!_addressCheck(currentAddress)){ + #ifdef RUNDIAGNOSTIC + errorcode = OUTOFBOUNDS; + _troubleshoot(errorcode); + #endif + return false; + } + else { + uint32_t address = currentAddress; + /*Serial.print("Current Address: "); + Serial.println(currentAddress);*/ + currentAddress+=size; + return address; + } +} +// Variant B +bool SPIFlash::getAddress(uint16_t size, uint16_t &page_number, uint8_t &offset) { + uint32_t address = getAddress(size); + offset = (address >> 0); + page_number = (address >> 8); + return true; +} + +//Function for returning the size of the string (only to be used for the getAddress() function) +uint16_t SPIFlash::sizeofStr(String &inputStr) { + uint16_t inStrLen = inputStr.length() + 1; + uint16_t size; + + //inputStr.toCharArray(inputChar, inStrLen); + + size=(sizeof(char)*inStrLen); + size+=sizeof(inStrLen); + + return size; +} + +// Reads a byte of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +uint8_t SPIFlash::readByte(uint32_t address, bool fastRead) { + uint8_t data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + data = _readNextByte(NO_CONTINUE); + _endProcess(); + return data; + } +} +// Variant B +uint8_t SPIFlash::readByte(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readByte(address, fastRead); +} + +// Reads a char of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +int8_t SPIFlash::readChar(uint32_t address, bool fastRead) { + int8_t data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + data = _readNextByte(NO_CONTINUE); + _endProcess(); + return data; + } +} +// Variant B +int8_t SPIFlash::readChar(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readChar(address, fastRead); +} + +// Reads an array of bytes starting from a specific location in a page.// Has two variants: +// A. Takes three arguments +// 1. address --> Any address from 0 to maxAddress +// 2. data_buffer --> The array of bytes to be read from the flash memory - starting at the address indicated +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes four arguments +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data_buffer --> The array of bytes to be read from the flash memory - starting at the offset on the page indicated +// 4. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +uint8_t SPIFlash::readByteArray(uint32_t address, uint8_t *data_buffer, uint16_t bufferSize, bool fastRead) { + if (!_prepRead(address)) { + + } + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t a = 0; a < bufferSize; a++) { + if (a == (bufferSize-1)) + data_buffer[a] = _readNextByte(NO_CONTINUE); + else + data_buffer[a] = _readNextByte(); + _addressCheck(address++); + } + _endProcess(); + } + return true; +} +// Variant B +uint8_t SPIFlash::readByteArray(uint16_t page_number, uint8_t offset, uint8_t *data_buffer, uint16_t bufferSize, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readByteArray(address, data_buffer, bufferSize, fastRead); +} + +// Reads an array of bytes starting from a specific location in a page.// Has two variants: +// A. Takes three arguments +// 1. address --> Any address from 0 to maxAddress +// 2. data_buffer --> The array of bytes to be read from the flash memory - starting at the address indicated +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes four arguments +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data_buffer --> The array of bytes to be read from the flash memory - starting at the offset on the page indicated +// 4. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +uint8_t SPIFlash::readCharArray(uint32_t address, char *data_buffer, uint16_t bufferSize, bool fastRead) { + if (_prepRead(address)) { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t a = 0; a < bufferSize; a++) { + _addressCheck(address+a); + if (a == (bufferSize-1)) + data_buffer[a] = _readNextByte(NO_CONTINUE); + else + data_buffer[a] = _readNextByte(); + } + _endProcess(); + return true; + } + else + return false; +} +// Variant B +uint8_t SPIFlash::readCharArray(uint16_t page_number, uint8_t offset, char *data_buffer, uint16_t bufferSize, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readCharArray(address, data_buffer, bufferSize, fastRead); +} + +// Reads an unsigned int of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +uint16_t SPIFlash::readWord(uint32_t address, bool fastRead) { + union + { + byte b[sizeof(uint16_t)]; + uint16_t I; + } data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t i=0; i < (sizeof(int16_t)); i++) { + if (i == (sizeof(uint16_t)-1)) + data.b[i] = _readNextByte(NO_CONTINUE); + else + data.b[i] = _readNextByte(); + } + _endProcess(); + return data.I; + } +} +// Variant B +uint16_t SPIFlash::readWord(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readWord(address, fastRead); +} + +// Reads a signed int of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +int16_t SPIFlash::readShort(uint32_t address, bool fastRead) { + union + { + byte b[sizeof(int16_t)]; + int16_t s; + } data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t i=0; i < (sizeof(int16_t)); i++) { + if (i == (sizeof(int16_t)-1)) + data.b[i] = _readNextByte(NO_CONTINUE); + else + data.b[i] = _readNextByte(); + } + _endProcess(); + return data.s; + } +} +// Variant B +int16_t SPIFlash::readShort(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readShort(address, fastRead); +} + +// Reads an unsigned long of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +uint32_t SPIFlash::readULong(uint32_t address, bool fastRead) { + union + { + byte b[sizeof(uint32_t)]; + uint32_t l; + } data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t i=0; i < (sizeof(uint32_t)); i++) { + if (i == (sizeof(uint32_t)-1)) + data.b[i] = _readNextByte(NO_CONTINUE); + else + data.b[i] = _readNextByte(); + } + _endProcess(); + return data.l; + } +} +// Variant B +uint32_t SPIFlash::readULong(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readULong(address, fastRead); +} + +// Reads a signed long of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +int32_t SPIFlash::readLong(uint32_t address, bool fastRead) { + union + { + byte b[sizeof(int32_t)]; + int32_t l; + } data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t i=0; i < (sizeof(int32_t)); i++) { + if (i == (sizeof(int32_t)-1)) + data.b[i] = _readNextByte(NO_CONTINUE); + else + data.b[i] = _readNextByte(); + } + _endProcess(); + return data.l; + } +} +// Variant B +int32_t SPIFlash::readLong(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readLong(address, fastRead); +} + +// Reads a signed long of data from a specific location in a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +float SPIFlash::readFloat(uint32_t address, bool fastRead) { + union + { + byte b[(sizeof(float))]; + float f; + } data; + if (!_prepRead(address)) + return false; + else { + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (uint16_t i=0; i < (sizeof(float)); i++) { + if (i == (sizeof(float)-1)) + data.b[i] = _readNextByte(NO_CONTINUE); + else + data.b[i] = _readNextByte(); + } + _endProcess(); + return data.f; + } +} +// Variant B +float SPIFlash::readFloat(uint16_t page_number, uint8_t offset, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + + return readFloat(address, fastRead); +} + +// Reads a string from a specific location on a page. +// Has two variants: +// A. Takes three arguments +// 1. address --> Any address from 0 to maxAddress +// 2. outputString --> String variable to write the output to +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes four arguments +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. outputString --> String variable to write the output to +// 4. fastRead --> defaults to false - executes _beginFastRead() if set to true +// This function first reads a short from the address to figure out the size of the String object stored and +// then reads the String object data +// Variant A +bool SPIFlash::readStr(uint32_t address, String &outStr, bool fastRead) { + if (!_prepRead(address)) + return false; + uint16_t strLen; + + strLen = readShort(address); + address+=(sizeof(strLen)); + + char outputChar[strLen]; + + readCharArray(address, outputChar, strLen, fastRead); + + outStr = String(outputChar); + return true; +} +// Variant B +bool SPIFlash::readStr(uint16_t page_number, uint8_t offset, String &outStr, bool fastRead) { + uint32_t address = _getAddress(page_number, offset); + return readStr(address, outStr, fastRead); +} + +// Reads a page of data into a page buffer. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. data_buffer --> a data buffer to read the data into (This HAS to be an array of 256 bytes) +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +bool SPIFlash::readPage(uint16_t page_number, uint8_t *data_buffer, bool fastRead) { + uint32_t address = _prepRead(page_number); + + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + + for (int a = 0; a < 256; ++a) { + if (a == (255)) + data_buffer[a] = _readNextByte(NO_CONTINUE); + else + data_buffer[a] = _readNextByte(); + } + _endProcess(); + return true; +} + +// Writes a byte of data to a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One byte of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One byte of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeByte(uint32_t address, uint8_t data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + _beginWrite(address); + _writeNextByte(data, NO_CONTINUE); + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeByte(uint16_t page_number, uint8_t offset, uint8_t data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeByte(address, data, errorCheck); +} + +// Writes a char of data to a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One char of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One char of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeChar(uint32_t address, int8_t data, bool errorCheck) { + if (!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + _beginWrite(address); + _writeNextByte(data, NO_CONTINUE); + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); + +} +// Variant B +bool SPIFlash::writeChar(uint16_t page_number, uint8_t offset, int8_t data, bool errorCheck) { + uint32_t address = _prepWrite(page_number, offset); + + return writeChar(address, data, errorCheck); + +} + +// Writes an array of bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> An array of bytes to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> An array of bytes to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeByteArray(uint32_t address, uint8_t *data_buffer, uint16_t bufferSize, bool errorCheck) { + if (!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data_buffer))) + return false; + #endif + + _beginWrite(address); + + for (int i = 0; i < bufferSize; i++) { + _addressCheck(address+i); + if (i == (bufferSize-1)) + _writeNextByte(data_buffer[i], NO_CONTINUE); + else + _writeNextByte(data_buffer[i]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data_buffer); +} +// Variant B +bool SPIFlash::writeByteArray(uint16_t page_number, uint8_t offset, uint8_t *data_buffer, uint16_t bufferSize, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeByteArray(address, data_buffer, bufferSize, errorCheck); +} + +// Writes an array of bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> An array of chars to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> An array of chars to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeCharArray(uint32_t address, char *data_buffer, uint16_t bufferSize, bool errorCheck) { + if (!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data_buffer))) + return false; + #endif + + _beginWrite(address); + + for (int i = 0; i < bufferSize; i++) { + _addressCheck(address+i); + if (i == (bufferSize-1)) + _writeNextByte(data_buffer[i], NO_CONTINUE); + else + _writeNextByte(data_buffer[i]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data_buffer); +} +// Variant B +bool SPIFlash::writeCharArray(uint16_t page_number, uint8_t offset, char *data_buffer, uint16_t bufferSize, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeCharArray(address, data_buffer, bufferSize, errorCheck); +} + +// Writes an unsigned int as two bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One unsigned int of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One unsigned int of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeWord(uint32_t address, uint16_t data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + union + { + uint8_t b[sizeof(data)]; + uint16_t w; + } var; + var.w = data; + + _beginWrite(address); + for (uint16_t j = 0; j < sizeof(data); j++) { + if (j == (sizeof(data)-1)) + _writeNextByte(var.b[j], NO_CONTINUE); + else + _writeNextByte(var.b[j]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeWord(uint16_t page_number, uint8_t offset, uint16_t data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeWord(address, data, errorCheck); +} + +// Writes a signed int as two bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One signed int of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One signed int of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeShort(uint32_t address, int16_t data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + union + { + uint8_t b[sizeof(data)]; + int16_t s; + } var; + var.s = data; + _beginWrite(address); + for (uint16_t j = 0; j < (sizeof(data)); j++) { + if (j == (sizeof(data)-1)) + _writeNextByte(var.b[j], NO_CONTINUE); + else + _writeNextByte(var.b[j]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeShort(uint16_t page_number, uint8_t offset, int16_t data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeShort(address, data, errorCheck); +} + +// Writes an unsigned long as four bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One unsigned long of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One unsigned long of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeULong(uint32_t address, uint32_t data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + union + { + uint8_t b[sizeof(data)]; + uint32_t l; + } var; + var.l = data; + _beginWrite(address); + for (uint16_t j = 0; j < (sizeof(data)); j++) { + if (j == (sizeof(data)-1)) + _writeNextByte(var.b[j], NO_CONTINUE); + else + _writeNextByte(var.b[j]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeULong(uint16_t page_number, uint8_t offset, uint32_t data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeULong(address, data, errorCheck); +} + +// Writes a signed long as four bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One signed long of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One signed long of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeLong(uint32_t address, int32_t data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + union + { + uint8_t b[sizeof(data)]; + int32_t l; + } var; + var.l = data; + _beginWrite(address); + for (uint16_t j = 0; j < (sizeof(data)); j++) { + if (j == (sizeof(data)-1)) + _writeNextByte(var.b[j], NO_CONTINUE); + else + _writeNextByte(var.b[j]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeLong(uint16_t page_number, uint8_t offset, int32_t data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeLong(address, data, errorCheck); +} + +// Writes a float as four bytes starting from a specific location in a page. +// Has two variants: +// A. Takes three arguments - +// 1. address --> Any address - from 0 to maxAddress +// 2. data --> One float of data to be written to a particular location on a page +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. data --> One float of data to be written to a particular location on a page +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +bool SPIFlash::writeFloat(uint32_t address, float data, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data))) + return false; + #endif + + union + { + uint8_t b[sizeof(data)]; + float f; + } var; + var.f = data; + _beginWrite(address); + for (uint16_t j = 0; j < (sizeof(data)); j++) { + if (j == (sizeof(data)-1)) + _writeNextByte(var.b[j], NO_CONTINUE); + else + _writeNextByte(var.b[j]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, data); +} +// Variant B +bool SPIFlash::writeFloat(uint16_t page_number, uint8_t offset, float data, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + + return writeFloat(address, data, errorCheck); +} + +// Reads a string from a specific location on a page. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. inputString --> String variable to write the data from +// 3. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes four arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. inputString --> String variable to write the data from +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// This function first writes the size of the string as an unsigned int to the address to figure out the size of the String object stored and +// then writes the String object data. Therefore it takes up two bytes more than the size of the String itself. +// Variant A +bool SPIFlash::writeStr(uint32_t address, String &inputStr, bool errorCheck) { + if(!_prepWrite(address)) + return false; + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(inputStr))) + return false; + #endif + + uint16_t inStrLen = inputStr.length() + 1; + char inputChar[inStrLen]; + writeWord(address, inStrLen, errorCheck); + + address+=sizeof(inStrLen); + + inputStr.toCharArray(inputChar, inStrLen); + writeCharArray(address, inputChar, inStrLen, errorCheck); + return true; +} +// Variant B +bool SPIFlash::writeStr(uint16_t page_number, uint8_t offset, String &inputStr, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + return writeStr(address, inputStr, errorCheck); +} + +// Writes a page of data from a data_buffer array. Make sure the sizeOf(uint8_t data_buffer[]) == 256. +// errorCheck --> Turned on by default. Checks for writing errors. +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +bool SPIFlash::writePage(uint16_t page_number, uint8_t *data_buffer, bool errorCheck) { + uint32_t address = _prepWrite(page_number); + + #ifndef HIGHSPEED + if(!_notPrevWritten(address, sizeof(data_buffer))) + return false; + #endif + + _beginWrite(address); + for (uint16_t i = 0; i < PAGESIZE; ++i){ + if (i == (PAGESIZE-1)) + _writeNextByte(data_buffer[i], NO_CONTINUE); + else + _writeNextByte(data_buffer[i]); + } + _endProcess(); + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, *data_buffer); +} + + +//Erases one 4k sector. Has two variants: +// A. Takes the address as the argument and erases the sector containing the address. +// B. Takes page to be erased as the argument and erases the sector containing the page. +// The sectors are numbered 0 - 255 containing 16 pages each. +// Page 0-15 --> Sector 0; Page 16-31 --> Sector 1;......Page 4080-4095 --> Sector 255 +// Variant A +bool SPIFlash::eraseSector(uint32_t address) { + if(!_notBusy()||!_writeEnable()) + return false; + + _cmd(SECTORERASE); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, 0x00); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(0); + CHIP_DESELECT + #endif + + if(!_notBusy(410L)) + return false; //Datasheet says erasing a sector takes 400ms max + + //_writeDisable(); //_writeDisable() is not required because the Write Enable Latch (WEL) flag is cleared to 0 + // i.e. to write disable state upon the following conditions: + // Power-up, Write Disable, Page Program, Quad Page Program, ``Sector Erase``, Block Erase, Chip Erase, Write Status Register, + // Erase Security Register and Program Security register + + return true; +} +// Variant B +bool SPIFlash::eraseSector(uint16_t page_number, uint8_t offset) { + uint32_t address = _getAddress(page_number, offset); + return eraseSector(address); +} + +//Erases one 32k block. Has two variants: +// A. Takes the address as the argument and erases the block containing the address. +// B. Takes page to be erased as the argument and erases the block containing the page. +// The blocks are numbered 0 - 31 containing 128 pages each. +// Page 0-127 --> Block 0; Page 128-255 --> Block 1;......Page 3968-4095 --> Block 31 +// Variant A +bool SPIFlash::eraseBlock32K(uint32_t address) { + if(!_notBusy()||!_writeEnable()) + return false; + + _cmd(BLOCK32ERASE); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, 0x00); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(0); + CHIP_DESELECT + #endif + + if(!_notBusy(410L)) + return false; //Datasheet says erasing a sector takes 400ms max + + //_writeDisable(); //_writeDisable() is not required because the Write Enable Latch (WEL) flag is cleared to 0 + // i.e. to write disable state upon the following conditions: + // Power-up, Write Disable, Page Program, Quad Page Program, Sector Erase, ``Block Erase``, Chip Erase, Write Status Register, + // Erase Security Register and Program Security register + + return true; +} +// Variant B +bool SPIFlash::eraseBlock32K(uint16_t page_number, uint8_t offset) { + uint32_t address = _getAddress(page_number, offset); + return eraseBlock32K(address); +} + +//Erases one 64k block. Has two variants: +// A. Takes the address as the argument and erases the block containing the address. +// B. Takes page to be erased as the argument and erases the block containing the page. +// The blocks are numbered 0 - 15 containing 256 pages each. +// Page 0-255 --> Block 0; Page 256-511 --> Block 1;......Page 3840-4095 --> Block 15 +// Variant A +bool SPIFlash::eraseBlock64K(uint32_t address) { + if(!_notBusy()||!_writeEnable()) + return false; + + _cmd(BLOCK64ERASE); + #if defined (__arm__) && defined (__SAM3X8E__) + SPI.transfer(csPin, address >> 16, SPI_CONTINUE); + SPI.transfer(csPin, address >> 8, SPI_CONTINUE); + SPI.transfer(csPin, 0x00); + #else + (void)xfer(address >> 16); + (void)xfer(address >> 8); + (void)xfer(0); + CHIP_DESELECT + #endif + + if(!_notBusy(410L)) + return false; //Datasheet says erasing a sector takes 400ms max + + //_writeDisable(); //_writeDisable() is not required because the Write Enable Latch (WEL) flag is cleared to 0 + // i.e. to write disable state upon the following conditions: + // Power-up, Write Disable, Page Program, Quad Page Program, Sector Erase, ``Block Erase``, Chip Erase, Write Status Register, + // Erase Security Register and Program Security register + + return true; +} +// Variant B +bool SPIFlash::eraseBlock64K(uint16_t page_number, uint8_t offset) { + uint32_t address = _getAddress(page_number, offset); + return eraseBlock64K(address); +} + +//Erases whole chip. Think twice before using. +bool SPIFlash::eraseChip(void) { + if(!_notBusy()||!_writeEnable()) + return false; + + _cmd(CHIPERASE, NO_CONTINUE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + + if(!_notBusy(7000L)) + return false; //Datasheet says erasing chip takes 6s max + + //_writeDisable(); //_writeDisable() is not required because the Write Enable Latch (WEL) flag is cleared to 0 + // i.e. to write disable state upon the following conditions: + // Power-up, Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, ``Chip Erase``, Write Status Register, + // Erase Security Register and Program Security register + + return true; + +} + +//Suspends current Block Erase/Sector Erase/Page Program. Does not suspend chipErase(). +//Page Program, Write Status Register, Erase instructions are not allowed. +//Erase suspend is only allowed during Block/Sector erase. +//Program suspend is only allowed during Page/Quad Page Program +bool SPIFlash::suspendProg(void) { + if(_notBusy() || !_noSuspend()) + return false; + + _cmd(SUSPEND, NO_CONTINUE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + + _delay_us(20); + + if(!_notBusy() || _noSuspend()) //Max suspend Enable time according to datasheet + return false; + return true; +} + +//Resumes previously suspended Block Erase/Sector Erase/Page Program. +bool SPIFlash::resumeProg(void) { + if(!_notBusy() || _noSuspend()) + return false; + + _cmd(RESUME, NO_CONTINUE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + + _delay_us(20); + + if(_notBusy() || !_noSuspend()) + return false; + return true; + +} + +//Puts device in low power state. Good for battery powered operations. +//Typical current consumption during power-down is 1mA with a maximum of 5mA. (Datasheet 7.4) +//In powerDown() the chip will only respond to powerUp() +bool SPIFlash::powerDown(void) { + if(!_notBusy()) + return false; + + _cmd(POWERDOWN, NO_CONTINUE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + _delay_us(3); //Max powerDown enable time according to the Datasheet + + uint8_t status1 = _readStat1(); + uint8_t status2 = _readStat1(); + status1 = _readStat1(); + + if (status1 != 255 && status2 != 255) { + if (status1 == status2 || status1 == 0 || status2 == 0) { + status1 = _readStat1(); + status2 = _readStat1(); + } + else if (status1 != status2) + return true; + } + else if (status1 == 255 && status2 == 255) + return true; + else if (status1 == 0 && status2 == 0) + return false; + return true; +} + +//Wakes chip from low power state. +bool SPIFlash::powerUp(void) { + + _cmd(RELEASE, NO_CONTINUE); + #if defined (__AVR__) + CHIP_DESELECT + #endif + _delay_us(3); //Max release enable time according to the Datasheet + + if (_readStat1() == 255) + return false; + return true; +} + +/************************************************************************************************************************ + These functions are deprecated to enable compatibility with various AVR chips. They can be used by uncommenting + this block of code. However, be warned, this particular block of code has only been tested with the Arduino + IDE (1.6.5) and only with 8-bit AVR based Arduino boards and is not supported from library version 2.0 onward + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + // These functions work with data to/from Serial stream. // + // Declares Serial.begin() if not previously declared. // + // Initiates Serial at 115200 baud. // + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// + + + This function is deprecated to enable compatibility with various AVR chips. It can be used by uncommenting + this block of code. However, be warned, this particular block of code has only been tested with the Arduino + IDE and only with 8-bit AVR based Arduino boards. + +//Prints hex/dec formatted data from page reads - for debugging +void SPIFlash::_printPageBytes(uint8_t *data_buffer, uint8_t outputType) { + char buffer[10]; + for (int a = 0; a < 16; ++a) { + for (int b = 0; b < 16; ++b) { + if (outputType == 1) { + sprintf(buffer, "%02x", data_buffer[a * 16 + b]); + Serial.print(buffer); + } + else if (outputType == 2) { + uint8_t x = data_buffer[a * 16 + b]; + if (x < 10) Serial.print("0"); + if (x < 100) Serial.print("0"); + Serial.print(x); + Serial.print(','); + } + } + Serial.println(); + } +} + +//Reads a string from Serial +bool SPIFlash::readSerialStr(String &inputStr) { + if(!Serial) + Serial.begin(115200); + while (Serial.available()) { + inputStr = Serial.readStringUntil('\n'); + return true; + } + return false; +} + +//Reads a page of data and prints it to Serial stream. Make sure the sizeOf(uint8_t data_buffer[]) == 256. +void SPIFlash::printPage(uint16_t page_number, uint8_t outputType, bool fastRead) { + if(!Serial) + Serial.begin(115200); + + char buffer[24]; + sprintf(buffer, "Reading page (%04x)", page_number); + Serial.println(buffer); + + uint8_t data_buffer[256]; + readPage(page_number, data_buffer, fastRead); + _printPageBytes(data_buffer, outputType); +} + +//Reads all pages on Flash chip and dumps it to Serial stream. +//This function is useful when extracting data from a flash chip onto a computer as a text file. +void SPIFlash::printAllPages(uint8_t outputType, bool fastRead) { + if(!Serial) + Serial.begin(115200); + + Serial.println("Reading all pages"); + uint8_t data_buffer[256]; + + for (int a = 0; a < maxPage; a++) { + readPage(a, data_buffer, fastRead); + _printPageBytes(data_buffer, outputType); + } +} +************************************************************************************************************************/ \ No newline at end of file diff --git a/tools/olimexino-32u4 firmware/src/SPIFlash.h b/tools/olimexino-32u4 firmware/src/SPIFlash.h new file mode 100644 index 0000000..caad5d7 --- /dev/null +++ b/tools/olimexino-32u4 firmware/src/SPIFlash.h @@ -0,0 +1,267 @@ +/* Arduino SPIFlash Library v.2.2.0 + * Copyright (C) 2015 by Prajwal Bhattaram + * Modified by Prajwal Bhattaram - 24/11/2015 + * + * This file is part of the Arduino SPIFlash Library. This library is for + * Winbond NOR flash memory modules. In its current form it enables reading + * and writing individual data variables, structs and arrays from and to various locations; + * reading and writing pages; continuous read functions; sector, block and chip erase; + * suspending and resuming programming/erase and powering down for low power operation. + * + * This Library is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This Library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License v3.0 + * along with the Arduino SPIFlash Library. If not, see + * . + */ + +#ifndef SPIFLASH_H +#define SPIFLASH_H + +#include + +class SPIFlash { +public: + //----------------------------------------------Constructor-----------------------------------------------// + SPIFlash(uint8_t cs = 10, bool overflow = true); + //----------------------------------------Initial / Chip Functions----------------------------------------// + void begin(); + uint16_t getManID(); + uint32_t getJEDECID(); + bool getAddress(uint16_t size, uint16_t &page_number, uint8_t &offset); + uint32_t getAddress(uint16_t size); + uint16_t getChipName(); + uint16_t sizeofStr(String &inputStr); + uint32_t getCapacity(); + uint32_t getMaxPage(); + //-------------------------------------------Write / Read Bytes-------------------------------------------// + bool writeByte(uint32_t address, uint8_t data, bool errorCheck = true); + bool writeByte(uint16_t page_number, uint8_t offset, uint8_t data, bool errorCheck = true); + uint8_t readByte(uint16_t page_number, uint8_t offset, bool fastRead = false); + uint8_t readByte(uint32_t address, bool fastRead = false); + //----------------------------------------Write / Read Byte Arrays----------------------------------------// + bool writeByteArray(uint32_t address, uint8_t *data_buffer, uint16_t bufferSize, bool errorCheck = true); + bool writeByteArray(uint16_t page_number, uint8_t offset, uint8_t *data_buffer, uint16_t bufferSize, bool errorCheck = true); + uint8_t readByteArray(uint32_t address, uint8_t *data_buffer, uint16_t bufferSize, bool fastRead = false); + uint8_t readByteArray(uint16_t page_number, uint8_t offset, uint8_t *data_buffer, uint16_t bufferSize, bool fastRead = false); + //-------------------------------------------Write / Read Chars-------------------------------------------// + bool writeChar(uint32_t address, int8_t data, bool errorCheck = true); + bool writeChar(uint16_t page_number, uint8_t offset, int8_t data, bool errorCheck = true); + int8_t readChar(uint32_t address, bool fastRead = false); + int8_t readChar(uint16_t page_number, uint8_t offset, bool fastRead = false); + //----------------------------------------Write / Read Char Arrays----------------------------------------// + bool writeCharArray(uint32_t address, char *data_buffer, uint16_t bufferSize, bool errorCheck = true); + bool writeCharArray(uint16_t page_number, uint8_t offset, char *data_buffer, uint16_t bufferSize, bool errorCheck = true); + uint8_t readCharArray(uint32_t address, char *data_buffer, uint16_t buffer_size, bool fastRead = false); + uint8_t readCharArray(uint16_t page_number, uint8_t offset, char *data_buffer, uint16_t buffer_size, bool fastRead = false); + //------------------------------------------Write / Read Shorts------------------------------------------// + bool writeShort(uint32_t address, int16_t data, bool errorCheck = true); + bool writeShort(uint16_t page_number, uint8_t offset, int16_t data, bool errorCheck = true); + int16_t readShort(uint32_t address, bool fastRead = false); + int16_t readShort(uint16_t page_number, uint8_t offset, bool fastRead = false); + //-------------------------------------------Write / Read Words-------------------------------------------// + bool writeWord(uint32_t address, uint16_t data, bool errorCheck = true); + bool writeWord(uint16_t page_number, uint8_t offset, uint16_t data, bool errorCheck = true); + uint16_t readWord(uint32_t address, bool fastRead = false); + uint16_t readWord(uint16_t page_number, uint8_t offset, bool fastRead = false); + //-------------------------------------------Write / Read Longs-------------------------------------------// + bool writeLong(uint32_t address, int32_t data, bool errorCheck = true); + bool writeLong(uint16_t page_number, uint8_t offset, int32_t data, bool errorCheck = true); + int32_t readLong(uint32_t address, bool fastRead = false); + int32_t readLong(uint16_t page_number, uint8_t offset, bool fastRead = false); + //--------------------------------------Write / Read Unsigned Longs---------------------------------------// + bool writeULong(uint32_t address, uint32_t data, bool errorCheck = true); + bool writeULong(uint16_t page_number, uint8_t offset, uint32_t data, bool errorCheck = true); + uint32_t readULong(uint32_t address, bool fastRead = false); + uint32_t readULong(uint16_t page_number, uint8_t offset, bool fastRead = false); + //-------------------------------------------Write / Read Floats------------------------------------------// + bool writeFloat(uint32_t address, float data, bool errorCheck = true); + bool writeFloat(uint16_t page_number, uint8_t offset, float data, bool errorCheck = true); + float readFloat(uint32_t address, bool fastRead = false); + float readFloat(uint16_t page_number, uint8_t offset, bool fastRead = false); + //------------------------------------------Write / Read Strings------------------------------------------// + bool writeStr(uint32_t address, String &inputStr, bool errorCheck = true); + bool writeStr(uint16_t page_number, uint8_t offset, String &inputStr, bool errorCheck = true); + bool readStr(uint32_t address, String &outStr, bool fastRead = false); + bool readStr(uint16_t page_number, uint8_t offset, String &outStr, bool fastRead = false); + //-------------------------------------------Write / Read Pages-------------------------------------------// + bool writePage(uint16_t page_number, uint8_t *data_buffer, bool errorCheck = true); + bool readPage(uint16_t page_number, uint8_t *data_buffer, bool fastRead = false); + //------------------------------------------Write / Read Anything-----------------------------------------// + template bool writeAnything(uint32_t address, const T& value, bool errorCheck = true); + template bool writeAnything(uint16_t page_number, uint8_t offset, const T& value, bool errorCheck = true); + template bool readAnything(uint32_t address, T& value, bool fastRead = false); + template bool readAnything(uint16_t page_number, uint8_t offset, T& value, bool fastRead = false); + //--------------------------------------------Erase functions---------------------------------------------// + bool eraseSector(uint32_t address); + bool eraseSector(uint16_t page_number, uint8_t offset); + bool eraseBlock32K(uint32_t address); + bool eraseBlock32K(uint16_t page_number, uint8_t offset); + bool eraseBlock64K(uint32_t address); + bool eraseBlock64K(uint16_t page_number, uint8_t offset); + bool eraseChip(void); + //---------------------------------------------Power functions--------------------------------------------// + bool suspendProg(void); + bool resumeProg(void); + bool powerDown(void); + bool powerUp(void); + //--------------------------------------------Private functions-------------------------------------------// +private: + void _troubleshoot(uint8_t error); + void _cmd(uint8_t cmd, bool _continue = true, uint8_t cs = 0); + void _endProcess(void); + void _errorCodeCheck(void); + void _beginRead(uint32_t address); + void _beginFastRead(uint32_t address); + bool _noSuspend(void); + bool _notBusy(uint32_t timeout = 10L); + bool _notPrevWritten(uint32_t address, uint8_t size = 1); + bool _addressCheck(uint32_t address); + bool _beginWrite(uint32_t address); + bool _writeNextByte(uint8_t c, bool _continue = true); + bool _writeEnable(void); + bool _writeDisable(void); + bool _getJedecId(uint8_t *b1, uint8_t *b2, uint8_t *b3); + bool _getManId(uint8_t *b1, uint8_t *b2); + bool _chipID(void); + uint8_t _readStat1(void); + uint8_t _readNextByte(bool _continue = true); + uint32_t _getAddress(uint16_t page_number, uint8_t offset = 0); + uint32_t _prepRead(uint32_t address); + uint32_t _prepRead(uint16_t page_number, uint8_t offset = 0); + uint32_t _prepWrite(uint32_t address); + uint32_t _prepWrite(uint16_t page_number, uint8_t offset = 0); + template bool _writeErrorCheck(uint32_t address, const T& value); + //-------------------------------------------Private variables------------------------------------------// + bool pageOverflow; + volatile uint8_t *cs_port; + uint8_t cs_mask, csPin, errorcode; + uint16_t name; + uint32_t capacity, maxPage; + uint32_t currentAddress = 1; + const uint8_t devType[10] = {0x5, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17}; + const uint32_t memSize[10] = {64L * 1024L, 128L * 1024L, 256L * 1024L, 512L * 1024L, 1L * 1024L * 1024L, + 2L * 1024L * 1024L, 4L * 1024L * 1024L, 8L * 1024L * 1024L, 16L * 1024L * 1024L}; + const uint16_t chipName[10] = {05, 10, 20, 40, 80, 16, 32, 64, 128, 256}; +}; + + + //--------------------------------------------Templates-------------------------------------------// + +// Writes any type of data to a specific location in the flash memory. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. T& value --> Variable to return data into +// 4. errorCheck --> Turned on by default. Checks for writing errors +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. const T& value --> Variable with the data to be written +// 4. errorCheck --> Turned on by default. Checks for writing errors +// WARNING: You can only write to previously erased memory locations (see datasheet). +// Use the eraseSector()/eraseBlock32K/eraseBlock64K commands to first clear memory (write 0xFFs) +// Variant A +template bool SPIFlash::writeAnything(uint32_t address, const T& value, bool errorCheck) { + if (!_prepWrite(address)) + return false; + else { + const byte* p = (const byte*)(const void*)&value; + _beginWrite(address); + for (uint16_t i = 0; i < sizeof(value); i++) { + #if defined (__arm__) && defined (__SAM3X8E__) + if (i == sizeof(value)-1) + _writeNextByte(*p++, false); + #endif + _writeNextByte(*p++); + } + _endProcess(); + } + + if (!errorCheck) + return true; + else + return _writeErrorCheck(address, value); +} +// Variant B +template bool SPIFlash::writeAnything(uint16_t page_number, uint8_t offset, const T& value, bool errorCheck) { + uint32_t address = _getAddress(page_number, offset); + return writeAnything(address, value, errorCheck); +} + +// Reads any type of data from a specific location in the flash memory. +// Has two variants: +// A. Takes two arguments - +// 1. address --> Any address from 0 to maxAddress +// 2. T& value --> Variable to return data into +// 2. fastRead --> defaults to false - executes _beginFastRead() if set to true +// B. Takes three arguments - +// 1. page --> Any page number from 0 to maxPage +// 2. offset --> Any offset within the page - from 0 to 255 +// 3. T& value --> Variable to return data into +// 3. fastRead --> defaults to false - executes _beginFastRead() if set to true +// Variant A +template bool SPIFlash::readAnything(uint32_t address, T& value, bool fastRead) { + if (!_prepRead(address)) + return false; + + byte* p = (byte*)(void*)&value; + if(!fastRead) + _beginRead(address); + else + _beginFastRead(address); + for (uint16_t i = 0; i < sizeof(value); i++) { + #if defined (__arm__) && defined (__SAM3X8E__) + if (i == sizeof(value)-1) + *p++ = _readNextByte(false); + #endif + *p++ =_readNextByte(); + } + _endProcess(); + return true; +} +// Variant B +template bool SPIFlash::readAnything(uint16_t page_number, uint8_t offset, T& value, bool fastRead) +{ + uint32_t address = _getAddress(page_number, offset); + return readAnything(address, value, fastRead); +} + +// Private template to check for errors in writing to flash memory +template bool SPIFlash::_writeErrorCheck(uint32_t address, const T& value) { +if (!_prepRead(address)) + return false; + + const byte* p = (const byte*)(const void*)&value; + _beginRead(address); + for(uint16_t i = 0; i < sizeof(value);i++) + { + #if defined (__arm__) && defined (__SAM3X8E__) + if (i == sizeof(value)-1) { + if (*p++ != _readNextByte(false)) + return false; + else + return true; + } + else + if (*p++ != _readNextByte()) + return false; + #elif defined (__AVR__) + if (*p++ != _readNextByte()) + return false; + #endif + } + _endProcess(); + return true; +} + + +#endif // _SPIFLASH_H_ \ No newline at end of file diff --git a/tools/olimexino-32u4 firmware/src/iceprog.cpp b/tools/olimexino-32u4 firmware/src/iceprog.cpp new file mode 120000 index 0000000..c0874a9 --- /dev/null +++ b/tools/olimexino-32u4 firmware/src/iceprog.cpp @@ -0,0 +1 @@ +../iceprog.ino \ No newline at end of file diff --git a/tools/removeCode.sh b/tools/removeCode.sh new file mode 100755 index 0000000..c40a79c --- /dev/null +++ b/tools/removeCode.sh @@ -0,0 +1,23 @@ +#!/bin/sh +for filename in ../*/*.v +do + sed -i '1,/Put your code here:/!d' ${filename} + echo "\nendmodule" >> ${filename} +done +sed -i '1,/endmodule/!d' ../01_Boolean_Logic/Nand.v +sed -i '1,/endmodule/!d' ../03_Sequential_Logic/DFF.v +sed -i '1,/endmodule/!d' ../03_Sequential_Logic/RAM256.v +sed -i '1,/endmodule/!d' ../05_Computer_Architecture/ROM.v +sed -i '1,/endmodule/!d' ../06_IO_Devices/InOut.v + +sed -i '/[\t]/d' ../07_Operating_System/*.jack + +sed -i '/[\t]/d' ../04_Machine_Language/*.asm +for filename in ../06_IO_Devices/*/*.asm +do + sed -i '1,/Put your code here:/!d' ${filename} +done +sed -i '/REMOVE CODE/d' ../07_Operating_System/12_Tetris/Main.jack +#rm -r ../tools/Assembler/src +#rm -r ../tools/VMTranslator/src +#rm -r ../tools/JackCompiler/src diff --git a/tools/vim/ftdetect/hack_asm.vim b/tools/vim/ftdetect/hack_asm.vim new file mode 100644 index 0000000..c9c404d --- /dev/null +++ b/tools/vim/ftdetect/hack_asm.vim @@ -0,0 +1 @@ +autocmd BufNewFile,BufRead *.asm set filetype=hack_asm diff --git a/tools/vim/ftdetect/hack_vm.vim b/tools/vim/ftdetect/hack_vm.vim new file mode 100644 index 0000000..fbf1a64 --- /dev/null +++ b/tools/vim/ftdetect/hack_vm.vim @@ -0,0 +1 @@ +autocmd BufNewFile,BufRead *.vm set filetype=hack_vm diff --git a/tools/vim/ftdetect/hdl.vim b/tools/vim/ftdetect/hdl.vim new file mode 100644 index 0000000..1eec486 --- /dev/null +++ b/tools/vim/ftdetect/hdl.vim @@ -0,0 +1 @@ +autocmd BufNewFile,BufRead *.hdl set filetype=hdl diff --git a/tools/vim/ftdetect/jack.vim b/tools/vim/ftdetect/jack.vim new file mode 100644 index 0000000..f2f54df --- /dev/null +++ b/tools/vim/ftdetect/jack.vim @@ -0,0 +1 @@ +autocmd BufNewFile,BufRead *.jack set filetype=jack diff --git a/tools/vim/syntax/c.vim b/tools/vim/syntax/c.vim new file mode 100644 index 0000000..42e4249 --- /dev/null +++ b/tools/vim/syntax/c.vim @@ -0,0 +1,2 @@ +syn match cType "pair " +syn match cType "number " diff --git a/tools/vim/syntax/hack_asm.vim b/tools/vim/syntax/hack_asm.vim new file mode 100644 index 0000000..c0fe657 --- /dev/null +++ b/tools/vim/syntax/hack_asm.vim @@ -0,0 +1,32 @@ +" Vim syntax file +" Language: Hack Assembly +" Maintainer: Severyn Kozak +" Latest Revision: 15 November 2014 + +if version < 600 + syntax clear +endif + +setl iskeyword+=.,$,: + +syn keyword hackAsmDestination A M D AM MD AD AMD null +syn keyword hackAsmJump JGT JEQ JGE JLT JNE JLE JMP + +syn match hackAsmComment "\/\/.*$" +syn match hackAsmLabel "(\k\+)" +syn match hackAsmMathOp "[+-]" +syn match hackAsmBitwiseOp "[&|]" +syn match hackAsmAInstruction "@\k\+" +syn match hackAsmCInstruction "[=;]" +syn match hackAsmConstant "-1\|0\|1" + +hi link hackAsmDestination Identifier +hi link hackAsmJump Function +hi link hackAsmConstant Constant + +hi link hackAsmComment Comment +hi link hackAsmLabel Label +hi link hackAsmMathOp Operator +hi link hackAsmBitwiseOp Operator +hi link hackAsmAInstruction PreProc +hi link hackAsmCInstruction Operator diff --git a/tools/vim/syntax/hack_vm.vim b/tools/vim/syntax/hack_vm.vim new file mode 100644 index 0000000..227c51c --- /dev/null +++ b/tools/vim/syntax/hack_vm.vim @@ -0,0 +1,29 @@ +" Vim syntax file +" Language: Hack Virtual Machine +" Maintainer: Severyn Kozak +" Latest Revision: 02 December 2014 + +if version < 600 + syntax clear +endif + +setl iskeyword+=.,: +setl iskeyword+=- + +syn keyword hackVmMathLogicOp add sub neg eq gt lt or not +syn keyword hackVmMemoryOp push pop +syn keyword hackVmMemorySegments argument local static constant this that + \ pointer temp +syn keyword hackVmProgramFlowOp label goto if-goto +syn keyword hackVmFunctionCallOp function call return + +syn match hackVmComment "\/\/.*$" +syn match hackVmNumber "\v(\w)@=~]" +syn match jackString '"[^"\n]*"' +syn match jackNumber "\d\+" +syn match jackDelimiter "[.,;]" +syn match jackSurroundingElement "[{}()\[\]]" +syn match jackCommentInline "\/\/.*" +syn region jackCommentBlock start="/\*" end="*/" + +hi link jackOp Operator +hi link jackSurroundingElement Delimiter +hi link jackVarType Type +hi link jackFuncType Function +hi link jackDeclaration Statement +hi link jackStatement Statement +hi link jackConstant Constant +hi link jackNumber Number +hi link jackCommentInline Comment +hi link jackCommentBlock Comment +hi link jackDelimiter Comment diff --git a/tools/vim/syntax/nandhdl.vim b/tools/vim/syntax/nandhdl.vim new file mode 100644 index 0000000..56506b1 --- /dev/null +++ b/tools/vim/syntax/nandhdl.vim @@ -0,0 +1,49 @@ +"Vim syntax file +"Language: nand2tetris Hardware Description Language +"Maintainer: Christopher Noussis +"Latest Revision: 14 January 2015 +"TODO: Fix syntax names to work with accepted style convention +"syn keyword [languageName][SyntaxElementName] + +if exists("b:current_syntax") + finish +endif + +"Comments. +syn match hdlComment "\/\/.*$" +syn region hdlComment start='\/\*' end='\*\/' +syn region hdlComment start='\/\*\*' end='\*\/' + +"The all-caps basic language keywords. +syn keyword basicKeywords CHIP PARTS IN OUT BUILTIN CLOCKED + +"Builtin chips. +syn keyword builtInChips Nand Not And Or Xor Mux DMux +syn keyword builtInChips Not16 And16 Or16 Mux16 +syn keyword builtInChips Or8Way Mux4Way16 Mux8Way16 DMux4Way DMux8Way +syn keyword builtInChips HalfAdder FullAdder Add16 ALU Inc16 +syn keyword builtInChips DFF Bit Register ARegister DRegister +syn keyword builtInChips RAM8 RAM64 RAM512 RAM4K RAM16K +syn keyword builtInChips PC ROM32K Screen Keyboard + +"External +syn keyword extPin in out nextgroup=busNumber +syn match busNumber '\[\d*\]' "TODO: Make it so the braces are not matched. +syn region hdlInterface start='{' end='}' fold transparent + +"Internal +syn region hdlImplementation start=':' end='}' fold transparent +syn region partInterface start='(' end=')' contains=connection, extPin +"syn match connection '\w\+(\[\d+\])\*=\w\+(\[\d+\])\*' +syn match connection '\w\+=\@=' contained +syn match connection '=\@<=\w\+' contained + +let b:current_syntax = 'chip' +"Syntax Highlighting +hi def link hdlComment Comment +hi def link basicKeywords Statement +hi def link builtInChips Special +hi def link extPin Type +hi def link busNumber Constant +hi def link connection Identifier +