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add verilog files for project one through five

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This commit is contained in:
Konarak
2024-10-17 14:36:58 -04:00
parent b16bfcfd43
commit 792efa70cd
37 changed files with 871 additions and 275 deletions
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16
03_Sequential_Logic/Bit.v
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@@ -6,12 +6,16 @@
`default_nettype none
module Bit(
input clk,
input in,
input load,
output out
input clk,
input in,
input load,
output out
);
// Put your code here:
// Put your code here:
wire muxout;
// Mux(a=dffout, b=in, sel=load, out=muxout);
// DFF(in=muxout, out=out, out=dffout);
Mux MUX(out, in, load, muxout);
DFF DFF(clk, muxout, out);
endmodule

56
03_Sequential_Logic/BitShift8L.v
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@@ -7,14 +7,56 @@
`default_nettype none
module BitShift8L(
input clk,
input [7:0] in,
input inLSB,
input load,
input shift,
output [7:0] out
input clk,
input [7:0] in,
input inLSB,
input load,
input shift,
output [7:0] out
);
// Put your code here:
// Put your code here:
reg [7:0] reg8;
always @(posedge clk) begin
if (load == 1) begin
reg8[7:0] = in[7:0];
end
else if (shift == 1 ) begin
reg8[7:1] = reg8[6:0];
reg8[0] = inLSB;
end
end
assign out = reg8;
// wire [7:0] out_l;
// wire [7:0] out_s;
// Mux MUXLA(out[0], in[0], load, out_l[0]);
// Mux MUXLB(out[1], in[1], load, out_l[1]);
// Mux MUXLC(out[2], in[2], load, out_l[2]);
// Mux MUXLD(out[3], in[3], load, out_l[3]);
// Mux MUXLE(out[4], in[4], load, out_l[4]);
// Mux MUXLF(out[5], in[5], load, out_l[5]);
// Mux MUXLG(out[6], in[6], load, out_l[6]);
// Mux MUXLH(out[7], in[7], load, out_l[7]);
// Mux MUXSA(out_l[0], inLSB, shift, out_s[0]);
// Mux MUXSB(out_l[1], out[0], shift, out_s[1]);
// Mux MUXSC(out_l[2], out[1], shift, out_s[2]);
// Mux MUXSD(out_l[3], out[2], shift, out_s[3]);
// Mux MUXSE(out_l[4], out[3], shift, out_s[4]);
// Mux MUXSF(out_l[5], out[4], shift, out_s[5]);
// Mux MUXSG(out_l[6], out[5], shift, out_s[6]);
// Mux MUXSH(out_l[7], out[6], shift, out_s[7]);
// Bit BITA(clk, out_s[0], 1'b1, out[0]);
// Bit BITB(clk, out_s[1], 1'b1, out[1]);
// Bit BITC(clk, out_s[2], 1'b1, out[2]);
// Bit BITD(clk, out_s[3], 1'b1, out[3]);
// Bit BITE(clk, out_s[4], 1'b1, out[4]);
// Bit BITF(clk, out_s[5], 1'b1, out[5]);
// Bit BITG(clk, out_s[6], 1'b1, out[6]);
// Bit BITH(clk, out_s[7], 1'b1, out[7]);
endmodule

26
03_Sequential_Logic/BitShift9R.v
View File

@@ -7,14 +7,26 @@
`default_nettype none
module BitShift9R(
input clk,
input [8:0] in,
input inMSB,
input load,
input shift,
output [8:0] out
input clk,
input [8:0] in,
input inMSB,
input load,
input shift,
output [8:0] out
);
// Put your code here:
// Put your code here:
reg [8:0] reg9;
always @(posedge clk) begin
if (load == 1) begin
reg9[7:0] = in[7:0];
end
else if (shift == 1 ) begin
reg9[7:0] = reg9[8:1];
reg9[8] = inMSB;
end
end
assign out = reg9;
endmodule

18
03_Sequential_Logic/DFF.v
View File

@@ -5,16 +5,16 @@
`default_nettype none
module DFF(
input clk,
input in,
output out
input clk,
input in,
output reg out
);
// No need to implement this chip
// This chip is implemented in verilog using reg-variables
reg out;
always @(posedge clk)
if (in) out <= 1'b1;
else out <= 1'b0;
// No need to implement this chip
// This chip is implemented in verilog using reg-variables
// reg out;
always @(posedge clk)
if (in) out <= 1'b1;
else out <= 1'b0;
endmodule

28
03_Sequential_Logic/PC.v
View File

@@ -8,14 +8,24 @@
`default_nettype none
module PC(
input clk,
input [15:0] in,
input load,
input inc,
input reset,
output [15:0] out
);
// Put your code here:
input clk,
input [15:0] in,
input load,
input inc,
input reset,
output [15:0] out
);
// Put your code here:
// wire [15:0] plusone;
// wire [15:0] incstep;
// wire [15:0] loadstep;
// wire [15:0] resetstep;
// Inc16 INC16(out, plusone);
// Mux16 MUX16A(out, plusone, inc, incstep);
// Mux16 MUX16B(incstep, in, load, loadstep);
// Mux16 MUX16C(loadstep, 16'b0, reset, resetstep);
wire [15:0] select;
assign select = reset? 0 : (load? in : (inc? out+1 : out));
Register REG(clk, select, 1'b1, out);
endmodule

44
03_Sequential_Logic/RAM3840.v
View File

@@ -6,13 +6,43 @@
`default_nettype none
module RAM3840(
input clk,
input [11:0] address,
input [15:0] in,
input load,
output [15:0] out
input clk,
input [11:0] address,
input [15:0] in,
input load,
output [15:0] out
);
// Put your code here:
// Put your code here:
wire load0;
wire load1;
wire load2;
wire load3;
wire load4;
wire load5;
wire load6;
wire load7;
wire [15:0] ram0;
wire [15:0] ram1;
wire [15:0] ram2;
wire [15:0] ram3;
wire [15:0] ram4;
wire [15:0] ram5;
wire [15:0] ram6;
wire [15:0] ram7;
DMux8Way DMUX(load, address[11:9],
load0, load1, load2, load3, load4, load5, load6, load7);
RAM512 RAM0(clk, address[8:0], in, load0, ram0);
RAM512 RAM1(clk, address[8:0], in, load1, ram1);
RAM512 RAM2(clk, address[8:0], in, load2, ram2);
RAM512 RAM3(clk, address[8:0], in, load3, ram3);
RAM512 RAM4(clk, address[8:0], in, load4, ram4);
RAM512 RAM5(clk, address[8:0], in, load5, ram5);
RAM512 RAM6(clk, address[8:0], in, load6, ram6);
RAM256 RAM7(clk, address[7:0], in, load7, ram7);
Mux8Way16 MUX(ram0, ram1, ram2, ram3, ram4, ram5, ram6, ram7,
address[11:9], out);
endmodule

22
03_Sequential_Logic/RAM512.v
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@@ -6,13 +6,21 @@
`default_nettype none
module RAM512(
input clk,
input [8:0] address,
input [15:0] in,
input load,
output [15:0] out
input clk,
input [8:0] address,
input [15:0] in,
input load,
output [15:0] out
);
// Put your code here:
// Put your code here:
wire load0;
wire load1;
wire [15:0] ram0;
wire [15:0] ram1;
DMux DMUX(load, address[8], load0, load1);
RAM256 RAM0(clk, address[7:0], in, load0, ram0);
RAM256 RAM1(clk, address[7:0], in, load1, ram1);
Mux16 MUX(ram0, ram1, address[8], out);
endmodule

27
03_Sequential_Logic/Register.v
View File

@@ -7,12 +7,27 @@
`default_nettype none
module Register(
input clk,
input [15:0] in,
input load,
output [15:0] out
input clk,
input [15:0] in,
input load,
output [15:0] out
);
// Put your code here:
// Put your code here:
Bit BITA(clk, in[0], load, out[0]);
Bit BITB(clk, in[1], load, out[1]);
Bit BITC(clk, in[2], load, out[2]);
Bit BITD(clk, in[3], load, out[3]);
Bit BITE(clk, in[4], load, out[4]);
Bit BITF(clk, in[5], load, out[5]);
Bit BITG(clk, in[6], load, out[6]);
Bit BITH(clk, in[7], load, out[7]);
Bit BITI(clk, in[8], load, out[8]);
Bit BITJ(clk, in[9], load, out[9]);
Bit BITK(clk, in[10], load, out[10]);
Bit BITL(clk, in[11], load, out[11]);
Bit BITM(clk, in[12], load, out[12]);
Bit BITN(clk, in[13], load, out[13]);
Bit BITO(clk, in[14], load, out[14]);
Bit BITP(clk, in[15], load, out[15]);
endmodule