nand2/03_Sequential_Logic/PC.v

32 lines
875 B
Verilog

/**
* A 16-bit counter with load and reset control bits.
* if (reset[t] == 1) out[t+1] = 0
* else if (load[t] == 1) out[t+1] = in[t]
* else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition)
* else out[t+1] = out[t]
*/
`default_nettype none
module PC(
input clk,
input [15:0] in,
input load,
input inc,
input reset,
output [15:0] out
);
// Put your code here:
// wire [15:0] plusone;
// wire [15:0] incstep;
// wire [15:0] loadstep;
// wire [15:0] resetstep;
// Inc16 INC16(out, plusone);
// Mux16 MUX16A(out, plusone, inc, incstep);
// Mux16 MUX16B(incstep, in, load, loadstep);
// Mux16 MUX16C(loadstep, 16'b0, reset, resetstep);
wire [15:0] select;
assign select = reset? 0 : (load? in : (inc? out+1 : out));
Register REG(clk, select, 1'b1, out);
endmodule