nand2/03_Sequential_Logic/RAM3840.v

49 lines
1.2 KiB
Verilog

/**
* RAM3840 implements 3840 Bytes of RAM addressed from 0 - 3839
* out = M[address]
* if (load =i= 1) M[address][t+1] = in[t]
*/
`default_nettype none
module RAM3840(
input clk,
input [11:0] address,
input [15:0] in,
input load,
output [15:0] out
);
// Put your code here:
wire load0;
wire load1;
wire load2;
wire load3;
wire load4;
wire load5;
wire load6;
wire load7;
wire [15:0] ram0;
wire [15:0] ram1;
wire [15:0] ram2;
wire [15:0] ram3;
wire [15:0] ram4;
wire [15:0] ram5;
wire [15:0] ram6;
wire [15:0] ram7;
DMux8Way DMUX(load, address[11:9],
load0, load1, load2, load3, load4, load5, load6, load7);
RAM512 RAM0(clk, address[8:0], in, load0, ram0);
RAM512 RAM1(clk, address[8:0], in, load1, ram1);
RAM512 RAM2(clk, address[8:0], in, load2, ram2);
RAM512 RAM3(clk, address[8:0], in, load3, ram3);
RAM512 RAM4(clk, address[8:0], in, load4, ram4);
RAM512 RAM5(clk, address[8:0], in, load5, ram5);
RAM512 RAM6(clk, address[8:0], in, load6, ram6);
RAM256 RAM7(clk, address[7:0], in, load7, ram7);
Mux8Way16 MUX(ram0, ram1, ram2, ram3, ram4, ram5, ram6, ram7,
address[11:9], out);
endmodule