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added v2.0

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This commit is contained in:
Michael Schröder
2023-01-11 11:13:09 +01:00
parent 2a5a64ca91
commit 971b323822
584 changed files with 159319 additions and 0 deletions
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17
07_Operating_System/00_HACK/And.v Normal file
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/**
* And gate:
* out = 1 if (a == 1 and b == 1)
* 0 otherwise
*/
`default_nettype none
module And(
input a,
input b,
output out
);
// Put your code here:
and(out,a,b);
endmodule

19
07_Operating_System/00_HACK/Bit.v Normal file
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/**
* 1-bit register:
* If load[t] == 1 then out[t+1] = in[t]
* else out does not change (out[t+1] = out[t])
*/
`default_nettype none
module Bit(
input clk,
input in,
input load,
output out
);
reg out = 0;
always @(posedge clk)
out <= load?in:out;
endmodule

22
07_Operating_System/00_HACK/BitShift8L.v Normal file
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/**
* 8-bit Shiftregister (shifts to left)
* if (load == 1) out[t+1] = in[t]
* else if (shift == 1) out[t+1] = out[t]<<1 | inLSB
* (shift one position to left and insert inLSB as least significant bit)
*/
`default_nettype none
module BitShift8L(
input clk,
input [7:0] in,
input inLSB,
input load,
input shift,
output [7:0] out
);
reg [7:0] out=0;
always @(posedge clk)
out <= load?in:(shift?{out[6:0],inLSB}:out);
endmodule

22
07_Operating_System/00_HACK/BitShift9R.v Normal file
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/**
* 10 bit Shiftregister (shifts to right)
* if (load == 1) out[t+1] = in[t]
* else if (shift == 1) out[t+1] = out[t]>>1 | (inMSB<<9)
* (shift one position to right and insert inMSB as most significant bit)
*/
`default_nettype none
module BitShift9R(
input clk,
input [8:0] in,
input inMSB,
input load,
input shift,
output [8:0] out
);
reg [8:0] out = 0;
always @(posedge clk)
out <= load?in:(shift?{inMSB,out[8:1]}:out);
endmodule

14
07_Operating_System/00_HACK/Buffer.v Normal file
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/**
* Buffer:
* out = in
*/
`default_nettype none
module Buffer(
input in,
output out
);
assign out = in;
endmodule

14
07_Operating_System/00_HACK/Buffer16.v Normal file
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/**
* 16-bit bitwise Buffer:
* for i = 0..15: out[i] = in[i]
*/
`default_nettype none
module Buffer16(
input [15:0] in,
output [15:0] out
);
assign out = in;
endmodule

37
07_Operating_System/00_HACK/CPU.v Normal file
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`default_nettype none
module CPU(
input clk,
input [15:0] inM,
input [15:0] instruction,
input reset,
output [15:0] outM,
output writeM,
output [15:0] addressM,
output [15:0] pc
);
// Compare
reg [15:0] addressM=0;
reg [15:0] regD=0;
reg [15:0] pc=0;
wire [15:0] x,y;
wire zr,ng;
assign x = instruction[10]?(instruction[11]?~0:~regD):(instruction[11]?0:regD);
assign y = instruction[8]?(instruction[9]?~0:~(instruction[12]?inM:addressM)):(instruction[9]?0:(instruction[12]?inM:addressM));
assign outM = instruction[6]?(instruction[7]?~(x+y):~(x&y)):(instruction[7]?(x+y):(x&y));
wire comp;
wire jmp;
assign comp = instruction[15] && instruction[14] && instruction[13];
assign zr = (outM==0);
assign ng = outM[15];
assign jmp = comp && ((ng&&instruction[2])||(zr&&instruction[1])||(~(ng|zr)&&instruction[0]));
always @(posedge clk) begin
addressM <= comp?(instruction[5]?outM:addressM) : instruction;
regD <= comp?(instruction[4]?outM:regD) : regD;
pc <= reset?0 : (jmp?addressM:pc+1);
end
wire writeM;
assign writeM = comp?instruction[3]:0;
endmodule

18
07_Operating_System/00_HACK/Clock25_Reset20.v Normal file
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`default_nettype none
module Clock25_Reset20(
input CLK, // external clock 100 MHz
output clk, // internal clock 25 Mhz
output reset // reset signal
);
// put your code here:
reg [15:0] n=0;
always @(posedge CLK)
n <= n + 1;
assign clk = n[1];
reg resetx=0;
always @(posedge clk)
resetx <= n[11]?1:resetx;
wire reset=~resetx;
endmodule

19
07_Operating_System/00_HACK/Counter.v Normal file
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/**
* A 16-bit counter with reset control bits.
* if (reset[t] == 1) out[t+1] = 0
* else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition)
* else out[t+1] = out[t]
*/
`default_nettype none
module Counter(
input clk,
input inc,
input reset,
output [15:0] out
);
reg [15:0] out=0;
always @(posedge clk)
out <= reset?0:(inc?out+1:out);
endmodule

21
07_Operating_System/00_HACK/DFF.v Normal file
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/**
* Data-Flip-Flop
* out[t+1] = in[t]
*/
`default_nettype none
module DFF(
input clk,
input in,
output out
);
// No need to implement this module
// This module is implemented in verilog using reg-variables
reg out=0;
always @(posedge clk)
if (in) out <= 1'b1;
else out <= 1'b0;
endmodule

18
07_Operating_System/00_HACK/DMux.v Normal file
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/**
* Demultiplexor:
* {a, b} = {in, 0} if sel == 0
* {0, in} if sel == 1
*/
`default_nettype none
module DMux(
input in,
input sel,
output a,
output b
);
assign a = ~sel&in;
assign b = sel&in;
endmodule

32
07_Operating_System/00_HACK/DMux8Way.v Normal file
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/**
* 8-way demultiplexor:
* {a, b, c, d, e, f, g, h} = {in, 0, 0, 0, 0, 0, 0, 0} if sel == 000
* {0, in, 0, 0, 0, 0, 0, 0} if sel == 001
* etc.
* {0, 0, 0, 0, 0, 0, 0, in} if sel == 111
*/
`default_nettype none
module DMux8Way(
input in,
input [2:0] sel,
output a,
output b,
output c,
output d,
output e,
output f,
output g,
output h
);
assign a = (sel==0)?in:0;
assign b = (sel==1)?in:0;
assign c = (sel==2)?in:0;
assign d = (sel==3)?in:0;
assign e = (sel==4)?in:0;
assign f = (sel==5)?in:0;
assign g = (sel==6)?in:0;
assign h = (sel==7)?in:0;
endmodule

52
07_Operating_System/00_HACK/HACK_tb.gtkw Normal file
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[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Mon Dec 19 17:25:20 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris/07_JACK_OS/00_HACK/HACK_tb.vcd"
[dumpfile_mtime] "Mon Dec 19 17:24:51 2022"
[dumpfile_size] 116364543
[savefile] "/home/micha/gitlab/nand2tetris/07_JACK_OS/00_HACK/HACK_tb.gtkw"
[timestart] 0
[size] 1920 963
[pos] 0 40
*-28.000000 353135000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] HACK_tb.
[treeopen] HACK_tb.HACK.
[sst_width] 281
[signals_width] 180
[sst_expanded] 1
[sst_vpaned_height] 259
@200
-GPIO
@28
HACK_tb.HACK.BUT[1:0]
HACK_tb.HACK.LED[1:0]
@200
-UART
@28
HACK_tb.HACK.UART_RX
HACK_tb.HACK.UART_TX
@200
-LCD
@28
HACK_tb.HACK.LCD_CSX
HACK_tb.HACK.LCD_DCX
HACK_tb.HACK.LCD_SDO
HACK_tb.HACK.LCD_SCK
@200
-RTP
@28
HACK_tb.HACK.RTP_SDI
HACK_tb.HACK.RTP_SDO
HACK_tb.HACK.RTP_SCK
@200
-DEBUG
@821
HACK_tb.HACK.outDEBUG0[15:0]
@420
HACK_tb.HACK.outDEBUG1[15:0]
HACK_tb.HACK.outDEBUG2[15:0]
HACK_tb.HACK.outDEBUG3[15:0]
HACK_tb.HACK.outDEBUG4[15:0]
[pattern_trace] 1
[pattern_trace] 0

60
07_Operating_System/00_HACK/HACK_tb.v Normal file
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`timescale 10ns/1ns
`default_nettype none
module HACK_tb();
reg CLK = 0;
reg [1:0] BUT = 3;
wire [1:0] LED;
wire RX,TX;
wire LCD_DCX,LCD_SDO,LCD_SCK,LCD_CSX;
wire RTP_SDI;
wire RTP_SCK,RTP_SDO;
HACK HACK(
.CLK(CLK),
.BUT(BUT),
.LED(LED),
.UART_RX(RX),
.UART_TX(TX),
.LCD_DCX(LCD_DCX),
.LCD_SDO(LCD_SDO),
.LCD_SCK(LCD_SCK),
.LCD_CSX(LCD_CSX),
.RTP_SDO(RTP_SDO),
.RTP_SDI(RTP_SDI),
.RTP_SCK(RTP_SCK)
);
always #0.5 CLK = ~CLK;
//Simulate UART
reg [9:0] uart = 10'b1111111111;
reg [15:0] baudrate = 0;
always @(posedge CLK)
baudrate <= (baudrate==866)?0:baudrate+1;
always @(posedge CLK)
if (baudrate==0) uart <= {1'b1,uart[9:1]};
assign RX = uart[0];
//Simulate RTP
reg [40:0] spi={1'b0,8'd128,8'd10,8'd25,8'd8,8'd22};
assign RTP_SDI = spi[40];
always @(posedge (RTP_SCK))
spi <= {spi[39:0],1'b0};
initial begin
$dumpfile("HACK_tb.vcd");
$dumpvars(0, HACK_tb);
#15000
#30000
#30000 uart = (("R"<<2)|1);
#30000 uart = (("X"<<2)|1);
#30000
#30000 BUT = 1;
#30000
#30000 BUT = 0;
#400000
$finish;
end
endmodule

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07_Operating_System/00_HACK/Hack.dia Normal file
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68
07_Operating_System/00_HACK/Hack.pcf Normal file
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# physical constrain file
# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40HX1K-EVB
# compare to the schematic of the board and the datasheet of fpga
set_io CLK 15 # SYSCLOCK 100 MHz
set_io RST 41 # BUT1
set_io BUT 42 # BUT2
set_io LED[0] 40 # LED1
set_io LED[1] 51 # LED2
set_io UART_RX 36 # PIO2_8/RxD connected to pin 3 of UEXT (PGM)
set_io UART_TX 37 # PIO2_9/TxD connected to pin 4 of UEXT (PGM)
set_io SPI_MOSI 45 # iCE40-SDO
set_io SPI_MISO 46 # iCE40-SDI
set_io SPI_SCK 48 # iCE40-SCK
set_io SPI_CEN 49 # iCE40-SS_B
set_io SRAM_ADDR[0] 79 # SA0
set_io SRAM_ADDR[1] 80 # SA1
set_io SRAM_ADDR[2] 81 # SA2
set_io SRAM_ADDR[3] 82 # SA3
set_io SRAM_ADDR[4] 83 # SA4
set_io SRAM_ADDR[5] 85 # SA5
set_io SRAM_ADDR[6] 86 # SA6
set_io SRAM_ADDR[7] 87 # SA7
set_io SRAM_ADDR[8] 89 # SA8
set_io SRAM_ADDR[9] 90 # SA9
set_io SRAM_ADDR[10] 91 # SA10
set_io SRAM_ADDR[11] 93 # SA11
set_io SRAM_ADDR[12] 94 # SA12
set_io SRAM_ADDR[13] 95 # SA13
set_io SRAM_ADDR[14] 96 # SA14
set_io SRAM_ADDR[15] 97 # SA15
set_io SRAM_ADDR[16] 99 # SA16
set_io SRAM_ADDR[17] 100 # SA17
set_io SRAM_CEN 78 # SRAM_#CS
set_io SRAM_OEN 74 # SRAM_#OE
set_io SRAM_WEN 73 # SRAM_#WE
set_io SRAM_DATA[0] 62 # SD0
set_io SRAM_DATA[1] 63 # SD1
set_io SRAM_DATA[2] 64 # SD2
set_io SRAM_DATA[3] 65 # SD3
set_io SRAM_DATA[4] 66 # SD4
set_io SRAM_DATA[5] 68 # SD5
set_io SRAM_DATA[6] 69 # SD6
set_io SRAM_DATA[7] 71 # SD7
set_io SRAM_DATA[8] 72 # SD8
set_io SRAM_DATA[9] 60 # SD9
set_io SRAM_DATA[10] 59 # SD10
set_io SRAM_DATA[11] 57 # SD11
set_io SRAM_DATA[12] 56 # SD12
set_io SRAM_DATA[13] 54 # SD13
set_io SRAM_DATA[14] 53 # SD14
set_io SRAM_DATA[15] 52 # SD15
set_io LCD_DCN 1 # PIO3_1A connected to pin 5 of GPIO1
set_io LCD_MOSI 2 # PIO3_1B connected to pin 7 of GPIO1
set_io LCD_SCK 3 # PIO3_2A connected to pin 9 of GPIO1
set_io LCD_CEN 4 # PIO3_2B connected to pin 11 of GPIO1
set_io RTP_MISO 7 # PIO3_3A connected to pin 13 of GPIO1
set_io RTP_MOSI 8 # PIO3_3B connected to pin 15 of GPIO1
set_io RTP_SCK 9 # PIO3_5A connected to pin 17 of GPIO1

BIN
07_Operating_System/00_HACK/Hack.png Normal file
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After

Width:  |  Height:  |  Size: 100 KiB

55
07_Operating_System/00_HACK/Hack_tb.gtkw Normal file
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[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Sun Nov 27 17:22:57 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris/07_JACK_OS/00_HACK/Hack_tb.vcd"
[dumpfile_mtime] "Sun Nov 27 17:22:36 2022"
[dumpfile_size] 47620156
[savefile] "/home/micha/gitlab/nand2tetris/07_JACK_OS/00_HACK/Hack_tb.gtkw"
[timestart] 0
[size] 1920 963
[pos] -1 -1
*-28.420643 385300000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] Hack_tb.
[treeopen] Hack_tb.HACK.
[sst_width] 281
[signals_width] 200
[sst_expanded] 1
[sst_vpaned_height] 261
@28
Hack_tb.clk_in
Hack_tb.HACK.clk
@29
Hack_tb.HACK.BUT
@200
-GPIO
@28
Hack_tb.HACK.loadLED
Hack_tb.led[1:0]
@200
-UART
@28
Hack_tb.HACK.loadRX
Hack_tb.HACK.loadTX
Hack_tb.HACK.UART_RX
Hack_tb.HACK.UART_TX
@200
-SPI
@28
Hack_tb.HACK.loadSPI
@22
Hack_tb.spi_cmd[31:0]
Hack_tb.spi[23:0]
@28
Hack_tb.mosi
Hack_tb.miso
Hack_tb.sck
Hack_tb.cen
Hack_tb.HACK.SPI.load
@200
-LCD
@22
Hack_tb.lcd_c[7:0]
Hack_tb.lcd_d[15:0]
[pattern_trace] 1
[pattern_trace] 0

11
07_Operating_System/00_HACK/Include.v Normal file
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`include "../../05_Computer_Architecture/Memory.v"
`include "../../06_IO_Devices/HACK.v"
`include "../../06_IO_Devices/UartTX.v"
`include "../../06_IO_Devices/UartRX.v"
`include "../../06_IO_Devices/SPI.v"
`include "../../06_IO_Devices/SRAM_D.v"
`include "../../06_IO_Devices/GO.v"
`include "../../06_IO_Devices/InOut.v"
`include "../../06_IO_Devices/LCD.v"
`include "../../06_IO_Devices/RTP.v"

17
07_Operating_System/00_HACK/Mux.v Normal file
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/**
* Multiplexor:
* out = a if sel == 0
* b otherwise
*/
`default_nettype none
module Mux(
input a,
input b,
input sel,
output out
);
assign out = sel?b:a;
endmodule

17
07_Operating_System/00_HACK/Mux16.v Normal file
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/**
* 16-bit multiplexor:
* for i = 0..15 out[i] = a[i] if sel == 0
* b[i] if sel == 1
*/
`default_nettype none
module Mux16(
input [15:0] a,
input [15:0] b,
input sel,
output [15:0] out
);
assign out = sel?b:a;
endmodule

32
07_Operating_System/00_HACK/Mux8Way16.v Normal file
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/**
* 16-bit multiplexor:
* for i = 0..15 out[i] = a[i] if sel == 0
* b[i] if sel == 1
*/
`default_nettype none
module Mux8Way16(
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input [15:0] e,
input [15:0] f,
input [15:0] g,
input [15:0] h,
input [2:0] sel,
output reg [15:0] out
);
always @(*) begin
case (sel)
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
4 : out = e;
5 : out = f;
6 : out = g;
7 : out = h;
endcase
end
endmodule

15
07_Operating_System/00_HACK/Not.v Normal file
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/**
* Not gate:
* out = not in
*/
`default_nettype none
module Not(
input in,
output out
);
// Put your code here:
not(out,in);
endmodule

17
07_Operating_System/00_HACK/Or.v Normal file
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/**
* Or gate:
* out = 1 if (a == 1 or b == 1)
* 0 otherwise
*/
`default_nettype none
module Or(
input a,
input b,
output out
);
// Put your code here:
or(out,a,b);
endmodule

14
07_Operating_System/00_HACK/Or8Way.v Normal file
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/**
* 8-way Or:
* out = (in[0] or in[1] or ... or in[7])
*/
`default_nettype none
module Or8Way(
input [7:0] in,
output out
);
// Put your code here:
assign out = |in;
endmodule

22
07_Operating_System/00_HACK/PC.v Normal file
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/**
* A 16-bit counter with load and reset control bits.
* if (reset[t] == 1) out[t+1] = 0
* else if (load[t] == 1) out[t+1] = in[t]
* else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition)
* else out[t+1] = out[t]
*/
`default_nettype none
module PC(
input clk,
input [15:0] in,
input load,
input inc,
input reset,
output [15:0] out
);
reg [15:0] out = 0;
always @(posedge clk)
out <= reset?0:(load?in:(inc?out+1:out));
endmodule

24
07_Operating_System/00_HACK/RAM3840.v Normal file
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/**
* RAM implements 3840 Bytes of RAM addressed from 0000 - 3839
* out = M[address]
* if (load =i= 1) M[address][t+1] = in[t]
*/
`default_nettype none
module RAM3840(
input clk,
input [15:0] address,
input [15:0] in,
input load,
output [15:0] out
);
// No need to implement this chip
// RAM is implemented using BRAM of iCE40
reg [15:0] regRAM [0:3839];
always @(posedge clk)
if (load) regRAM[address[11:0]] <= in;
assign out = regRAM[address[11:0]];
endmodule

26
07_Operating_System/00_HACK/ROM.v Normal file
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/**
* instruction memory at boot time
* The instruction memory is read only (ROM) and
* preloaded with 256 x 16bit of Hackcode holding the bootloader.
*
* instruction = ROM[pc]
*/
`default_nettype none
module ROM(
input [15:0] pc,
output [15:0] instruction
);
// No need to implement this chip
// The file ROM.BIN holds the hack code
parameter ROMFILE = "ROM.hack";
reg [15:0] mem [0:65535];
assign instruction = mem[pc];
initial begin
$readmemb(ROMFILE,mem);
end
endmodule

19
07_Operating_System/00_HACK/Register.v Normal file
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/**
* 16-bit register:
* If load[t] == 1 then out[t+1] = in[t]
* else out does not change
*/
`default_nettype none
module Register(
input clk,
input [15:0] in,
input load,
output [15:0] out
);
reg [15:0] out = 0;
always @(posedge clk)
out <= load?in:out;
initial out = 0;
endmodule

20
07_Operating_System/00_HACK/Switch.v Normal file
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@@ -0,0 +1,20 @@
/**
* One Bit-register, that can be switched on and off
*
* if (out[t] == 0) and (on[t] == 1) out[t+1] = 1
* if (out[t] == 1) and (off[t] == 1) out[t+1] = 0
*/
`default_nettype none
module Switch(
input clk,
input on,
input off,
output out
);
reg out = 0;
always @(posedge clk)
out <= (on&off)?(~out):(on?1:(off?0:(out?1:0)));
endmodule

3
07_Operating_System/00_HACK/apio.ini Normal file
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[env]
board = iCE40-HX1K-EVB