19 lines
366 B
Verilog
19 lines
366 B
Verilog
`default_nettype none
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module Clock25_Reset20(
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input CLK, // external clock 100 MHz
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output clk, // internal clock 25 Mhz
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output reset // reset signal
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);
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// put your code here:
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reg [15:0] n=0;
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always @(posedge CLK)
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n <= n + 1;
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assign clk = n[1];
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reg resetx=0;
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always @(posedge clk)
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resetx <= n[11]?1:resetx;
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wire reset=~resetx;
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endmodule
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