added v2.0

2023-01-11 11:13:09 +01:00
parent 2a5a64ca91
commit 971b323822
584 changed files with 159319 additions and 0 deletions
--- a/03_Sequential_Logic/07_BitShift9R/BitShift10R_tb.gtkw
+++ b/03_Sequential_Logic/07_BitShift9R/BitShift10R_tb.gtkw
@@ -0,0 +1,38 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Mon Nov 28 10:00:33 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/05_BitShift10R/BitShift10R_tb.vcd"
+[dumpfile_mtime] "Mon Nov 28 09:59:44 2022"
+[dumpfile_size] 98425
+[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/05_BitShift10R/BitShift10R_tb.gtkw"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*-5.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 150
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@28
+BitShift10R_tb.clk
+@23
+BitShift10R_tb.in[9:0]
+@28
+BitShift10R_tb.inMSB
+BitShift10R_tb.load
+BitShift10R_tb.shift
+@200
+-OUT
+@22
+BitShift10R_tb.out[9:0]
+@200
+-CMP
+@22
+BitShift10R_tb.out_cmp[9:0]
+@28
+BitShift10R_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0
--- a/03_Sequential_Logic/07_BitShift9R/BitShift9R_tb.gtkw
+++ b/03_Sequential_Logic/07_BitShift9R/BitShift9R_tb.gtkw
@@ -0,0 +1,40 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 17:45:42 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/05_BitShift9R/BitShift9R_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 17:45:34 2022"
+[dumpfile_size] 91711
+[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/05_BitShift9R/BitShift9R_tb.gtkw"
+[timestart] 0
+[size] 1712 730
+[pos] -1 -1
+*-4.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 150
+[sst_expanded] 1
+[sst_vpaned_height] 177
+@200
+-IN
+@28
+BitShift9R_tb.clk
+BitShift9R_tb.inMSB
+@22
+BitShift9R_tb.in[8:0]
+@28
+BitShift9R_tb.shift
+BitShift9R_tb.load
+@200
+-OUT
+@22
+BitShift9R_tb.out[8:0]
+@200
+-CMP
+@22
+BitShift9R_tb.out_cmp[8:0]
+@201
+-Test
+@28
+BitShift9R_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0
--- a/03_Sequential_Logic/07_BitShift9R/BitShift9R_tb.v
+++ b/03_Sequential_Logic/07_BitShift9R/BitShift9R_tb.v
@@ -0,0 +1,61 @@
+`default_nettype none
+module BitShift9R_tb();
+
+	// IN,OUT
+	reg clk=1;
+	reg [8:0] in;
+	reg load,shift,inMSB;
+	wire [8:0] out;
+	
+	// Part
+	BitShift9R BITSHIFT9R(
+		.clk(clk),
+		.in(in),
+		.inMSB(inMSB),
+		.load(load),
+		.shift(shift),
+		.out(out)
+	);
+
+	// Simulate
+	always #1 clk=~clk;
+	always @(posedge clk) begin
+		in <= $random;
+		shift <= (n==0) || ((n>20) && (n<50));
+		inMSB <= $random;	
+		load <= (n==10);
+	end
+	
+	// Compare
+	reg [8:0] out_cmp;
+	always @(posedge clk)
+		out_cmp <= load?in:(shift?(out_cmp>>1)|(inMSB<<8):out_cmp);	
+	
+	reg fail = 0;
+	reg [15:0] n = 0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: clk=%1b, in=%9b, load=%1b, shift=%1b, out=%9b",clk,in,inMSB,load,shift,out);
+				fail=1;
+			end
+	endtask
+	
+	// Test  
+  	initial begin
+  		$dumpfile("BitShift9R_tb.vcd");
+  		$dumpvars(0, BitShift9R_tb);
+		
+		$display("------------------------");
+		$display("Testbench: BitShift9R");
+
+		for (n=0; n<1000;n=n+1) 
+			check();
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule
--- a/03_Sequential_Logic/07_BitShift9R/Include.v
+++ b/03_Sequential_Logic/07_BitShift9R/Include.v
@@ -0,0 +1,31 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+`include "../../01_Boolean_Logic/Mux4Way16.v"
+`include "../../01_Boolean_Logic/Mux8Way16.v"
+`include "../../01_Boolean_Logic/DMux4Way.v"
+`include "../../01_Boolean_Logic/DMux8Way.v"
+
+`include "../../02_Boolean_Arithmetic/HalfAdder.v"
+`include "../../02_Boolean_Arithmetic/FullAdder.v"
+`include "../../02_Boolean_Arithmetic/Add16.v"
+`include "../../02_Boolean_Arithmetic/Inc16.v"
+`include "../../02_Boolean_Arithmetic/ALU.v"
+
+`include "../../03_Sequential_Logic/DFF.v"
+`include "../../03_Sequential_Logic/Bit.v"
+`include "../../03_Sequential_Logic/Register.v"
+`include "../../03_Sequential_Logic/PC.v"
+`include "../../03_Sequential_Logic/BitShift8L.v"
+`include "../../03_Sequential_Logic/BitShift9R.v"
--- a/03_Sequential_Logic/07_BitShift9R/ShifterR_tb.gtkw
+++ b/03_Sequential_Logic/07_BitShift9R/ShifterR_tb.gtkw
@@ -0,0 +1,38 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Nov 24 12:29:38 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/07_ShifterR/ShifterR_tb.vcd"
+[dumpfile_mtime] "Thu Nov 24 12:28:59 2022"
+[dumpfile_size] 67820
+[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/07_ShifterR/ShifterR_tb.gtkw"
+[timestart] 0
+[size] 1920 963
+[pos] -1 -1
+*-3.000000 14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 150
+[sst_expanded] 1
+[sst_vpaned_height] 259
+@28
+ShifterR_tb.clk
+@200
+-IN
+@22
+ShifterR_tb.in[9:0]
+@28
+ShifterR_tb.inMSB
+ShifterR_tb.load
+ShifterR_tb.shift
+@200
+-OUT
+@22
+ShifterR_tb.out[9:0]
+@200
+-CMP
+@23
+ShifterR_tb.out_cmp[9:0]
+@28
+ShifterR_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0
--- a/03_Sequential_Logic/07_BitShift9R/apio.ini
+++ b/03_Sequential_Logic/07_BitShift9R/apio.ini
@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+