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added v2.0

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This commit is contained in:
Michael Schröder
2023-01-11 11:13:09 +01:00
parent 2a5a64ca91
commit 971b323822
584 changed files with 159319 additions and 0 deletions
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36
03_Sequential_Logic/00_DFF/DFF_tb.gtkw Normal file
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[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Thu Dec 22 17:41:19 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/00_DFF/DFF_tb.vcd"
[dumpfile_mtime] "Thu Dec 22 17:41:04 2022"
[dumpfile_size] 23490
[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/00_DFF/DFF_tb.gtkw"
[timestart] 0
[size] 1699 600
[pos] -1 -1
*-2.536562 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 281
[signals_width] 100
[sst_expanded] 1
[sst_vpaned_height] 132
@28
DFF_tb.clk
@200
-IN
@28
DFF_tb.in
@200
-OUT
@28
DFF_tb.out
@200
-CMP
@28
DFF_tb.out_cmp
@201
-Test
@28
DFF_tb.fail
[pattern_trace] 1
[pattern_trace] 0

52
03_Sequential_Logic/00_DFF/DFF_tb.v Normal file
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`default_nettype none
module DFF_tb();
// IN,OUT
reg clk = 1;
reg in;
wire out;
// Part
DFF DFF(
.clk(clk),
.in(in),
.out(out)
);
// Compare
always #1 clk=~clk;
always @(posedge clk)
in <= $random;
reg out_cmp;
always @(posedge clk)
out_cmp <= in;
reg fail = 0;
reg [15:0] n = 0;
task check;
#1
if (out != out_cmp)
begin
$display("FAIL: clk=%1b, in=%1b, out=%1b",clk,in,out);
fail=1;
end
endtask
// Test
initial begin
$dumpfile("DFF_tb.vcd");
$dumpvars(0, DFF_tb);
$display("------------------------");
$display("Testbench: DFF");
for (n=0; n<1000;n=n+1)
check();
if (fail==0) $display("passed");
$display("------------------------");
$finish;
end
endmodule

31
03_Sequential_Logic/00_DFF/Include.v Normal file
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`include "../../01_Boolean_Logic/Nand.v"
`include "../../01_Boolean_Logic/Not.v"
`include "../../01_Boolean_Logic/Buffer.v"
`include "../../01_Boolean_Logic/And.v"
`include "../../01_Boolean_Logic/Or.v"
`include "../../01_Boolean_Logic/Xor.v"
`include "../../01_Boolean_Logic/Mux.v"
`include "../../01_Boolean_Logic/DMux.v"
`include "../../01_Boolean_Logic/Not16.v"
`include "../../01_Boolean_Logic/Buffer16.v"
`include "../../01_Boolean_Logic/And16.v"
`include "../../01_Boolean_Logic/Or16.v"
`include "../../01_Boolean_Logic/Mux16.v"
`include "../../01_Boolean_Logic/Or8Way.v"
`include "../../01_Boolean_Logic/Mux4Way16.v"
`include "../../01_Boolean_Logic/Mux8Way16.v"
`include "../../01_Boolean_Logic/DMux4Way.v"
`include "../../01_Boolean_Logic/DMux8Way.v"
`include "../../02_Boolean_Arithmetic/HalfAdder.v"
`include "../../02_Boolean_Arithmetic/FullAdder.v"
`include "../../02_Boolean_Arithmetic/Add16.v"
`include "../../02_Boolean_Arithmetic/Inc16.v"
`include "../../02_Boolean_Arithmetic/ALU.v"
`include "../../03_Sequential_Logic/DFF.v"
`include "../../03_Sequential_Logic/Bit.v"
`include "../../03_Sequential_Logic/Register.v"
`include "../../03_Sequential_Logic/PC.v"
`include "../../03_Sequential_Logic/BitShift8L.v"
`include "../../03_Sequential_Logic/BitShift9R.v"

3
03_Sequential_Logic/00_DFF/apio.ini Normal file
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[env]
board = iCE40-HX1K-EVB

38
03_Sequential_Logic/01_Bit/Bit_tb.gtkw Normal file
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[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Thu Dec 22 17:43:28 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/01_Bit/Bit_tb.vcd"
[dumpfile_mtime] "Thu Dec 22 17:42:58 2022"
[dumpfile_size] 29689
[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/01_Bit/Bit_tb.gtkw"
[timestart] 0
[size] 1709 600
[pos] -1 -1
*-2.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] Bit_tb.
[sst_width] 281
[signals_width] 100
[sst_expanded] 1
[sst_vpaned_height] 132
@28
Bit_tb.clk
@200
-IN
@28
Bit_tb.in
Bit_tb.load
@200
-OUT
@28
Bit_tb.out
@200
-CMP
@28
Bit_tb.out_cmp
@201
-Test
@28
Bit_tb.fail
[pattern_trace] 1
[pattern_trace] 0

53
03_Sequential_Logic/01_Bit/Bit_tb.v Normal file
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`default_nettype none
module Bit_tb();
// IN,OUT
reg clk = 1;
reg in,load;
wire out;
// Part
Bit BIT(
.clk(clk),
.in(in),
.load(load),
.out(out)
);
// Compare
always #1 clk=~clk;
always @(posedge clk) begin
in <= $random;
load <= $random;
end
reg out_cmp;
always @(posedge clk)
out_cmp <= (load?in:out);
reg fail = 0;
reg [15:0] n = 0;
task check;
#1
if (out != out_cmp)
begin
$display("FAIL: clk=%1b, in=%1b, load=%1b, out=%1b",clk,in,load,out);
fail=1;
end
endtask
initial begin
$dumpfile("Bit_tb.vcd");
$dumpvars(0, Bit_tb);
$display("------------------------");
$display("Testbench: Bit");
for (n=0; n<1000;n=n+1)
check();
if (fail==0) $display("passed");
$display("------------------------");
$finish;
end
endmodule

31
03_Sequential_Logic/01_Bit/Include.v Normal file
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`include "../../01_Boolean_Logic/Nand.v"
`include "../../01_Boolean_Logic/Not.v"
`include "../../01_Boolean_Logic/Buffer.v"
`include "../../01_Boolean_Logic/And.v"
`include "../../01_Boolean_Logic/Or.v"
`include "../../01_Boolean_Logic/Xor.v"
`include "../../01_Boolean_Logic/Mux.v"
`include "../../01_Boolean_Logic/DMux.v"
`include "../../01_Boolean_Logic/Not16.v"
`include "../../01_Boolean_Logic/Buffer16.v"
`include "../../01_Boolean_Logic/And16.v"
`include "../../01_Boolean_Logic/Or16.v"
`include "../../01_Boolean_Logic/Mux16.v"
`include "../../01_Boolean_Logic/Or8Way.v"
`include "../../01_Boolean_Logic/Mux4Way16.v"
`include "../../01_Boolean_Logic/Mux8Way16.v"
`include "../../01_Boolean_Logic/DMux4Way.v"
`include "../../01_Boolean_Logic/DMux8Way.v"
`include "../../02_Boolean_Arithmetic/HalfAdder.v"
`include "../../02_Boolean_Arithmetic/FullAdder.v"
`include "../../02_Boolean_Arithmetic/Add16.v"
`include "../../02_Boolean_Arithmetic/Inc16.v"
`include "../../02_Boolean_Arithmetic/ALU.v"
`include "../../03_Sequential_Logic/DFF.v"
`include "../../03_Sequential_Logic/Bit.v"
`include "../../03_Sequential_Logic/Register.v"
`include "../../03_Sequential_Logic/PC.v"
`include "../../03_Sequential_Logic/BitShift8L.v"
`include "../../03_Sequential_Logic/BitShift9R.v"

3
03_Sequential_Logic/01_Bit/apio.ini Normal file
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@@ -0,0 +1,3 @@
[env]
board = iCE40-HX1K-EVB

31
03_Sequential_Logic/02_Register/Include.v Normal file
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`include "../../01_Boolean_Logic/Nand.v"
`include "../../01_Boolean_Logic/Not.v"
`include "../../01_Boolean_Logic/Buffer.v"
`include "../../01_Boolean_Logic/And.v"
`include "../../01_Boolean_Logic/Or.v"
`include "../../01_Boolean_Logic/Xor.v"
`include "../../01_Boolean_Logic/Mux.v"
`include "../../01_Boolean_Logic/DMux.v"
`include "../../01_Boolean_Logic/Not16.v"
`include "../../01_Boolean_Logic/Buffer16.v"
`include "../../01_Boolean_Logic/And16.v"
`include "../../01_Boolean_Logic/Or16.v"
`include "../../01_Boolean_Logic/Mux16.v"
`include "../../01_Boolean_Logic/Or8Way.v"
`include "../../01_Boolean_Logic/Mux4Way16.v"
`include "../../01_Boolean_Logic/Mux8Way16.v"
`include "../../01_Boolean_Logic/DMux4Way.v"
`include "../../01_Boolean_Logic/DMux8Way.v"
`include "../../02_Boolean_Arithmetic/HalfAdder.v"
`include "../../02_Boolean_Arithmetic/FullAdder.v"
`include "../../02_Boolean_Arithmetic/Add16.v"
`include "../../02_Boolean_Arithmetic/Inc16.v"
`include "../../02_Boolean_Arithmetic/ALU.v"
`include "../../03_Sequential_Logic/DFF.v"
`include "../../03_Sequential_Logic/Bit.v"
`include "../../03_Sequential_Logic/Register.v"
`include "../../03_Sequential_Logic/PC.v"
`include "../../03_Sequential_Logic/BitShift8L.v"
`include "../../03_Sequential_Logic/BitShift9R.v"

38
03_Sequential_Logic/02_Register/Register_tb.gtkw Normal file
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@@ -0,0 +1,38 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Thu Dec 22 17:44:03 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/02_Register/Register_tb.vcd"
[dumpfile_mtime] "Thu Dec 22 17:43:41 2022"
[dumpfile_size] 182432
[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/02_Register/Register_tb.gtkw"
[timestart] 0
[size] 1920 963
[pos] -1 -1
*-1.000000 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 281
[signals_width] 160
[sst_expanded] 1
[sst_vpaned_height] 258
@28
Register_tb.clk
@200
-IN
@22
Register_tb.in[15:0]
@28
Register_tb.load
@200
-OUT
@22
Register_tb.out[15:0]
@200
-CMP
@22
Register_tb.out_cmp[15:0]
@200
-Test
@28
Register_tb.fail
[pattern_trace] 1
[pattern_trace] 0

53
03_Sequential_Logic/02_Register/Register_tb.v Normal file
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@@ -0,0 +1,53 @@
`default_nettype none
module Register_tb();
// IN,OUT
reg clk = 1;
reg [15:0] in;
reg load;
wire [15:0] out;
// Part
Register REGISTER(
.clk(clk),
.in(in),
.load(load),
.out(out)
);
// Compare
always #1 clk=~clk;
always @(posedge clk) begin
in <= $random;
load <= $random;
end
reg [15:0] out_cmp;
always @(posedge clk)
out_cmp <= (load?in:out);
reg fail = 0;
reg [15:0] n = 0;
task check;
#1
if (out != out_cmp)
begin
$display("FAIL: clk=%1b, in=%16b, load=%1b, out=%16b",clk,in,load,out);
fail=1;
end
endtask
initial begin
$dumpfile("Register_tb.vcd");
$dumpvars(0, Register_tb);
$display("------------------------");
$display("Testbench: Register");
for (n=0; n<1000;n=n+1)
check();
if (fail==0) $display("passed");
$display("------------------------");
$finish;
end
endmodule

3
03_Sequential_Logic/02_Register/apio.ini Normal file
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@@ -0,0 +1,3 @@
[env]
board = iCE40-HX1K-EVB

31
03_Sequential_Logic/03_PC/Include.v Normal file
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@@ -0,0 +1,31 @@
`include "../../01_Boolean_Logic/Nand.v"
`include "../../01_Boolean_Logic/Not.v"
`include "../../01_Boolean_Logic/Buffer.v"
`include "../../01_Boolean_Logic/And.v"
`include "../../01_Boolean_Logic/Or.v"
`include "../../01_Boolean_Logic/Xor.v"
`include "../../01_Boolean_Logic/Mux.v"
`include "../../01_Boolean_Logic/DMux.v"
`include "../../01_Boolean_Logic/Not16.v"
`include "../../01_Boolean_Logic/Buffer16.v"
`include "../../01_Boolean_Logic/And16.v"
`include "../../01_Boolean_Logic/Or16.v"
`include "../../01_Boolean_Logic/Mux16.v"
`include "../../01_Boolean_Logic/Or8Way.v"
`include "../../01_Boolean_Logic/Mux4Way16.v"
`include "../../01_Boolean_Logic/Mux8Way16.v"
`include "../../01_Boolean_Logic/DMux4Way.v"
`include "../../01_Boolean_Logic/DMux8Way.v"
`include "../../02_Boolean_Arithmetic/HalfAdder.v"
`include "../../02_Boolean_Arithmetic/FullAdder.v"
`include "../../02_Boolean_Arithmetic/Add16.v"
`include "../../02_Boolean_Arithmetic/Inc16.v"
`include "../../02_Boolean_Arithmetic/ALU.v"
`include "../../03_Sequential_Logic/DFF.v"
`include "../../03_Sequential_Logic/Bit.v"
`include "../../03_Sequential_Logic/Register.v"
`include "../../03_Sequential_Logic/PC.v"
`include "../../03_Sequential_Logic/BitShift8L.v"
`include "../../03_Sequential_Logic/BitShift9R.v"

40
03_Sequential_Logic/03_PC/PC_tb.gtkw Normal file
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@@ -0,0 +1,40 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Thu Dec 22 17:44:56 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.vcd"
[dumpfile_mtime] "Thu Dec 22 17:44:20 2022"
[dumpfile_size] 627445
[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.gtkw"
[timestart] 0
[size] 1920 963
[pos] -1 -1
*-3.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 281
[signals_width] 160
[sst_expanded] 1
[sst_vpaned_height] 258
@28
PC_tb.clk
@200
-IN
@22
PC_tb.in[15:0]
@28
PC_tb.load
PC_tb.inc
PC_tb.reset
@200
-OUT
@22
PC_tb.out[15:0]
@200
-CMP
@22
PC_tb.out_cmp[15:0]
@200
-Test
@29
PC_tb.fail
[pattern_trace] 1
[pattern_trace] 0

60
03_Sequential_Logic/03_PC/PC_tb.v Normal file
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@@ -0,0 +1,60 @@
`default_nettype none
module PC_tb();
// IN,OUT
reg clk=1;
reg [15:0] in;
reg load,inc,reset;
wire [15:0] out;
// Part
PC PC(
.clk(clk),
.in(in),
.load(load),
.inc(inc),
.reset(reset),
.out(out)
);
// Simulate
always #1 clk=~clk;
always @(posedge clk) begin
in <= $random;
reset <= (n==10) || (n==24) || (n==44);
inc <= $random;
load <= $random;
end
// Compare
reg [15:0] out_cmp;
always @(posedge clk)
out_cmp <= (reset?0:(load?in:(inc?out+1:out)));
reg fail = 0;
reg [15:0] n = 0;
task check;
#1
if (out != out_cmp)
begin
$display("FAIL: clk=%1b, in=%16b, load=%1b, inc=%1b, reset=%1b, out=%16b",clk,in,load,inc,reset,out);
fail=1;
end
endtask
initial begin
$dumpfile("PC_tb.vcd");
$dumpvars(0, PC_tb);
$display("------------------------");
$display("Testbench: PC");
for (n=0; n<1000;n=n+1)
check();
if (fail==0) $display("passed");
$display("------------------------");
$finish;
end
endmodule

3
03_Sequential_Logic/03_PC/apio.ini Normal file
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@@ -0,0 +1,3 @@
[env]
board = iCE40-HX1K-EVB

33
03_Sequential_Logic/04_RAM512/Include.v Normal file
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@@ -0,0 +1,33 @@
`include "../../01_Boolean_Logic/Nand.v"
`include "../../01_Boolean_Logic/Not.v"
`include "../../01_Boolean_Logic/Buffer.v"
`include "../../01_Boolean_Logic/And.v"
`include "../../01_Boolean_Logic/Or.v"
`include "../../01_Boolean_Logic/Xor.v"
`include "../../01_Boolean_Logic/Mux.v"
`include "../../01_Boolean_Logic/DMux.v"
`include "../../01_Boolean_Logic/Not16.v"
`include "../../01_Boolean_Logic/Buffer16.v"
`include "../../01_Boolean_Logic/And16.v"
`include "../../01_Boolean_Logic/Or16.v"
`include "../../01_Boolean_Logic/Mux16.v"
`include "../../01_Boolean_Logic/Or8Way.v"
`include "../../01_Boolean_Logic/Mux4Way16.v"
`include "../../01_Boolean_Logic/Mux8Way16.v"
`include "../../01_Boolean_Logic/DMux4Way.v"
`include "../../01_Boolean_Logic/DMux8Way.v"
`include "../../02_Boolean_Arithmetic/HalfAdder.v"
`include "../../02_Boolean_Arithmetic/FullAdder.v"
`include "../../02_Boolean_Arithmetic/Add16.v"
`include "../../02_Boolean_Arithmetic/Inc16.v"
`include "../../02_Boolean_Arithmetic/ALU.v"
`include "../../03_Sequential_Logic/DFF.v"
`include "../../03_Sequential_Logic/Bit.v"
`include "../../03_Sequential_Logic/Register.v"
`include "../../03_Sequential_Logic/PC.v"
`include "../../03_Sequential_Logic/RAM256.v"
`include "../../03_Sequential_Logic/RAM512.v"
`include "../../03_Sequential_Logic/BitShift8L.v"
`include "../../03_Sequential_Logic/BitShift9R.v"

40
03_Sequential_Logic/04_RAM512/PC_tb.gtkw Normal file
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@@ -0,0 +1,40 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Thu Dec 22 17:44:56 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.vcd"
[dumpfile_mtime] "Thu Dec 22 17:44:20 2022"
[dumpfile_size] 627445
[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.gtkw"
[timestart] 0
[size] 1920 963
[pos] -1 -1
*-3.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 281
[signals_width] 160
[sst_expanded] 1
[sst_vpaned_height] 258
@28
PC_tb.clk
@200
-IN
@22
PC_tb.in[15:0]
@28
PC_tb.load
PC_tb.inc
PC_tb.reset
@200
-OUT
@22
PC_tb.out[15:0]
@200
-CMP
@22
PC_tb.out_cmp[15:0]
@200
-Test
@29
PC_tb.fail
[pattern_trace] 1
[pattern_trace] 0

39
03_Sequential_Logic/04_RAM512/RAM512_tb.gtkw Normal file
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@@ -0,0 +1,39 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Sat Dec 31 10:22:59 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/04_RAM512/RAM512_tb.vcd"
[dumpfile_mtime] "Sat Dec 31 10:22:49 2022"
[dumpfile_size] 259286
[savefile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/04_RAM512/RAM512_tb.gtkw"
[timestart] 0
[size] 1700 626
[pos] -1 -1
*-8.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 281
[signals_width] 160
[sst_expanded] 1
[sst_vpaned_height] 142
@200
-IN
@28
RAM512_tb.clk
@22
RAM512_tb.address[8:0]
RAM512_tb.in[15:0]
@28
RAM512_tb.load
@200
-OUT
@22
RAM512_tb.out[15:0]
@200
-CMP
@22
RAM512_tb.out_cmp[15:0]
@200
-Test
@29
RAM512_tb.fail
[pattern_trace] 1
[pattern_trace] 0

60
03_Sequential_Logic/04_RAM512/RAM512_tb.v Normal file
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@@ -0,0 +1,60 @@
`default_nettype none
module RAM512_tb();
// IN,OUT
reg clk=1;
reg [15:0] in;
reg [8:0] address;
reg load;
wire [15:0] out;
// Part
RAM512 RAM512(
.clk(clk),
.address(address),
.in(in),
.load(load),
.out(out)
);
// Simulate
always #1 clk=~clk;
always @(posedge clk) begin
in <= $random;
address <= n;
load <= (n<512);
end
// Compare
reg [15:0] regRAM [0:511];
always @(posedge clk)
if (load) regRAM[address[8:0]] <= in;
wire[15:0] out_cmp = regRAM[address[8:0]];
reg fail = 0;
reg [15:0] n = 0;
task check;
#1
if (out != out_cmp)
begin
$display("FAIL: clk=%1b, address=%9b, in=%16b, load=%1b, out=%16b",clk,address,in,load,out);
fail=1;
end
endtask
initial begin
$dumpfile("RAM512_tb.vcd");
$dumpvars(0, RAM512_tb);
$display("------------------------");
$display("Testbench: RAM512");
for (n=0; n<1000;n=n+1)
check();
if (fail==0) $display("passed");
$display("------------------------");
$finish;
end
endmodule

3
03_Sequential_Logic/04_RAM512/apio.ini Normal file
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@@ -0,0 +1,3 @@
[env]
board = iCE40-HX1K-EVB

34
03_Sequential_Logic/05_RAM3840/Include.v Normal file
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@@ -0,0 +1,34 @@
`include "../../01_Boolean_Logic/Nand.v"
`include "../../01_Boolean_Logic/Not.v"
`include "../../01_Boolean_Logic/Buffer.v"
`include "../../01_Boolean_Logic/And.v"
`include "../../01_Boolean_Logic/Or.v"
`include "../../01_Boolean_Logic/Xor.v"
`include "../../01_Boolean_Logic/Mux.v"
`include "../../01_Boolean_Logic/DMux.v"
`include "../../01_Boolean_Logic/Not16.v"
`include "../../01_Boolean_Logic/Buffer16.v"
`include "../../01_Boolean_Logic/And16.v"
`include "../../01_Boolean_Logic/Or16.v"
`include "../../01_Boolean_Logic/Mux16.v"
`include "../../01_Boolean_Logic/Or8Way.v"
`include "../../01_Boolean_Logic/Mux4Way16.v"
`include "../../01_Boolean_Logic/Mux8Way16.v"
`include "../../01_Boolean_Logic/DMux4Way.v"
`include "../../01_Boolean_Logic/DMux8Way.v"
`include "../../02_Boolean_Arithmetic/HalfAdder.v"
`include "../../02_Boolean_Arithmetic/FullAdder.v"
`include "../../02_Boolean_Arithmetic/Add16.v"
`include "../../02_Boolean_Arithmetic/Inc16.v"
`include "../../02_Boolean_Arithmetic/ALU.v"
`include "../../03_Sequential_Logic/DFF.v"
`include "../../03_Sequential_Logic/Bit.v"
`include "../../03_Sequential_Logic/Register.v"
`include "../../03_Sequential_Logic/PC.v"
`include "../../03_Sequential_Logic/RAM256.v"
`include "../../03_Sequential_Logic/RAM512.v"
`include "../../03_Sequential_Logic/RAM3840.v"
`include "../../03_Sequential_Logic/BitShift8L.v"
`include "../../03_Sequential_Logic/BitShift9R.v"

40
03_Sequential_Logic/05_RAM3840/PC_tb.gtkw Normal file
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@@ -0,0 +1,40 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Thu Dec 22 17:44:56 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.vcd"
[dumpfile_mtime] "Thu Dec 22 17:44:20 2022"
[dumpfile_size] 627445
[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.gtkw"
[timestart] 0
[size] 1920 963
[pos] -1 -1
*-3.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 281
[signals_width] 160
[sst_expanded] 1
[sst_vpaned_height] 258
@28
PC_tb.clk
@200
-IN
@22
PC_tb.in[15:0]
@28
PC_tb.load
PC_tb.inc
PC_tb.reset
@200
-OUT
@22
PC_tb.out[15:0]
@200
-CMP
@22
PC_tb.out_cmp[15:0]
@200
-Test
@29
PC_tb.fail
[pattern_trace] 1
[pattern_trace] 0

40
03_Sequential_Logic/05_RAM3840/RAM3840_tb.gtkw Normal file
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@@ -0,0 +1,40 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Sat Dec 31 11:27:32 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/05_RAM3840/RAM3840_tb.vcd"
[dumpfile_mtime] "Sat Dec 31 11:26:49 2022"
[dumpfile_size] 19516827
[savefile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/05_RAM3840/RAM3840_tb.gtkw"
[timestart] 0
[size] 1616 559
[pos] -1 -1
*-11.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 281
[signals_width] 160
[sst_expanded] 1
[sst_vpaned_height] 117
@28
RAM3840_tb.clk
@200
-IN
@22
RAM3840_tb.address[11:0]
@29
RAM3840_tb.load
@22
RAM3840_tb.in[15:0]
@200
-OUT
@22
RAM3840_tb.out[15:0]
@200
-CMP
@22
RAM3840_tb.out_cmp[15:0]
@200
-Test
@28
RAM3840_tb.fail
[pattern_trace] 1
[pattern_trace] 0

60
03_Sequential_Logic/05_RAM3840/RAM3840_tb.v Normal file
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@@ -0,0 +1,60 @@
`default_nettype none
module RAM3840_tb();
// IN,OUT
reg clk=1;
reg [15:0] in;
reg [11:0] address;
reg load;
wire [15:0] out;
// Part
RAM3840 RAM3840(
.clk(clk),
.address(address),
.in(in),
.load(load),
.out(out)
);
// Simulate
always #1 clk=~clk;
always @(posedge clk) begin
in <= $random;
address <= (n<3840)?n:n-3840;
load <= (n<3840);
end
// Compare
reg [15:0] regRAM [0:3839];
always @(posedge clk)
if (load) regRAM[address[11:0]] <= in;
wire[15:0] out_cmp = regRAM[address[11:0]];
reg fail = 0;
reg [15:0] n = 0;
task check;
#1
if (out != out_cmp)
begin
$display("FAIL: clk=%1b, address=%12b, in=%16b, load=%1b, out=%16b",clk,address,in,load,out);
fail=1;
end
endtask
initial begin
$dumpfile("RAM3840_tb.vcd");
$dumpvars(0, RAM3840_tb);
$display("------------------------");
$display("Testbench: RAM3840");
for (n=0; n<2*3840;n=n+1)
check();
if (fail==0) $display("passed");
$display("------------------------");
$finish;
end
endmodule

3
03_Sequential_Logic/05_RAM3840/apio.ini Normal file
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@@ -0,0 +1,3 @@
[env]
board = iCE40-HX1K-EVB

40
03_Sequential_Logic/06_BitShift8L/BitShift8L_tb.gtkw Normal file
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@@ -0,0 +1,40 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Thu Dec 22 17:45:21 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/04_BitShift8L/BitShift8L_tb.vcd"
[dumpfile_mtime] "Thu Dec 22 17:45:11 2022"
[dumpfile_size] 84704
[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/04_BitShift8L/BitShift8L_tb.gtkw"
[timestart] 0
[size] 1920 963
[pos] -1 -1
*-3.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 281
[signals_width] 150
[sst_expanded] 1
[sst_vpaned_height] 259
@200
-IN
@28
BitShift8L_tb.clk
@22
BitShift8L_tb.in[7:0]
@28
BitShift8L_tb.inLSB
BitShift8L_tb.load
BitShift8L_tb.shift
@200
-OUT
@22
BitShift8L_tb.out[7:0]
@200
-CMP
@22
BitShift8L_tb.out_cmp[7:0]
@201
-Test
@28
BitShift8L_tb.fail
[pattern_trace] 1
[pattern_trace] 0

61
03_Sequential_Logic/06_BitShift8L/BitShift8L_tb.v Normal file
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@@ -0,0 +1,61 @@
`default_nettype none
module BitShift8L_tb();
// IN,OUT
reg clk=1;
reg [7:0] in;
reg load,shift,inLSB;
wire [7:0] out;
// Part
BitShift8L BITSHIFT8L(
.clk(clk),
.in(in),
.inLSB(inLSB),
.load(load),
.shift(shift),
.out(out)
);
// Simulate
always #1 clk=~clk;
always @(posedge clk) begin
in <= $random;
shift <= (n==0) || ((n>20) && (n<50));
inLSB <= $random;
load <= (n==10);
end
// Compare
reg [7:0] out_cmp;
always @(posedge clk)
out_cmp <= load?in:(shift?(out_cmp<<1)|inLSB:out_cmp);
reg fail = 0;
reg [15:0] n = 0;
task check;
#1
if (out != out_cmp)
begin
$display("FAIL: clk=%1b, in=%8b, load=%1b, shift=%1b, out=%8b",clk,in,inLSB,load,shift,out);
fail=1;
end
endtask
// Test
initial begin
$dumpfile("BitShift8L_tb.vcd");
$dumpvars(0, BitShift8L_tb);
$display("------------------------");
$display("Testbench: BitShift8L");
for (n=0; n<1000;n=n+1)
check();
if (fail==0) $display("passed");
$display("------------------------");
$finish;
end
endmodule

31
03_Sequential_Logic/06_BitShift8L/Include.v Normal file
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@@ -0,0 +1,31 @@
`include "../../01_Boolean_Logic/Nand.v"
`include "../../01_Boolean_Logic/Not.v"
`include "../../01_Boolean_Logic/Buffer.v"
`include "../../01_Boolean_Logic/And.v"
`include "../../01_Boolean_Logic/Or.v"
`include "../../01_Boolean_Logic/Xor.v"
`include "../../01_Boolean_Logic/Mux.v"
`include "../../01_Boolean_Logic/DMux.v"
`include "../../01_Boolean_Logic/Not16.v"
`include "../../01_Boolean_Logic/Buffer16.v"
`include "../../01_Boolean_Logic/And16.v"
`include "../../01_Boolean_Logic/Or16.v"
`include "../../01_Boolean_Logic/Mux16.v"
`include "../../01_Boolean_Logic/Or8Way.v"
`include "../../01_Boolean_Logic/Mux4Way16.v"
`include "../../01_Boolean_Logic/Mux8Way16.v"
`include "../../01_Boolean_Logic/DMux4Way.v"
`include "../../01_Boolean_Logic/DMux8Way.v"
`include "../../02_Boolean_Arithmetic/HalfAdder.v"
`include "../../02_Boolean_Arithmetic/FullAdder.v"
`include "../../02_Boolean_Arithmetic/Add16.v"
`include "../../02_Boolean_Arithmetic/Inc16.v"
`include "../../02_Boolean_Arithmetic/ALU.v"
`include "../../03_Sequential_Logic/DFF.v"
`include "../../03_Sequential_Logic/Bit.v"
`include "../../03_Sequential_Logic/Register.v"
`include "../../03_Sequential_Logic/PC.v"
`include "../../03_Sequential_Logic/BitShift8L.v"
`include "../../03_Sequential_Logic/BitShift9R.v"

3
03_Sequential_Logic/06_BitShift8L/apio.ini Normal file
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@@ -0,0 +1,3 @@
[env]
board = iCE40-HX1K-EVB

38
03_Sequential_Logic/07_BitShift9R/BitShift10R_tb.gtkw Normal file
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@@ -0,0 +1,38 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Mon Nov 28 10:00:33 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/05_BitShift10R/BitShift10R_tb.vcd"
[dumpfile_mtime] "Mon Nov 28 09:59:44 2022"
[dumpfile_size] 98425
[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/05_BitShift10R/BitShift10R_tb.gtkw"
[timestart] 0
[size] 1000 600
[pos] -1 -1
*-5.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 281
[signals_width] 150
[sst_expanded] 1
[sst_vpaned_height] 132
@200
-IN
@28
BitShift10R_tb.clk
@23
BitShift10R_tb.in[9:0]
@28
BitShift10R_tb.inMSB
BitShift10R_tb.load
BitShift10R_tb.shift
@200
-OUT
@22
BitShift10R_tb.out[9:0]
@200
-CMP
@22
BitShift10R_tb.out_cmp[9:0]
@28
BitShift10R_tb.fail
[pattern_trace] 1
[pattern_trace] 0

40
03_Sequential_Logic/07_BitShift9R/BitShift9R_tb.gtkw Normal file
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@@ -0,0 +1,40 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Thu Dec 22 17:45:42 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/05_BitShift9R/BitShift9R_tb.vcd"
[dumpfile_mtime] "Thu Dec 22 17:45:34 2022"
[dumpfile_size] 91711
[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/05_BitShift9R/BitShift9R_tb.gtkw"
[timestart] 0
[size] 1712 730
[pos] -1 -1
*-4.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 281
[signals_width] 150
[sst_expanded] 1
[sst_vpaned_height] 177
@200
-IN
@28
BitShift9R_tb.clk
BitShift9R_tb.inMSB
@22
BitShift9R_tb.in[8:0]
@28
BitShift9R_tb.shift
BitShift9R_tb.load
@200
-OUT
@22
BitShift9R_tb.out[8:0]
@200
-CMP
@22
BitShift9R_tb.out_cmp[8:0]
@201
-Test
@28
BitShift9R_tb.fail
[pattern_trace] 1
[pattern_trace] 0

61
03_Sequential_Logic/07_BitShift9R/BitShift9R_tb.v Normal file
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@@ -0,0 +1,61 @@
`default_nettype none
module BitShift9R_tb();
// IN,OUT
reg clk=1;
reg [8:0] in;
reg load,shift,inMSB;
wire [8:0] out;
// Part
BitShift9R BITSHIFT9R(
.clk(clk),
.in(in),
.inMSB(inMSB),
.load(load),
.shift(shift),
.out(out)
);
// Simulate
always #1 clk=~clk;
always @(posedge clk) begin
in <= $random;
shift <= (n==0) || ((n>20) && (n<50));
inMSB <= $random;
load <= (n==10);
end
// Compare
reg [8:0] out_cmp;
always @(posedge clk)
out_cmp <= load?in:(shift?(out_cmp>>1)|(inMSB<<8):out_cmp);
reg fail = 0;
reg [15:0] n = 0;
task check;
#1
if (out != out_cmp)
begin
$display("FAIL: clk=%1b, in=%9b, load=%1b, shift=%1b, out=%9b",clk,in,inMSB,load,shift,out);
fail=1;
end
endtask
// Test
initial begin
$dumpfile("BitShift9R_tb.vcd");
$dumpvars(0, BitShift9R_tb);
$display("------------------------");
$display("Testbench: BitShift9R");
for (n=0; n<1000;n=n+1)
check();
if (fail==0) $display("passed");
$display("------------------------");
$finish;
end
endmodule

31
03_Sequential_Logic/07_BitShift9R/Include.v Normal file
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@@ -0,0 +1,31 @@
`include "../../01_Boolean_Logic/Nand.v"
`include "../../01_Boolean_Logic/Not.v"
`include "../../01_Boolean_Logic/Buffer.v"
`include "../../01_Boolean_Logic/And.v"
`include "../../01_Boolean_Logic/Or.v"
`include "../../01_Boolean_Logic/Xor.v"
`include "../../01_Boolean_Logic/Mux.v"
`include "../../01_Boolean_Logic/DMux.v"
`include "../../01_Boolean_Logic/Not16.v"
`include "../../01_Boolean_Logic/Buffer16.v"
`include "../../01_Boolean_Logic/And16.v"
`include "../../01_Boolean_Logic/Or16.v"
`include "../../01_Boolean_Logic/Mux16.v"
`include "../../01_Boolean_Logic/Or8Way.v"
`include "../../01_Boolean_Logic/Mux4Way16.v"
`include "../../01_Boolean_Logic/Mux8Way16.v"
`include "../../01_Boolean_Logic/DMux4Way.v"
`include "../../01_Boolean_Logic/DMux8Way.v"
`include "../../02_Boolean_Arithmetic/HalfAdder.v"
`include "../../02_Boolean_Arithmetic/FullAdder.v"
`include "../../02_Boolean_Arithmetic/Add16.v"
`include "../../02_Boolean_Arithmetic/Inc16.v"
`include "../../02_Boolean_Arithmetic/ALU.v"
`include "../../03_Sequential_Logic/DFF.v"
`include "../../03_Sequential_Logic/Bit.v"
`include "../../03_Sequential_Logic/Register.v"
`include "../../03_Sequential_Logic/PC.v"
`include "../../03_Sequential_Logic/BitShift8L.v"
`include "../../03_Sequential_Logic/BitShift9R.v"

38
03_Sequential_Logic/07_BitShift9R/ShifterR_tb.gtkw Normal file
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@@ -0,0 +1,38 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Thu Nov 24 12:29:38 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/07_ShifterR/ShifterR_tb.vcd"
[dumpfile_mtime] "Thu Nov 24 12:28:59 2022"
[dumpfile_size] 67820
[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/07_ShifterR/ShifterR_tb.gtkw"
[timestart] 0
[size] 1920 963
[pos] -1 -1
*-3.000000 14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 281
[signals_width] 150
[sst_expanded] 1
[sst_vpaned_height] 259
@28
ShifterR_tb.clk
@200
-IN
@22
ShifterR_tb.in[9:0]
@28
ShifterR_tb.inMSB
ShifterR_tb.load
ShifterR_tb.shift
@200
-OUT
@22
ShifterR_tb.out[9:0]
@200
-CMP
@23
ShifterR_tb.out_cmp[9:0]
@28
ShifterR_tb.fail
[pattern_trace] 1
[pattern_trace] 0

3
03_Sequential_Logic/07_BitShift9R/apio.ini Normal file
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@@ -0,0 +1,3 @@
[env]
board = iCE40-HX1K-EVB

24
03_Sequential_Logic/08_blinky/Include.v Normal file
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@@ -0,0 +1,24 @@
`include "../../01_Boolean_Logic/Nand.v"
`include "../../01_Boolean_Logic/Not.v"
`include "../../01_Boolean_Logic/Buffer.v"
`include "../../01_Boolean_Logic/And.v"
`include "../../01_Boolean_Logic/Or.v"
`include "../../01_Boolean_Logic/Xor.v"
`include "../../01_Boolean_Logic/Mux.v"
`include "../../01_Boolean_Logic/DMux.v"
`include "../../01_Boolean_Logic/Not16.v"
`include "../../01_Boolean_Logic/Buffer16.v"
`include "../../01_Boolean_Logic/And16.v"
`include "../../01_Boolean_Logic/Or16.v"
`include "../../01_Boolean_Logic/Mux16.v"
`include "../../01_Boolean_Logic/Or8Way.v"
`include "../../02_Boolean_Arithmetic/HalfAdder.v"
`include "../../02_Boolean_Arithmetic/FullAdder.v"
`include "../../02_Boolean_Arithmetic/Add16.v"
`include "../../02_Boolean_Arithmetic/Inc16.v"
`include "../../03_Sequential_Logic/DFF.v"
`include "../../03_Sequential_Logic/Bit.v"
`include "../../03_Sequential_Logic/Register.v"
`include "../../03_Sequential_Logic/PC.v"

3
03_Sequential_Logic/08_blinky/apio.ini Normal file
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@@ -0,0 +1,3 @@
[env]
board = iCE40-HX1K-EVB

19
03_Sequential_Logic/08_blinky/blinky.v Normal file
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@@ -0,0 +1,19 @@
// Test to run on fpga with 100 MHz
`default_nettype none
module blinky(
input CLK,
output [1:0] LED
);
wire [15:0] prescaler;
wire clk;
PC PRESCALER(.clk(CLK),.load(1'b0),.in(16'b0),.reset(1'b0),.inc(1'b1),.out(prescaler));
Buffer CLOCK(.in(prescaler[12]),.out(clk));
wire [15:0] counter;
PC COUNTER(.clk(clk),.load(1'b0),.in(16'b0),.reset(1'b0),.inc(1'b1),.out(counter));
Buffer BUF1(.in(counter[15]),.out(LED[1]));
Buffer BUF2(.in(counter[14]),.out(LED[0]));
endmodule

26
03_Sequential_Logic/08_blinky/blinky_tb.gtkw Normal file
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@@ -0,0 +1,26 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Fri Dec 30 09:21:12 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/06_Blinky/blinky_tb.vcd"
[dumpfile_mtime] "Fri Dec 30 09:19:51 2022"
[dumpfile_size] 30570990
[savefile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/06_Blinky/blinky_tb.gtkw"
[timestart] 0
[size] 1746 387
[pos] 46 72
*-2.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] blinky_tb.
[sst_width] 281
[signals_width] 180
[sst_expanded] 1
[sst_vpaned_height] 58
@28
blinky_tb.CLK
@22
blinky_tb.blinky.prescaler[15:0]
blinky_tb.blinky.counter[15:0]
@29
blinky_tb.LED[1:0]
[pattern_trace] 1
[pattern_trace] 0

24
03_Sequential_Logic/08_blinky/blinky_tb.v Normal file
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@@ -0,0 +1,24 @@
`default_nettype none
module blinky_tb();
// IN,OUT
reg CLK=1;
wire[1:0] LED;
// Part
blinky blinky(
.CLK(CLK),
.LED(LED)
);
// Simulate
always #1 CLK=~CLK;
initial begin
$dumpfile("blinky_tb.vcd");
$dumpvars(0, blinky_tb);
#100000
$finish;
end
endmodule

BIN
03_Sequential_Logic/08_blinky/counter.png Normal file
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Binary file not shown.
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After

Width:  |  Height:  |  Size: 47 KiB

12
03_Sequential_Logic/08_blinky/iCE40HX1K.pcf Normal file
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@@ -0,0 +1,12 @@
# physical constrain file
# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB
# compare to the schematic of the board and the datasheet of fpga
set_io CLK 15 # CLK (100 Mhz)
set_io BUT[0] 41 # BUT1
set_io BUT[1] 42 # BUT2
set_io LED[0] 40 # LED1
set_io LED[1] 51 # LED2

BIN
03_Sequential_Logic/08_blinky/prescaler.png Normal file
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03_Sequential_Logic/Bit.v Normal file
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/**
* 1-bit register:
* If load[t] == 1 then out[t+1] = in[t]
* else out does not change (out[t+1] = out[t])
*/
`default_nettype none
module Bit(
input clk,
input in,
input load,
output out
);
// Put your code here:
endmodule

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03_Sequential_Logic/BitShift8L.v Normal file
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/**
* 8-bit Shiftregister (shifts to left)
* if (load == 1) out[t+1] = in[t]
* else if (shift == 1) out[t+1] = out[t]<<1 | inLSB
* (shift one position to left and insert inLSB as least significant bit)
*/
`default_nettype none
module BitShift8L(
input clk,
input [7:0] in,
input inLSB,
input load,
input shift,
output [7:0] out
);
// Put your code here:
endmodule

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03_Sequential_Logic/BitShift9R.v Normal file
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/**
* 10 bit Shiftregister (shifts to right)
* if (load == 1) out[t+1] = in[t]
* else if (shift == 1) out[t+1] = out[t]>>1 | (inMSB<<9)
* (shift one position to right and insert inMSB as most significant bit)
*/
`default_nettype none
module BitShift9R(
input clk,
input [8:0] in,
input inMSB,
input load,
input shift,
output [8:0] out
);
// Put your code here:
endmodule

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03_Sequential_Logic/DFF.v Normal file
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/**
* Data-Flip-Flop
* out[t+1] = in[t]
*/
`default_nettype none
module DFF(
input clk,
input in,
output out
);
// No need to implement this chip
// This chip is implemented in verilog using reg-variables
reg out;
always @(posedge clk)
if (in) out <= 1'b1;
else out <= 1'b0;
endmodule

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03_Sequential_Logic/PC.v Normal file
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/**
* A 16-bit counter with load and reset control bits.
* if (reset[t] == 1) out[t+1] = 0
* else if (load[t] == 1) out[t+1] = in[t]
* else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition)
* else out[t+1] = out[t]
*/
`default_nettype none
module PC(
input clk,
input [15:0] in,
input load,
input inc,
input reset,
output [15:0] out
);
// Put your code here:
endmodule

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03_Sequential_Logic/RAM256.v Normal file
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/**
* RAM256 implements 256 Bytes of RAM addressed from 0 - 255
* out = M[address]
* if (load =i= 1) M[address][t+1] = in[t]
*/
`default_nettype none
module RAM256(
input clk,
input [7:0] address,
input [15:0] in,
input load,
output [15:0] out
);
// No need to implement this chip
// RAM is implemented using BRAM of iCE40
reg [15:0] regRAM [0:255];
always @(posedge clk)
if (load) regRAM[address[7:0]] <= in;
assign out = regRAM[address[7:0]];
endmodule

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03_Sequential_Logic/RAM3840.v Normal file
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/**
* RAM3840 implements 3840 Bytes of RAM addressed from 0 - 3839
* out = M[address]
* if (load =i= 1) M[address][t+1] = in[t]
*/
`default_nettype none
module RAM3840(
input clk,
input [11:0] address,
input [15:0] in,
input load,
output [15:0] out
);
// Put your code here:
endmodule

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03_Sequential_Logic/RAM512.v Normal file
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/**
* RAM512 implements 512 Bytes of RAM addressed from 0 - 511
* out = M[address]
* if (load =i= 1) M[address][t+1] = in[t]
*/
`default_nettype none
module RAM512(
input clk,
input [8:0] address,
input [15:0] in,
input load,
output [15:0] out
);
// Put your code here:
endmodule

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03_Sequential_Logic/Readme.md Normal file
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# 03 Sequential Logic
Build sequential chips `Bit` , `Register` and `PC`, that make use of the data flip flop (DFF) to store the state. `DFF` is considered primitive, so it's not necessary to implement it. The memory chips `RAM512` and `RAM3840` are based on the primitive `RAM256`, which uses block ram structures integrated in iCE40HX1K. `BitShift9R` and `BitShift8L` are new chips not explained in the original nand2tetris course. They serve to connect HACK to different IO-Devices, which are connected using a serial protocol, where data is transmitted bitwise.
## blinky
The folder `08_blinky` contains a project to test the counter `PC` in real hardware. Blinky uses counters `PC` to scale down the frequency of 100MHz provided by the clock oscillator on iCE40HX1K-EVB and finally drives the LED1/2.
***
### Project
* Implement the chips `Bit`, `Register`, `PC`, `RAM512`, `RAM3840`, `BitShift9R` and `BitShift8L` using `DFF` as primitive building block.
* Implement the chips `RAM512` and `RAM3840` using `RAM256` as primitive building block.
* for every chip we provide a test bench in the dedicated folder.
```shell
$ cd <test folder>
$ apio clean
$ apio sim
```
* Run blinky in simulation
```
$ cd 06_blinky
$ apio clean
$ apio sim
```
* Zoom in to check the prescaler:
![](08_blinky/prescaler.png)
* Zoom out to check the counter:
![](08_blinky/counter.png)
* Upload the project to iCE40HX1K-EVB end test in real hardware:
```
$ cd 06_blinky
$ apio clean
$ apio upload
```
* Look at LED1/2 and see if they blink.

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03_Sequential_Logic/Register.v Normal file
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/**
* 16-bit register:
* If load[t] == 1 then out[t+1] = in[t]
* else out does not change
*/
`default_nettype none
module Register(
input clk,
input [15:0] in,
input load,
output [15:0] out
);
// Put your code here:
endmodule