added v2.0

2023-01-11 11:13:09 +01:00
parent 2a5a64ca91
commit 971b323822
584 changed files with 159319 additions and 0 deletions
--- a/02_Boolean_Arithmetic/01_HalfAdder/HalfAdder_tb.gtkw
+++ b/02_Boolean_Arithmetic/01_HalfAdder/HalfAdder_tb.gtkw
@@ -0,0 +1,37 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 17:31:37 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/01_HalfAdder/HalfAdder_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 17:31:23 2022"
+[dumpfile_size] 1592
+[savefile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/01_HalfAdder/HalfAdder_tb.gtkw"
+[timestart] 0
+[size] 1329 600
+[pos] -1 -1
+*-0.771027 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 150
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@28
+HalfAdder_tb.a
+HalfAdder_tb.b
+@200
+-OUT
+@28
+HalfAdder_tb.sum
+HalfAdder_tb.carry
+@200
+-CMP
+@28
+(1)HalfAdder_tb.out_cmp[1:0]
+(0)HalfAdder_tb.out_cmp[1:0]
+@200
+-Test
+@28
+HalfAdder_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0
--- a/02_Boolean_Arithmetic/01_HalfAdder/HalfAdder_tb.v
+++ b/02_Boolean_Arithmetic/01_HalfAdder/HalfAdder_tb.v
@@ -0,0 +1,47 @@
+`default_nettype none
+module HalfAdder_tb();
+
+	// IN,OUT
+	reg a,b;
+	wire sum,carry;
+
+	// Part
+	HalfAdder HALFADDER(
+		.a(a),
+		.b(b),
+		.sum(sum),
+		.carry(carry)
+	);
+
+	// Compare
+	wire [1:0] out_cmp;
+	assign out_cmp = a+b;
+	
+	reg fail = 0;
+	task check;
+		#1
+		if ({carry,sum} != out_cmp) 
+			begin
+				$display("FAIL: a=%1b, b=%1b, sum=%1b, carry=%1b",a,b,sum,carry);
+				fail=1;
+			end
+	endtask
+	  
+  	initial begin
+  		$dumpfile("HalfAdder_tb.vcd");
+  		$dumpvars(0, HalfAdder_tb);
+		
+		$display("------------------------");
+		$display("Testbench: HalfAdder");
+		
+		a=0;b=0;check();
+		a=0;b=1;check();
+		a=1;b=0;check();
+		a=1;b=1;check();
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule
--- a/02_Boolean_Arithmetic/01_HalfAdder/Include.v
+++ b/02_Boolean_Arithmetic/01_HalfAdder/Include.v
@@ -0,0 +1,9 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+
+`include "../../02_Boolean_Arithmetic/HalfAdder.v"
+
--- a/02_Boolean_Arithmetic/01_HalfAdder/apio.ini
+++ b/02_Boolean_Arithmetic/01_HalfAdder/apio.ini
@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+
--- a/02_Boolean_Arithmetic/01_HalfAdder/iCE40HX1K.pcf
+++ b/02_Boolean_Arithmetic/01_HalfAdder/iCE40HX1K.pcf
@@ -0,0 +1,10 @@
+# physical constrain file
+# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB
+# compare to the schematic of the board and the datasheet of fpga
+
+set_io BUT1 41	# BUT1
+set_io BUT2 42	# BUT2
+
+set_io LED1 40	# LED1
+set_io LED2 51	# LED2
+
--- a/02_Boolean_Arithmetic/01_HalfAdder/top.v
+++ b/02_Boolean_Arithmetic/01_HalfAdder/top.v
@@ -0,0 +1,11 @@
+`default_nettype none
+module top(
+	input BUT1,
+	input BUT2,
+	output LED1,
+	output LED2
+);
+
+	HalfAdder HA(.a(BUT1),.b(BUT2),.sum(LED1),.carry(LED2));
+	
+endmodule
--- a/02_Boolean_Arithmetic/02_FullAdder/FullAdder_tb.gtkw
+++ b/02_Boolean_Arithmetic/02_FullAdder/FullAdder_tb.gtkw
@@ -0,0 +1,38 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 17:31:12 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/02_FullAdder/FullAdder_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 17:30:26 2022"
+[dumpfile_size] 3773
+[savefile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/02_FullAdder/FullAdder_tb.gtkw"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*-1.619024 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 150
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@28
+FullAdder_tb.a
+FullAdder_tb.b
+FullAdder_tb.c
+@200
+-OUT
+@28
+FullAdder_tb.sum
+FullAdder_tb.carry
+@200
+-CMP
+@28
+(1)FullAdder_tb.out_cmp[1:0]
+(0)FullAdder_tb.out_cmp[1:0]
+@200
+-Test
+@28
+FullAdder_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0
--- a/02_Boolean_Arithmetic/02_FullAdder/FullAdder_tb.v
+++ b/02_Boolean_Arithmetic/02_FullAdder/FullAdder_tb.v
@@ -0,0 +1,52 @@
+`default_nettype none
+module FullAdder_tb();
+
+	// IN,OUT
+	reg a,b,c;
+	wire sum,carry;
+
+	// Part
+	FullAdder FULLADDER(
+		.a(a),
+		.b(b),
+		.c(c),
+		.sum(sum),
+		.carry(carry)
+	);
+
+	// Compare
+	wire [1:0] out_cmp;
+	assign out_cmp = a+b+c;
+
+	reg fail = 0;
+	task check;
+		#1
+		if ({carry,sum} != out_cmp) 
+			begin
+				$display("FAIL: a=%1b, b=%1b, c=%1b, sum=%1b, carry=%1b",a,b,c,sum,carry);
+				fail=1;
+			end
+	endtask
+	  
+  	initial begin
+  		$dumpfile("FullAdder_tb.vcd");
+  		$dumpvars(0, FullAdder_tb);
+		
+		$display("------------------------");
+		$display("Testbench: FullAdder");
+		
+		a=0;b=0;c=0;check();
+		a=0;b=0;c=1;check();
+		a=0;b=1;c=0;check();
+		a=0;b=1;c=1;check();
+		a=1;b=0;c=0;check();
+		a=1;b=0;c=1;check();
+		a=1;b=1;c=0;check();
+		a=1;b=1;c=1;check();
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule
--- a/02_Boolean_Arithmetic/02_FullAdder/Include.v
+++ b/02_Boolean_Arithmetic/02_FullAdder/Include.v
@@ -0,0 +1,24 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+`include "../../01_Boolean_Logic/Mux4Way16.v"
+`include "../../01_Boolean_Logic/Mux8Way16.v"
+`include "../../01_Boolean_Logic/DMux4Way.v"
+`include "../../01_Boolean_Logic/DMux8Way.v"
+
+`include "../../02_Boolean_Arithmetic/HalfAdder.v"
+`include "../../02_Boolean_Arithmetic/FullAdder.v"
+`include "../../02_Boolean_Arithmetic/Add16.v"
+`include "../../02_Boolean_Arithmetic/Inc16.v"
+`include "../../02_Boolean_Arithmetic/ALU.v"
+
--- a/02_Boolean_Arithmetic/02_FullAdder/apio.ini
+++ b/02_Boolean_Arithmetic/02_FullAdder/apio.ini
@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+
--- a/02_Boolean_Arithmetic/03_Add16/Add16_tb.gtkw
+++ b/02_Boolean_Arithmetic/03_Add16/Add16_tb.gtkw
@@ -0,0 +1,35 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 17:32:11 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/03_Add16/Add16_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 17:31:52 2022"
+[dumpfile_size] 678331
+[savefile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/03_Add16/Add16_tb.gtkw"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 160
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@22
+Add16_tb.a[15:0]
+Add16_tb.b[15:0]
+@200
+-OUT
+@22
+Add16_tb.out[15:0]
+@201
+-CMP
+@22
+Add16_tb.out_cmp[15:0]
+@200
+-Test
+@28
+Add16_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0
--- a/02_Boolean_Arithmetic/03_Add16/Add16_tb.v
+++ b/02_Boolean_Arithmetic/03_Add16/Add16_tb.v
@@ -0,0 +1,49 @@
+`default_nettype none
+module Add16_tb();
+
+	// IN,OUT
+	reg [15:0] a,b;
+	wire [15:0] out;
+
+	// Part
+	Add16 ADD16(
+		.a(a),
+		.b(b),
+		.out(out)
+	);
+
+	// Compare
+	wire [15:0] out_cmp;
+	assign out_cmp = a+b;
+
+	reg fail = 0;
+	reg [15:0] n=0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: a=%16b, b=%16b, out=%16b",a,b,out);
+				fail=1;
+			end
+	endtask
+	  
+  	initial begin
+  		$dumpfile("Add16_tb.vcd");
+  		$dumpvars(0, Add16_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Add16");
+		
+		for (n=0; n<1000;n=n+1) 
+			begin
+				a=$random;
+				b=$random;
+				check();
+			end
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule
--- a/02_Boolean_Arithmetic/03_Add16/Include.v
+++ b/02_Boolean_Arithmetic/03_Add16/Include.v
@@ -0,0 +1,24 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+`include "../../01_Boolean_Logic/Mux4Way16.v"
+`include "../../01_Boolean_Logic/Mux8Way16.v"
+`include "../../01_Boolean_Logic/DMux4Way.v"
+`include "../../01_Boolean_Logic/DMux8Way.v"
+
+`include "../../02_Boolean_Arithmetic/HalfAdder.v"
+`include "../../02_Boolean_Arithmetic/FullAdder.v"
+`include "../../02_Boolean_Arithmetic/Add16.v"
+`include "../../02_Boolean_Arithmetic/Inc16.v"
+`include "../../02_Boolean_Arithmetic/ALU.v"
+
--- a/02_Boolean_Arithmetic/03_Add16/apio.ini
+++ b/02_Boolean_Arithmetic/03_Add16/apio.ini
@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+
--- a/02_Boolean_Arithmetic/04_Inc16/Inc16_tb.gtkw
+++ b/02_Boolean_Arithmetic/04_Inc16/Inc16_tb.gtkw
@@ -0,0 +1,34 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 17:32:33 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/04_Inc16/Inc16_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 17:32:19 2022"
+[dumpfile_size] 232467
+[savefile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/04_Inc16/Inc16_tb.gtkw"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 160
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@22
+Inc16_tb.in[15:0]
+@200
+-OUT
+@22
+Inc16_tb.out[15:0]
+@201
+-CMP
+@22
+Inc16_tb.out_cmp[15:0]
+@200
+-Test
+@28
+Inc16_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0
--- a/02_Boolean_Arithmetic/04_Inc16/Inc16_tb.v
+++ b/02_Boolean_Arithmetic/04_Inc16/Inc16_tb.v
@@ -0,0 +1,51 @@
+`default_nettype none
+module Inc16_tb();
+
+	// IN,OUT
+	reg [15:0] in;
+	wire [15:0] out;
+
+	// Part
+	Inc16 INC16(
+		.in(in),
+		.out(out)
+	);
+
+	// Compare
+	wire [15:0] out_cmp;
+	assign out_cmp = in+1;
+	
+	reg fail = 0;
+	reg [15:0] n=0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: in=%16b, out=%16b",in,out);
+				fail=1;
+			end
+	endtask
+	  
+	// Test
+  	initial begin
+  		$dumpfile("Inc16_tb.vcd");
+  		$dumpvars(0, Inc16_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Inc16");
+
+		in=0;check();
+		in=16'b1111111111111111;check();
+		
+		for (n=0; n<1000;n=n+1) 
+			begin
+				in=$random;
+				check();
+			end
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule
--- a/02_Boolean_Arithmetic/04_Inc16/Include.v
+++ b/02_Boolean_Arithmetic/04_Inc16/Include.v
@@ -0,0 +1,24 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+`include "../../01_Boolean_Logic/Mux4Way16.v"
+`include "../../01_Boolean_Logic/Mux8Way16.v"
+`include "../../01_Boolean_Logic/DMux4Way.v"
+`include "../../01_Boolean_Logic/DMux8Way.v"
+
+`include "../../02_Boolean_Arithmetic/HalfAdder.v"
+`include "../../02_Boolean_Arithmetic/FullAdder.v"
+`include "../../02_Boolean_Arithmetic/Add16.v"
+`include "../../02_Boolean_Arithmetic/Inc16.v"
+`include "../../02_Boolean_Arithmetic/ALU.v"
+
--- a/02_Boolean_Arithmetic/04_Inc16/apio.ini
+++ b/02_Boolean_Arithmetic/04_Inc16/apio.ini
@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+
--- a/02_Boolean_Arithmetic/05_ALU/ALU_tb.gtkw
+++ b/02_Boolean_Arithmetic/05_ALU/ALU_tb.gtkw
@@ -0,0 +1,48 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 17:33:08 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/05_ALU/ALU_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 17:32:45 2022"
+[dumpfile_size] 6961131
+[savefile] "/home/micha/gitlab/nand2tetris/02_Boolean_Arithmetic/05_ALU/ALU_tb.gtkw"
+[timestart] 0
+[size] 1920 963
+[pos] -1 -1
+*-1.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 160
+[sst_expanded] 1
+[sst_vpaned_height] 258
+@200
+-IN
+@22
+ALU_tb.x[15:0]
+ALU_tb.y[15:0]
+@28
+ALU_tb.zx
+ALU_tb.nx
+ALU_tb.zy
+ALU_tb.ny
+ALU_tb.f
+ALU_tb.no
+@200
+-OUT
+@22
+ALU_tb.out[15:0]
+@28
+ALU_tb.zr
+ALU_tb.ng
+@200
+-CMP
+@22
+ALU_tb.out_cmp[15:0]
+@28
+ALU_tb.zr_cmp
+ALU_tb.ng_cmp
+@201
+-Test
+@28
+ALU_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0
--- a/02_Boolean_Arithmetic/05_ALU/ALU_tb.v
+++ b/02_Boolean_Arithmetic/05_ALU/ALU_tb.v
@@ -0,0 +1,81 @@
+`default_nettype none
+module ALU_tb();
+
+	// IN,OUT
+	reg [15:0] x,y;
+	reg zx,nx,zy,ny,f,no;
+	wire [15:0] out;
+	wire zr,ng;
+
+	// Part	
+	ALU ALU(
+		.x(x),
+		.y(y),
+		.zx(zx),
+		.nx(nx),
+		.zy(zy),
+		.ny(ny),
+		.f(f),
+		.no(no),
+		.out(out),
+		.zr(zr),
+		.ng(ng)
+	);
+	
+	// Compare
+	wire [15:0] xx,yy,out_cmp;
+	wire zr_cmp,ng_cmp;
+	assign xx = nx?(zx?~0:~x):(zx?0:x);
+	assign yy = ny?(zy?~0:~y):(zy?0:y);
+	assign out_cmp= no?(f?~(xx+yy):~(xx&yy)):(f?(xx+yy):(xx&yy));
+	assign zr_cmp = (out==0);
+	assign ng_cmp = out[15];
+	
+	reg fail = 0;
+	reg [15:0] n = 0;
+	task check;
+		#1
+		if ((out != out_cmp) || (zr != zr_cmp) || (ng != ng_cmp)) 
+			begin
+				$display("FAIL: x=%16b, y=%16b, zx=%1b, nx=%1b, zy=%1b, ny=%1b, f=%1b, no=%1b, out=%16b, zr=%1b, ng=%1b",x,y,zx,nx,zy,ny,f,no,out,zr,ng);
+				fail=1;
+			end
+	endtask
+	  
+  	initial begin
+  		$dumpfile("ALU_tb.vcd");
+  		$dumpvars(0, ALU_tb);
+		
+		$display("------------------------");
+		$display("Testbench: ALU");
+		
+		for (n=0; n<100;n=n+1) 
+			begin
+				x=$random;
+				y=$random;
+				zx=1;nx=0;zy=1;ny=0;f=1;no=0;check();// 0
+				zx=1;nx=1;zy=1;ny=1;f=1;no=1;check();// 1
+				zx=1;nx=1;zy=1;ny=0;f=1;no=0;check();// -1
+				zx=0;nx=0;zy=1;ny=1;f=0;no=0;check();// x
+				zx=1;nx=1;zy=0;ny=0;f=0;no=0;check();// y
+				zx=0;nx=0;zy=1;ny=1;f=0;no=1;check();// !x
+				zx=1;nx=1;zy=0;ny=0;f=0;no=1;check();// !y
+				zx=0;nx=0;zy=1;ny=1;f=1;no=1;check();// -x
+				zx=1;nx=1;zy=0;ny=0;f=1;no=1;check();// -y
+				zx=0;nx=1;zy=1;ny=1;f=1;no=1;check();// x+1
+				zx=1;nx=1;zy=0;ny=1;f=1;no=1;check();// y+1
+				zx=0;nx=0;zy=1;ny=1;f=1;no=0;check();// x-1
+				zx=1;nx=1;zy=0;ny=0;f=1;no=0;check();// y-1
+				zx=0;nx=0;zy=0;ny=0;f=1;no=0;check();// x+y
+				zx=0;nx=1;zy=0;ny=0;f=1;no=1;check();// x-y
+				zx=0;nx=0;zy=0;ny=1;f=1;no=1;check();// y-x
+				zx=0;nx=0;zy=0;ny=0;f=0;no=0;check();// x&y
+				zx=0;nx=1;zy=0;ny=1;f=0;no=1;check();// x|y
+			end
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule
--- a/02_Boolean_Arithmetic/05_ALU/Include.v
+++ b/02_Boolean_Arithmetic/05_ALU/Include.v
@@ -0,0 +1,24 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+`include "../../01_Boolean_Logic/Mux4Way16.v"
+`include "../../01_Boolean_Logic/Mux8Way16.v"
+`include "../../01_Boolean_Logic/DMux4Way.v"
+`include "../../01_Boolean_Logic/DMux8Way.v"
+
+`include "../../02_Boolean_Arithmetic/HalfAdder.v"
+`include "../../02_Boolean_Arithmetic/FullAdder.v"
+`include "../../02_Boolean_Arithmetic/Add16.v"
+`include "../../02_Boolean_Arithmetic/Inc16.v"
+`include "../../02_Boolean_Arithmetic/ALU.v"
+
--- a/02_Boolean_Arithmetic/05_ALU/apio.ini
+++ b/02_Boolean_Arithmetic/05_ALU/apio.ini
@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+
--- a/02_Boolean_Arithmetic/ALU.v
+++ b/02_Boolean_Arithmetic/ALU.v
@@ -0,0 +1,41 @@
+/**
+ * The ALU (Arithmetic Logic Unit).
+ * Computes one of the following functions:
+ * x+y, x-y, y-x, 0, 1, -1, x, y, -x, -y, !x, !y,
+ * x+1, y+1, x-1, y-1, x&y, x|y on two 16-bit inputs, 
+ * according to 6 input bits denoted zx,nx,zy,ny,f,no.
+ * In addition, the ALU computes two 1-bit outputs:
+ * if the ALU output == 0, zr is set to 1; otherwise zr is set to 0;
+ * if the ALU output < 0, ng is set to 1; otherwise ng is set to 0.
+ */
+
+// Implementation: the ALU logic manipulates the x and y inputs
+// and operates on the resulting values, as follows:
+// if (zx == 1) set x = 0        // 16-bit constant
+// if (nx == 1) set x = !x       // bitwise not
+// if (zy == 1) set y = 0        // 16-bit constant
+// if (ny == 1) set y = !y       // bitwise not
+// if (f == 1)  set out = x + y  // integer 2's complement addition
+// if (f == 0)  set out = x & y  // bitwise and
+// if (no == 1) set out = !out   // bitwise not
+// if (out == 0) set zr = 1
+// if (out < 0) set ng = 1
+
+`default_nettype none
+module ALU(
+	input [15:0] x,		// input x (16 bit)
+	input [15:0] y,		// input y (16 bit)
+    input zx, 				// zero the x input?
+    input nx, 				// negate the x input?
+    input zy, 				// zero the y input?
+    input ny, 				// negate the y input?
+    input f,  				// compute out = x + y (if 1) or x & y (if 0)
+    input no, 				// negate the out output?
+    output [15:0] out, 			// 16-bit output
+    output zr, 				// 1 if (out == 0), 0 otherwise
+    output ng 				// 1 if (out < 0),  0 otherwise
+);
+
+	// Put your code here:
+
+endmodule
--- a/02_Boolean_Arithmetic/Add16.v
+++ b/02_Boolean_Arithmetic/Add16.v
@@ -0,0 +1,16 @@
+/**
+ * Adds two 16-bit values.
+ * The most significant carry bit is ignored.
+ * out = a + b (16 bit)
+ */
+
+`default_nettype none
+module Add16(
+	input [15:0] a,
+	input [15:0] b,
+	output [15:0] out
+);
+
+	// Put your code here:
+
+endmodule
--- a/02_Boolean_Arithmetic/FullAdder.v
+++ b/02_Boolean_Arithmetic/FullAdder.v
@@ -0,0 +1,16 @@
+/**
+ * Computes the sum of three bits.
+ */
+
+`default_nettype none
+module FullAdder(
+	input a,		//1-bit input
+	input b,		//1-bit input
+	input c,		//1-bit input
+	output sum,		//Right bit of a + b + c
+	output carry	//Left bit of a + b + c
+);
+
+	// Put your code here:
+
+endmodule
--- a/02_Boolean_Arithmetic/HalfAdder.v
+++ b/02_Boolean_Arithmetic/HalfAdder.v
@@ -0,0 +1,15 @@
+/**
+ * Computes the sum of two bits.
+ */
+
+`default_nettype none
+module HalfAdder(
+	input a,		//1-bit input
+	input b,		//1-bit inpur
+	output sum,	//Right bit of a + b
+	output carry	//Lef bit of a + b
+);
+
+	// Put your code here:
+
+endmodule
--- a/02_Boolean_Arithmetic/Inc16.v
+++ b/02_Boolean_Arithmetic/Inc16.v
@@ -0,0 +1,14 @@
+/**
+ * 16-bit incrementer:
+ * out = in + 1 (arithmetic addition)
+ */
+
+`default_nettype none
+module Inc16(
+	input [15:0] in,
+	output [15:0] out
+);
+
+	// Put your code here:
+
+endmodule
--- a/02_Boolean_Arithmetic/Readme.md
+++ b/02_Boolean_Arithmetic/Readme.md
@@ -0,0 +1,26 @@
+# 02 Arithmetic Logic
+
+Proceed and implement the chips `HalfAdder`, `FullAdder`, `Add16`, `Inc16` and `ALU`.
+
+Keep in mind the following remarks:
+
+* in order to use the chips implemented in project `01_Boolean_Logic`, they must be listed in the file `Include.v`, which can be found in every subfolder.
+
+* you dan use a `Buffer` to split the signal wires. e.g. `ng` signal of ALU can be derived from out[15].
+
+* clear cache every time you edit and change your implementation in the verilog file `<chipname>.v`.
+
+* test your chip implementation with:
+  
+  ```
+  $ cd <XX_chipname>
+  $ apio clean
+  $ apio sim
+  ```
+
+* the chip `HalfAdder` can be uploaded to iCE40HX1K-EVB and tested using BUT1/2 and LED1/2. Keep in mind, that due to pull up resistors at the buttons, the signals appear inverted:
+  
+  | pin    | function                                            |
+  | ------ | --------------------------------------------------- |
+  | LED1/2 | =0 led is off, =1 led is on                         |
+  | BUT1/2 | =0 button is pressed down, =1 button is released up |