17 lines
275 B
Verilog
17 lines
275 B
Verilog
/**
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* Computes the sum of three bits.
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*/
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`default_nettype none
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module FullAdder(
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input a, //1-bit input
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input b, //1-bit input
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input c, //1-bit input
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output sum, //Right bit of a + b + c
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output carry //Left bit of a + b + c
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);
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// Put your code here:
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endmodule
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