add verilog files for project one through five
This commit is contained in:
@@ -1,40 +1,106 @@
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/**
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* The Hack CPU (Central Processing unit), consisting of an ALU,
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* two registers named A and D, and a program counter named PC.
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* The CPU is designed to fetch and execute instructions written in
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* The CPU is designed to fetch and execute instructions written in
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* the Hack machine language. In particular, functions as follows:
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* Executes the inputted instruction according to the Hack machine
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* Executes the inputted instruction according to the Hack machine
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* language specification. The D and A in the language specification
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* refer to CPU-resident registers, while M refers to the external
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* memory location addressed by A, i.e. to Memory[A]. The inM input
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* holds the value of this location. If the current instruction needs
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* to write a value to M, the value is placed in outM, the address
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* of the target location is placed in the addressM output, and the
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* writeM control bit is asserted. (When writeM==0, any value may
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* appear in outM). The outM and writeM outputs are combinational:
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* they are affected instantaneously by the execution of the current
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* instruction. The addressM and pc outputs are clocked: although they
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* are affected by the execution of the current instruction, they commit
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* to their new values only in the next time step. If reset==1 then the
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* CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather
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* than to the address resulting from executing the current instruction.
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* memory location addressed by A, i.e. to Memory[A]. The inM input
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* holds the value of this location. If the current instruction needs
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* to write a value to M, the value is placed in outM, the address
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* of the target location is placed in the addressM output, and the
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* writeM control bit is asserted. (When writeM==0, any value may
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* appear in outM). The outM and writeM outputs are combinational:
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* they are affected instantaneously by the execution of the current
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* instruction. The addressM and pc outputs are clocked: although they
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* are affected by the execution of the current instruction, they commit
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* to their new values only in the next time step. If reset==1 then the
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* CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather
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* than to the address resulting from executing the current instruction.
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*/
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`default_nettype none
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module CPU(
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input clk,
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input [15:0] inM, // M value input (M = contents of RAM[A])
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input [15:0] instruction, // Instruction for execution
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input reset, // Signals whether to re-start the current
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// program (reset==1) or continue executing
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// the current program (reset==0).
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input clk,
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input [15:0] inM, // M value input (M = contents of RAM[A])
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input [15:0] instruction, // Instruction for execution
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input reset, // Signals whether to re-start the current
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// program (reset==1) or continue executing
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// the current program (reset==0).
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output [15:0] outM, // M value output
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output writeM, // Write to M?
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output [15:0] addressM, // Address in data memory (of M) to read
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output [15:0] pc // address of next instruction
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output [15:0] outM, // M value output
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output writeM, // Write to M?
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output [15:0] addressM, // Address in data memory (of M) to read
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output [15:0] pc // address of next instruction
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);
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// Put your code here:
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// Put your code here:
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wire loadA;
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wire loadD;
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wire is_A;
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wire is_C;
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wire zr;
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wire ng;
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wire inc;
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wire load;
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wire jump;
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wire [15:0] toA;
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wire [15:0] toD;
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wire [15:0] toPC;
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wire [15:0] fromA;
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wire [15:0] fromD;
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wire [15:0] fromPC;
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wire [15:0] fromAorM;
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wire [15:0] fromALU;
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reg [15:0] tempM;
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reg [15:0] tempPC;
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assign is_C = instruction[15] & instruction[14] & instruction[13];
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assign is_A = ~is_C;
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assign loadD = is_C & instruction[4];
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assign loadA = (is_C & instruction[5]) || is_A;
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assign fromAorM = instruction[12] ? inM : fromA;
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assign toA = is_A ? instruction : outM;
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// jump if j1 bit set and ng bit set
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// jump if j2 bit set and zr bit set
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// jump if j3 bit set and zr, ng bit not set
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assign jump = is_C
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& ((instruction[2] & ng)
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|| (instruction[1] & zr)
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|| (instruction[0] & ~(zr | ng)));
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assign inc = ~jump;
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assign outM = fromALU;
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//assign toPC = jump? fromA : pc;
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//xxxx xxxx xxxx xxxx
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Register RegA(clk, toA, loadA, fromA);
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Register RegD(clk, fromALU, loadD, fromD);
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PC PC(clk, fromA, jump, inc, reset, pc);
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ALU ALU(
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fromD,
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fromAorM,
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instruction[11],
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instruction[10],
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instruction[9],
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instruction[8],
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instruction[7],
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instruction[6],
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fromALU,
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zr,
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ng
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);
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assign addressM = fromA;
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assign writeM = is_C & instruction[3];
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endmodule
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@@ -4,12 +4,24 @@
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* a reset signal of approx. 20us length
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*/
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`default_nettype none
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module Clock25_Reset20(
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input CLK, // external clock 100 MHz
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output clk, // internal clock 25 Mhz
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output reset // reset signal approx. 20us
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module Clock25_Reset20(
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input CLK, // external clock 100 MHz
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output reg clk, // internal clock 25 Mhz
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output reg reset // reset signal approx. 20us
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);
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// Put your code here:
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// Put your code here:
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reg boot=1;
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reg [3:0] ccount=0;
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reg [12:0] rcount=0;
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always @(posedge CLK) begin
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if (boot == 1) begin
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boot <= (rcount == 4095) ? 0 : 1;
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rcount <= (rcount == 4095) ? 0 : rcount + 1;
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reset <= (rcount >= 2048) ? 0 : 1;
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end
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ccount <= (ccount == 3) ? 0 : ccount + 1;
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clk <= (ccount >= 2) ? 1 : 0;
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end
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endmodule
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@@ -8,12 +8,89 @@
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*/
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`default_nettype none
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module HACK(
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input CLK, // external clock 100 MHz
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input [1:0] BUT, // user button (0 if pressed, 1 if released)
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output [1:0] LED // leds (0 off, 1 on)
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module HACK(
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input CLK, // external clock 100 MHz
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input [1:0] BUT, // user button (0 if pressed, 1 if released)
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output [1:0] LED // leds (0 off, 1 on)
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);
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// Put your code here:
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wire loadRAM;
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wire loadIO0;
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wire loadIO1;
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wire loadIO2;
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wire loadIO3;
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wire loadIO4;
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wire loadIO5;
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wire loadIO6;
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wire loadIO7;
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wire loadIO8;
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wire loadIO9;
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wire loadIOA;
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wire loadIOB;
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wire loadIOC;
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wire loadIOD;
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wire loadIOE;
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wire loadIOF;
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wire [15:0] inRAM;
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wire [15:0] inIO0;
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wire [15:0] inIO1;
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wire [15:0] inIO2=0;
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wire [15:0] inIO3=0;
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wire [15:0] inIO4=0;
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wire [15:0] inIO5=0;
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wire [15:0] inIO6=0;
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wire [15:0] inIO7=0;
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wire [15:0] inIO8=0;
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wire [15:0] inIO9=0;
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wire [15:0] inIOA=0;
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wire [15:0] inIOB;
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wire [15:0] inIOC;
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wire [15:0] inIOD;
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wire [15:0] inIOE;
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wire [15:0] inIOF;
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wire writeM;
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wire [15:0] inM;
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wire [15:0] instruction;
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wire [15:0] outM;
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wire [15:0] addressM;
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wire [15:0] pc;
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wire clk, reset;
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wire [15:0] outDEBUG0;
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wire [15:0] outDEBUG1;
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wire [15:0] outDEBUG2;
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wire loadDEBUG0;
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wire loadDEBUG1;
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wire loadDEBUG2;
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// Put your code here:
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assign LED[1:0] = inIO0[1:0];
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assign outDEBUG0 = inIOB;
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assign outDEBUG1 = inIOC;
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assign outDEBUG2 = inIOD;
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assign loadDEBUG0 = loadIOB;
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assign loadDEBUG1 = loadIOC;
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assign loadDEBUG2 = loadIOD;
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Clock25_Reset20 CLKR(CLK, clk, reset);
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CPU CPU(clk, inM, instruction, reset, outM, writeM, addressM, pc);
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Memory Memory(addressM, writeM, inM, loadRAM,
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loadIO0, loadIO1, loadIO2, loadIO3, loadIO4, loadIO5, loadIO6, loadIO7,
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loadIO8, loadIO9, loadIOA, loadIOB, loadIOC, loadIOD, loadIOE, loadIOF,
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inRAM, inIO0, inIO1, inIO2, inIO3, inIO4, inIO5, inIO6, inIO7,
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inIO8, inIO9, inIOA, inIOB, inIOC, inIOD, inIOE, inIOF);
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ROM ROM(pc, instruction);
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RAM3840 RAM(clk, addressM[11:0], outM, loadRAM, inRAM);
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Register LED12(clk, outM, loadIO0, inIO0);
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Register BUT12(clk, {14'b0, BUT[1:0]}, 1'b1, inIO1);
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Register DEBUG0(clk, outM, loadIOB, inIOB);
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Register DEBUG1(clk, outM, loadIOC, inIOC);
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Register DEBUG2(clk, outM, loadIOD, inIOD);
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Register DEBUG3(clk, outM, loadIOE, inIOE);
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Register DEBUG4(clk, outM, loadIOF, inIOF);
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endmodule
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@@ -1,12 +1,12 @@
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/**
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* The complete address space of the Hack computer's memory,
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* including RAM and memory-mapped I/O.
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* including RAM and memory-mapped I/O.
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* The chip facilitates read and write operations, as follows:
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* Read: out(t) = Memory[address(t)](t)
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* Write: if load(t-1) then Memory[address(t-1)](t) = in(t-1)
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* In words: the chip always outputs the value stored at the memory
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* location specified by address. If load==1, the in value is loaded
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* into the memory location specified by address. This value becomes
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* In words: the chip always outputs the value stored at the memory
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* location specified by address. If load==1, the in value is loaded
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* into the memory location specified by address. This value becomes
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* available through the out output from the next time step onward.
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* Address space rules:
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* RAM 0x0000 - 0x0EFF (3840 words)
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@@ -16,45 +16,80 @@
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`default_nettype none
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module Memory(
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input [15:0] address,
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input load,
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output [15:0] out,
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output loadRAM,
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output loadIO0,
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output loadIO1,
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output loadIO2,
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output loadIO3,
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output loadIO4,
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output loadIO5,
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output loadIO6,
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output loadIO7,
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output loadIO8,
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output loadIO9,
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output loadIOA,
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output loadIOB,
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output loadIOC,
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output loadIOD,
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output loadIOE,
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output loadIOF,
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input [15:0] inRAM,
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input [15:0] inIO0,
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input [15:0] inIO1,
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input [15:0] inIO2,
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input [15:0] inIO3,
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input [15:0] inIO4,
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input [15:0] inIO5,
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input [15:0] inIO6,
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input [15:0] inIO7,
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input [15:0] inIO8,
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input [15:0] inIO9,
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input [15:0] inIOA,
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input [15:0] inIOB,
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input [15:0] inIOC,
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input [15:0] inIOD,
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input [15:0] inIOE,
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input [15:0] inIOF
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input [15:0] address,
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input load,
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output [15:0] out,
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output loadRAM,
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output loadIO0,
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output loadIO1,
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output loadIO2,
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output loadIO3,
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output loadIO4,
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output loadIO5,
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output loadIO6,
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output loadIO7,
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output loadIO8,
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output loadIO9,
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output loadIOA,
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output loadIOB,
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output loadIOC,
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output loadIOD,
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output loadIOE,
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output loadIOF,
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input [15:0] inRAM,
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input [15:0] inIO0,
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input [15:0] inIO1,
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input [15:0] inIO2,
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input [15:0] inIO3,
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input [15:0] inIO4,
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input [15:0] inIO5,
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input [15:0] inIO6,
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input [15:0] inIO7,
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input [15:0] inIO8,
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input [15:0] inIO9,
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input [15:0] inIOA,
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input [15:0] inIOB,
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input [15:0] inIOC,
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input [15:0] inIOD,
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input [15:0] inIOE,
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input [15:0] inIOF
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);
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// Put your code here:
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// Put your code here:
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wire selA;
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wire selB;
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wire loadA;
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wire loadB;
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wire [15:0] outA;
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wire [15:0] outB;
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wire [15:0] outAB;
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DMux DMUX(address[12], address[3], selA, selB);
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And ANDA(selA,load,loadA);
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And ANDB(selB,load,loadB);
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And ANDR(~address[12], load, loadRAM);
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DMux8Way DMUXLOADA(loadA, address[2:0],
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loadIO0, loadIO1, loadIO2, loadIO3,
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loadIO4, loadIO5, loadIO6, loadIO7);
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DMux8Way DMUXLOADB(loadB, address[2:0],
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loadIO8, loadIO9, loadIOA, loadIOB,
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loadIOC, loadIOD, loadIOE, loadIOF);
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Mux8Way16 Mux8Way16A(
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inIO0[15:0], inIO1[15:0], inIO2[15:0], inIO3[15:0],
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inIO4[15:0], inIO5[15:0], inIO6[15:0], inIO7[15:0],
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address[2:0], outA[15:0]
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);
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Mux8Way16 Mux8Way16B(
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inIO8[15:0], inIO9[15:0], inIOA[15:0], inIOB[15:0],
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inIOC[15:0], inIOD[15:0], inIOE[15:0], inIOF[15:0],
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address[2:0], outB[15:0]
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);
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Mux16 MUX16AB(outA[15:0], outB[15:0], address[3], outAB[15:0]);
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Mux16 MUX16ABR(inRAM[15:0], outAB[15:0], address[12], out[15:0]);
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endmodule
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Reference in New Issue
Block a user