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add verilog files for project one through five

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Konarak
2024-10-17 14:36:58 -04:00
parent b16bfcfd43
commit 792efa70cd
37 changed files with 871 additions and 275 deletions
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85
02_Boolean_Arithmetic/ALU.v
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@@ -2,7 +2,7 @@
* The ALU (Arithmetic Logic Unit).
* Computes one of the following functions:
* x+y, x-y, y-x, 0, 1, -1, x, y, -x, -y, !x, !y,
* x+1, y+1, x-1, y-1, x&y, x|y on two 16-bit inputs,
* x+1, y+1, x-1, y-1, x&y, x|y on two 16-bit inputs,
* according to 6 input bits denoted zx,nx,zy,ny,f,no.
* In addition, the ALU computes two 1-bit outputs:
* if the ALU output == 0, zr is set to 1; otherwise zr is set to 0;
@@ -23,19 +23,78 @@
`default_nettype none
module ALU(
input [15:0] x, // input x (16 bit)
input [15:0] y, // input y (16 bit)
input zx, // zero the x input?
input nx, // negate the x input?
input zy, // zero the y input?
input ny, // negate the y input?
input f, // compute out = x + y (if 1) or x & y (if 0)
input no, // negate the out output?
output [15:0] out, // 16-bit output
output zr, // 1 if (out == 0), 0 otherwise
output ng // 1 if (out < 0), 0 otherwise
input [15:0] x, // input x (16 bit)
input [15:0] y, // input y (16 bit)
input zx, // zero the x input?
input nx, // negate the x input?
input zy, // zero the y input?
input ny, // negate the y input?
input f, // compute out = x + y (if 1) or x & y (if 0)
input no, // negate the out output?
output [15:0] out, // 16-bit output
output zr, // 1 if (out == 0), 0 otherwise
output ng // 1 if (out < 0), 0 otherwise
);
// Put your code here:
// Put your code here:
wire [15:0] xa;
wire [15:0] xb;
wire [15:0] xc;
wire [15:0] ya;
wire [15:0] yb;
wire [15:0] yc;
wire [15:0] xandy;
wire [15:0] xplusy;
wire [15:0] xf;
wire [15:0] xn;
wire [7:0] zri;
wire [7:0] zrj;
wire ngr;
wire zrm;
wire zrn;
wire zro;
wire tt;
wire ff;
// Mux16(a=x, b=false, sel=zx, out=xa);
// Not16(in=xa, out=xb);
// Mux16(a=xa, b=xb, sel=nx, out=xc);
Mux16 MUXX1(x, 16'b0, zx, xa);
Not16 NOTX1(xa, xb);
Mux16 MUXX2(xa, xb, nx, xc);
// Mux16(a=y, b=false, sel=zy, out=ya);
// Not16(in=ya, out=yb);
// Mux16(a=ya, b=yb, sel=ny, out=yc);
Mux16 MUXY1(y, 16'b0, zy, ya);
Not16 NOTY1(ya, yb);
Mux16 MUXY2(ya, yb, ny, yc);
// And16(a=xc, b=yc, out=xandy);
// Add16(a=xc, b=yc, out=xplusy);
// Mux16(a=xandy, b=xplusy, sel=f, out=xf);
And16 ANDZ1(xc, yc, xandy);
Add16 ADDZ1(xc, yc, xplusy);
Mux16 MUXZ1(xandy, xplusy, f, xf);
// Not16(in=xf, out=xn);
// Mux16(a=xf, b=xn, sel=no, out=out, out[15]=ngr, out[0..7]=zri, out[8..15]=zrj);
Not16 NOTF1(xf, xn);
Mux16 MUXF1(xf, xn, no, out);
assign ngr = out[15];
assign zri[7:0] = out[7:0];
assign zrj[7:0] = out[15:8];
// Or8Way(in=zri, out=zrm);
// Or8Way(in=zrj, out=zrn);
Or8Way OR8F1(zri, zrm);
Or8Way OR8F2(zrj, zrn);
Or ORF1(zrm, zrn, zro);
Not NOTF2(zro, zr);
Mux MUXF2(1'b0, 1'b1, ngr, ng);
// Or(a=zrm, b=zrn, out=zro);
// Not(in=zro, out=zr);
// Mux(a=false, b=true, sel=ngr, out=ng);
endmodule

40
02_Boolean_Arithmetic/Add16.v
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@@ -6,11 +6,43 @@
`default_nettype none
module Add16(
input [15:0] a,
input [15:0] b,
output [15:0] out
input [15:0] a,
input [15:0] b,
output [15:0] out
);
// Put your code here:
// Put your code here:
wire carry0;
wire carry1;
wire carry2;
wire carry3;
wire carry4;
wire carry5;
wire carry6;
wire carry7;
wire carry8;
wire carry9;
wire carry10;
wire carry11;
wire carry12;
wire carry13;
wire carry14;
wire carry15;
HalfAdder HA0(a[0], b[0], out[0], carry0);
FullAdder FA0(a[1], b[1], carry0, out[1], carry1);
FullAdder FA1(a[2], b[2], carry1, out[2], carry2);
FullAdder FA2(a[3], b[3], carry2, out[3], carry3);
FullAdder FA3(a[4], b[4], carry3, out[4], carry4);
FullAdder FA4(a[5], b[5], carry4, out[5], carry5);
FullAdder FA5(a[6], b[6], carry5, out[6], carry6);
FullAdder FA6(a[7], b[7], carry6, out[7], carry7);
FullAdder FA7(a[8], b[8], carry7, out[8], carry8);
FullAdder FA8(a[9], b[9], carry8, out[9], carry9);
FullAdder FA9(a[10], b[10], carry9, out[10], carry10);
FullAdder FA10(a[11], b[11], carry10, out[11], carry11);
FullAdder FA11(a[12], b[12], carry11, out[12], carry12);
FullAdder FA12(a[13], b[13], carry12, out[13], carry13);
FullAdder FA13(a[14], b[14], carry13, out[14], carry14);
FullAdder FA14(a[15], b[15], carry14, out[15], carry15);
endmodule

18
02_Boolean_Arithmetic/FullAdder.v
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@@ -4,13 +4,19 @@
`default_nettype none
module FullAdder(
input a, //1-bit input
input b, //1-bit input
input c, //1-bit input
output sum, //Right bit of a + b + c
output carry //Left bit of a + b + c
input a, //1-bit input
input b, //1-bit input
input c, //1-bit input
output sum, //Right bit of a + b + c
output carry //Left bit of a + b + c
);
// Put your code here:
// Put your code here:
wire sumi;
wire carryi;
wire carryj;
HalfAdder HA1(a, b, sumi, carryi);
HalfAdder HA2(c, sumi, sum, carryj);
Or OR(carryi, carryj, carry);
endmodule

13
02_Boolean_Arithmetic/HalfAdder.v
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@@ -4,12 +4,13 @@
`default_nettype none
module HalfAdder(
input a, //1-bit input
input b, //1-bit inpur
output sum, //Right bit of a + b
output carry //Lef bit of a + b
input a, //1-bit input
input b, //1-bit inpur
output sum, //Right bit of a + b
output carry //Lef bit of a + b
);
// Put your code here:
// Put your code here:
Xor XOR(a, b, sum);
And AND(a, b, carry);
endmodule

12
02_Boolean_Arithmetic/Inc16.v
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@@ -5,10 +5,14 @@
`default_nettype none
module Inc16(
input [15:0] in,
output [15:0] out
input [15:0] in,
output [15:0] out
);
// Put your code here:
// Put your code here:
wire [15:0] incr;
assign incr[15:0] = 16'b1;
Add16 ADD(in, incr, out);
// or just:
//assign out = in + 1;
endmodule