nand2/02_Boolean_Arithmetic/Add16.v

49 lines
1.4 KiB
Verilog

/**
* Adds two 16-bit values.
* The most significant carry bit is ignored.
* out = a + b (16 bit)
*/
`default_nettype none
module Add16(
input [15:0] a,
input [15:0] b,
output [15:0] out
);
// Put your code here:
wire carry0;
wire carry1;
wire carry2;
wire carry3;
wire carry4;
wire carry5;
wire carry6;
wire carry7;
wire carry8;
wire carry9;
wire carry10;
wire carry11;
wire carry12;
wire carry13;
wire carry14;
wire carry15;
HalfAdder HA0(a[0], b[0], out[0], carry0);
FullAdder FA0(a[1], b[1], carry0, out[1], carry1);
FullAdder FA1(a[2], b[2], carry1, out[2], carry2);
FullAdder FA2(a[3], b[3], carry2, out[3], carry3);
FullAdder FA3(a[4], b[4], carry3, out[4], carry4);
FullAdder FA4(a[5], b[5], carry4, out[5], carry5);
FullAdder FA5(a[6], b[6], carry5, out[6], carry6);
FullAdder FA6(a[7], b[7], carry6, out[7], carry7);
FullAdder FA7(a[8], b[8], carry7, out[8], carry8);
FullAdder FA8(a[9], b[9], carry8, out[9], carry9);
FullAdder FA9(a[10], b[10], carry9, out[10], carry10);
FullAdder FA10(a[11], b[11], carry10, out[11], carry11);
FullAdder FA11(a[12], b[12], carry11, out[12], carry12);
FullAdder FA12(a[13], b[13], carry12, out[13], carry13);
FullAdder FA13(a[14], b[14], carry13, out[14], carry14);
FullAdder FA14(a[15], b[15], carry14, out[15], carry15);
endmodule