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WIP optimizations on SPI/UART

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This commit is contained in:
Konarak 2025-04-25 21:22:29 +05:30
parent 2fdfe24793
commit 3157b5306d
Signed by: konarak
GPG Key ID: DE5E99432B548849
4 changed files with 128 additions and 162 deletions
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10
06_IO_Devices/HACK.v
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@ -134,7 +134,7 @@ module HACK(
Mux16 SWITCHD(ROM_DATA, inIO6, load_sram, instruction); Mux16 SWITCHD(ROM_DATA, inIO6, load_sram, instruction);
Register SRAM_A(clk, outM, loadIO5, inIO5); Register SRAM_A(clk, outM, loadIO5, inIO5);
SRAM_D SRAM_D(clk, loadIO6, outM, inIO6, SRAM_DATA, SRAM_CSX, SRAM_OEX, SRAM_WEX); SRAM_D SRAM_D(clk, loadIO6, outM, inIO6, SRAM_DATA, SRAM_CSX, SRAM_OEX, SRAM_WEX);
LCD LCD(clk, loadIO8, loadIO9, outM, fromLCD, LCD_DCX, LCD_CSX, LCD_SDO, LCD_SCK); //LCD LCD(clk, loadIO8, loadIO9, outM, fromLCD, LCD_DCX, LCD_CSX, LCD_SDO, LCD_SCK);
Register DEBUG0(clk, outM, loadIOB, inIOB); Register DEBUG0(clk, outM, loadIOB, inIOB);
Register DEBUG1(clk, outM, loadIOC, inIOC); Register DEBUG1(clk, outM, loadIOC, inIOC);
@ -150,10 +150,10 @@ module HACK(
//assign SRAM_WEX=0; //assign SRAM_WEX=0;
//assign SRAM_OEX=0; //assign SRAM_OEX=0;
//assign SRAM_CSX=0; //assign SRAM_CSX=0;
//assign LCD_DCX=0; assign LCD_DCX=0;
//assign LCD_SDO=0; assign LCD_SDO=0;
//assign LCD_SCK=0; assign LCD_SCK=0;
//assign LCD_CSX=0; assign LCD_CSX=0;
assign RTP_SDO=0; assign RTP_SDO=0;
assign RTP_SCK=0; assign RTP_SCK=0;
endmodule endmodule

129
06_IO_Devices/SPI.v
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@ -22,103 +22,64 @@ module SPI(
// Put your code here: // Put your code here:
// 1100 0000 0101 1011 // 1100 0000 0101 1011
// 1000 0000 0101 1011 // 1000 0000 0101 1011
reg active=0; reg active;
reg csx_low=0; reg [2:0] bit_index;
reg out_low=1; reg [7:0] shift_out;
reg [7:0] totx; reg [7:0] shift_in;
reg [7:0] torx; reg [4:0] count;
reg [4:0] is16;
wire is_sample_phase = (count >= 1 && count <= 15 && count[0] == 1);
wire is_shift_phase = (count >= 2 && count <= 16 && count[0] == 0);
initial begin
SDO <= 0;
CSX <= 1'b1;
out <= 16'b0;
bit_index <= 3'b0;
end
always @(posedge clk) begin always @(posedge clk) begin
CSX <= (csx_low) ? 0 : 1;
SDO <= 0;
SCK <= 0; SCK <= 0;
out <= (out)? out : 0;
if (load == 1) begin if (load == 1) begin
out_low=0;
out[14:8] <= 0;
out[7:0] <= in[7:0];
if (in[8]==1) begin
out[15] <= 0;
csx_low <= 0;
CSX <= 1; CSX <= 1;
end out <= { 8'b0, in[7:0] };
else if (in[8]==0) begin
out[15] <= 1; if (!in[8]) begin
csx_low <= 1;
CSX <= 0;
active <= 1; active <= 1;
is16 <= 1; count <= 1;
totx[7:0] <= in[7:0]; bit_index <= 7; // byte order MSB->LSB
CSX <= 0;
out[15] <= 1;
shift_out[7:0] <= in[7:0];
SDO <= in[7]; SDO <= in[7];
end end
end end
else if (active==1) begin else if (active==1) begin
SCK <= ~SCK; SCK <= ~SCK;
if (is16 == 16) begin
if (count == 16) begin
SDO <= 0;
out <= {8'b0, shift_in};
active <= 0; active <= 0;
out <= {8'b0, torx[7:0]};
end
else begin
csx_low <= 1;
is16 <= is16 + 1;
case (is16+1)
2 : SDO <= totx[7];
3 : SDO <= totx[6];
4 : SDO <= totx[6];
5 : SDO <= totx[5];
6 : SDO <= totx[5];
7 : SDO <= totx[4];
8 : SDO <= totx[4];
9 : SDO <= totx[3];
10 : SDO <= totx[3];
11 : SDO <= totx[2];
12 : SDO <= totx[2];
13 : SDO <= totx[1];
14 : SDO <= totx[1];
15 : SDO <= totx[0];
16 : SDO <= totx[0];
endcase
case (is16)
1 : torx[7] <= SDI;
3 : torx[6] <= SDI;
5 : torx[5] <= SDI;
7 : torx[4] <= SDI;
9 : torx[3] <= SDI;
11 : torx[2] <= SDI;
13 : torx[1] <= SDI;
15 : torx[0] <= SDI;
endcase
case (is16)
2 : out <= (out<<1);
4 : out <= (out<<1);
6 : out <= (out<<1);
8 : out <= (out<<1);
10 : out <= (out<<1);
12 : out <= (out<<1);
14 : out <= (out<<1);
endcase
case (is16)
2 : out[0] <= torx[7];
4 : out[0] <= torx[6];
6 : out[0] <= torx[5];
8 : out[0] <= torx[4];
10 : out[0] <= torx[3];
12 : out[0] <= torx[2];
14 : out[0] <= torx[1];
endcase
case (is16)
2 : out[15:8] <= 8'b10000000;
4 : out[15:8] <= 8'b10000000;
6 : out[15:8] <= 8'b10000000;
8 : out[15:8] <= 8'b10000000;
10 : out[15:8] <= 8'b10000000;
12 : out[15:8] <= 8'b10000000;
14 : out[15:8] <= 8'b10000000;
endcase
end
end else begin end else begin
out <= out_low? 16'b0 : out; count <= count + 1;
if (is_shift_phase) begin
// bit_index = bit_index - 1
bit_index <= 7 - ((count) >> 1);
out[7:0] <= {out[6:0], shift_in[bit_index]};
shift_out <= {shift_out[6:0], 1'b0};
SDO <= shift_out[6]; // next bit
end
if (is_sample_phase) begin
shift_in[bit_index] <= SDI;
end
end
end end
end end
endmodule endmodule

72
06_IO_Devices/UartRX.v
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@ -7,47 +7,49 @@
* of byte completes, chip ouputs the received byte to out[7:0]] with out[15]=0. * of byte completes, chip ouputs the received byte to out[7:0]] with out[15]=0.
*/ */
`default_nettype none `default_nettype none
module UartRX( module UartRX (
input clk, input wire clk,
input clear, input wire clear,
input RX, input wire RX,
output reg [15:0] out output reg [15:0] out
); );
// Put your code here: reg [7:0] baud_count;
wire clkdRX; reg [3:0] bit_index;
reg active=0; reg [7:0] rx_shift;
reg out_set=0; reg rx_active;
reg [7:0] uart;
reg [3:0] nthbit; initial begin
reg [9:0] is216; out <= 16'b0;
rx_active <= 1'b0;
end
always @(posedge clk) begin always @(posedge clk) begin
out_set <= clear ? 1 : out_set;
out <= clear ? 16'h8000 : (out_set ? out : 16'h0000); out <= (clear | out[15]) ? 16'h8000 : out;
if ((active==0) && (RX == 0)) begin
out_set <=1; if (!rx_active && !RX) begin
active <= 1;
is216 <= 1; // RX Falling edge: Start bit detected
uart <= 0; rx_active <= 1;
nthbit <= 0; rx_shift <= 0;
baud_count <= 1;
bit_index <= 0;
end else if (rx_active) begin
baud_count <= (baud_count == 216) ? 0 : baud_count + 1;
bit_index <= (baud_count == 108) ? bit_index + 1 : bit_index;
if (bit_index >= 1 && bit_index <= 8 && baud_count == 108) begin
rx_shift <= {RX, rx_shift[7:1]};
end end
else if (active==1) begin
is216 <= (is216 == 216) ? 0 : is216 + 1; if (bit_index == 10 && baud_count == 216) begin
nthbit <= (is216 == 108) ? nthbit + 1 : nthbit; rx_active <= 0; // Done receiving 8 bits + stop
case (nthbit) out <= {8'b0, rx_shift};
1 : uart[0] <= RX;
2 : uart[1] <= RX;
3 : uart[2] <= RX;
4 : uart[3] <= RX;
5 : uart[4] <= RX;
6 : uart[5] <= RX;
7 : uart[6] <= RX;
8 : uart[7] <= RX;
endcase
if (nthbit == 10 && is216 == 216) begin
active <= 0;
out <= {8'b0, uart};
end end
end end
end end
endmodule endmodule

73
06_IO_Devices/UartTX.v
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@ -8,47 +8,50 @@
* low again (ready). * low again (ready).
*/ */
`default_nettype none `default_nettype none
module UartTX( module UartTX (
input clk, input wire clk,
input load, input wire load,
input [15:0] in, input wire [15:0] in,
output TX, output wire TX,
output reg [15:0] out output reg [15:0] out
); );
reg uart=1; reg [9:0] baud_count;
reg active=0; reg [3:0] bit_index;
reg [7:0] to_send; reg [9:0] shift_reg;
reg [3:0] nthbit=0; reg tx_active;
reg [9:0] is216;
always @(posedge clk) begin
out <= (load || active) ? 16'h8000 : 16'h0000;
if ((active==0) && (load == 1)) begin initial begin
active <= 1; tx_active <= 1'b0;
is216 <= 1; shift_reg <= 10'b1;
nthbit <= 0;
uart <= 0;
to_send <= in[7:0];
end end
else if (active==1) begin
is216 <= (is216 == 216) ? 0 : is216 + 1;
nthbit <= (is216 == 216) ? nthbit + 1 : nthbit; always @(posedge clk) begin
case (nthbit) // Output status
0 : uart <= 0; out <= (load || tx_active) ? 16'h8000 : 16'h0000;
1 : uart <= to_send[0];
2 : uart <= to_send[1]; if (!tx_active && load) begin
3 : uart <= to_send[2]; // Load start bit + data + stop bit into shift register
4 : uart <= to_send[3]; shift_reg <= {1'b1, in[7:0], 1'b0}; // {stop, data[7:0], start}
5 : uart <= to_send[4]; tx_active <= 1;
6 : uart <= to_send[5]; baud_count <= 0;
7 : uart <= to_send[6]; bit_index <= 0;
8 : uart <= to_send[7]; end else if (tx_active) begin
9 : uart <= 1; if (baud_count == 216) begin
10 : begin active <= 0; out <= 16'h0000; end baud_count <= 0;
endcase bit_index <= bit_index + 1;
shift_reg <= {1'b1, shift_reg[9:1]}; // shift in stop bit after final bit
if (bit_index == 9) begin
tx_active <= 0;
out <= 16'h0000;
end
end else begin
baud_count <= baud_count + 1;
end end
end end
assign TX = uart; end
assign TX = shift_reg[0];
endmodule endmodule