58 lines
1.6 KiB
Verilog
58 lines
1.6 KiB
Verilog
/**
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* UartTX controls transmission of bytes over UART.
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*
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* When load = 1 the chip starts serial transmission of the byte in[7:0] to the
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* TX line according to the protocoll 8N1 with 115200 baud. During transmission
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* out[15] is set to high (busy). The transmission is finished after 2170 clock
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* cycles (10 byte a 217 cycle each). When transmission completes out[15] goes
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* low again (ready).
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*/
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`default_nettype none
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module UartTX (
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input wire clk,
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input wire load,
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input wire [15:0] in,
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output wire TX,
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output reg [15:0] out
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);
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reg [9:0] baud_count;
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reg [3:0] bit_index;
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reg [9:0] shift_reg;
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reg tx_active;
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initial begin
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tx_active <= 1'b0;
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shift_reg <= 10'b1;
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end
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always @(posedge clk) begin
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// Output status
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out <= (load || tx_active) ? 16'h8000 : 16'h0000;
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if (!tx_active && load) begin
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// Load start bit + data + stop bit into shift register
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shift_reg <= {1'b1, in[7:0], 1'b0}; // {stop, data[7:0], start}
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tx_active <= 1;
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baud_count <= 0;
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bit_index <= 0;
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end else if (tx_active) begin
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if (baud_count == 216) begin
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baud_count <= 0;
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bit_index <= bit_index + 1;
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shift_reg <= {1'b1, shift_reg[9:1]}; // shift in stop bit after final bit
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if (bit_index == 9) begin
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tx_active <= 0;
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out <= 16'h0000;
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end
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end else begin
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baud_count <= baud_count + 1;
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end
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end
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end
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assign TX = shift_reg[0];
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endmodule
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