dos2unix old files
This commit is contained in:
@@ -1,20 +1,20 @@
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// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/03/a/Bit.hdl
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/**
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* 1-bit register:
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* If load[t] == 1 then out[t+1] = in[t]
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* else out does not change (out[t+1] = out[t])
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*/
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CHIP Bit {
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IN in, load;
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OUT out;
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PARTS:
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// Put your code here:
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Mux(a=dffout, b=in, sel=load, out=muxout);
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DFF(in=muxout, out=out, out=dffout);
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}
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// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/03/a/Bit.hdl
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/**
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* 1-bit register:
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* If load[t] == 1 then out[t+1] = in[t]
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* else out does not change (out[t+1] = out[t])
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*/
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CHIP Bit {
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IN in, load;
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OUT out;
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PARTS:
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// Put your code here:
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Mux(a=dffout, b=in, sel=load, out=muxout);
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DFF(in=muxout, out=out, out=dffout);
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}
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@@ -1,25 +1,25 @@
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// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/03/a/PC.hdl
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/**
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* A 16-bit counter with load and reset control bits.
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* if (reset[t] == 1) out[t+1] = 0
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* else if (load[t] == 1) out[t+1] = in[t]
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* else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition)
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* else out[t+1] = out[t]
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*/
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CHIP PC {
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IN in[16], load, inc, reset;
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OUT out[16];
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PARTS:
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// Put your code here:
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Inc16(in=registerValue, out=incrementedValue);
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Mux16(a=registerValue, b=incrementedValue, sel=inc, out=incBitStep);
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Mux16(a=incBitStep, b=in, sel=load, out=loadBitStep);
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Mux16(a=loadBitStep, b=false, sel=reset, out=resetBitStep);
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Register(in=resetBitStep, load=true, out=out, out=registerValue);
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}
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// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/03/a/PC.hdl
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/**
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* A 16-bit counter with load and reset control bits.
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* if (reset[t] == 1) out[t+1] = 0
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* else if (load[t] == 1) out[t+1] = in[t]
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* else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition)
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* else out[t+1] = out[t]
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*/
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CHIP PC {
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IN in[16], load, inc, reset;
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OUT out[16];
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PARTS:
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// Put your code here:
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Inc16(in=registerValue, out=incrementedValue);
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Mux16(a=registerValue, b=incrementedValue, sel=inc, out=incBitStep);
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Mux16(a=incBitStep, b=in, sel=load, out=loadBitStep);
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Mux16(a=loadBitStep, b=false, sel=reset, out=resetBitStep);
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Register(in=resetBitStep, load=true, out=out, out=registerValue);
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}
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@@ -1,45 +1,45 @@
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// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/03/a/RAM64.hdl
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/**
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* Memory of 64 registers, each 16 bit-wide. Out holds the value
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* stored at the memory location specified by address. If load==1, then
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* the in value is loaded into the memory location specified by address
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* (the loaded value will be emitted to out from the next time step onward).
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*/
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CHIP RAM64 {
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IN in[16], load, address[6];
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OUT out[16];
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PARTS:
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// Put your code here:
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DMux8Way(in=load, sel=address[3..5], a=toRAM8A,
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b=toRAM8B,
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c=toRAM8C,
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d=toRAM8D,
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e=toRAM8E,
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f=toRAM8F,
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g=toRAM8G,
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h=toRAM8H);
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RAM8(in=in, load=toRAM8A, address=address[0..2], out=fromRAM8A);
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RAM8(in=in, load=toRAM8B, address=address[0..2], out=fromRAM8B);
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RAM8(in=in, load=toRAM8C, address=address[0..2], out=fromRAM8C);
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RAM8(in=in, load=toRAM8D, address=address[0..2], out=fromRAM8D);
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RAM8(in=in, load=toRAM8E, address=address[0..2], out=fromRAM8E);
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RAM8(in=in, load=toRAM8F, address=address[0..2], out=fromRAM8F);
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RAM8(in=in, load=toRAM8G, address=address[0..2], out=fromRAM8G);
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RAM8(in=in, load=toRAM8H, address=address[0..2], out=fromRAM8H);
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Mux8Way16(sel=address[3..5], out=out, a=fromRAM8A,
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b=fromRAM8B,
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c=fromRAM8C,
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d=fromRAM8D,
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e=fromRAM8E,
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f=fromRAM8F,
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g=fromRAM8G,
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h=fromRAM8H);
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}
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// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/03/a/RAM64.hdl
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/**
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* Memory of 64 registers, each 16 bit-wide. Out holds the value
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* stored at the memory location specified by address. If load==1, then
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* the in value is loaded into the memory location specified by address
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* (the loaded value will be emitted to out from the next time step onward).
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*/
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CHIP RAM64 {
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IN in[16], load, address[6];
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OUT out[16];
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PARTS:
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// Put your code here:
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DMux8Way(in=load, sel=address[3..5], a=toRAM8A,
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b=toRAM8B,
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c=toRAM8C,
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d=toRAM8D,
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e=toRAM8E,
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f=toRAM8F,
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g=toRAM8G,
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h=toRAM8H);
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RAM8(in=in, load=toRAM8A, address=address[0..2], out=fromRAM8A);
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RAM8(in=in, load=toRAM8B, address=address[0..2], out=fromRAM8B);
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RAM8(in=in, load=toRAM8C, address=address[0..2], out=fromRAM8C);
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RAM8(in=in, load=toRAM8D, address=address[0..2], out=fromRAM8D);
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RAM8(in=in, load=toRAM8E, address=address[0..2], out=fromRAM8E);
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RAM8(in=in, load=toRAM8F, address=address[0..2], out=fromRAM8F);
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RAM8(in=in, load=toRAM8G, address=address[0..2], out=fromRAM8G);
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RAM8(in=in, load=toRAM8H, address=address[0..2], out=fromRAM8H);
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Mux8Way16(sel=address[3..5], out=out, a=fromRAM8A,
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b=fromRAM8B,
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c=fromRAM8C,
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d=fromRAM8D,
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e=fromRAM8E,
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f=fromRAM8F,
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g=fromRAM8G,
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h=fromRAM8H);
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}
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@@ -1,45 +1,45 @@
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// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/03/a/RAM8.hdl
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/**
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* Memory of 8 registers, each 16 bit-wide. Out holds the value
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* stored at the memory location specified by address. If load==1, then
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* the in value is loaded into the memory location specified by address
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* (the loaded value will be emitted to out from the next time step onward).
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*/
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CHIP RAM8 {
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IN in[16], load, address[3];
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OUT out[16];
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PARTS:
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// Put your code here:
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DMux8Way(in=load, sel=address, a=toRegisterA,
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b=toRegisterB,
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c=toRegisterC,
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d=toRegisterD,
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e=toRegisterE,
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f=toRegisterF,
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g=toRegisterG,
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h=toRegisterH);
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Register(in=in, load=toRegisterA, out=fromRegisterA);
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Register(in=in, load=toRegisterB, out=fromRegisterB);
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Register(in=in, load=toRegisterC, out=fromRegisterC);
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Register(in=in, load=toRegisterD, out=fromRegisterD);
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Register(in=in, load=toRegisterE, out=fromRegisterE);
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Register(in=in, load=toRegisterF, out=fromRegisterF);
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Register(in=in, load=toRegisterG, out=fromRegisterG);
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Register(in=in, load=toRegisterH, out=fromRegisterH);
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Mux8Way16(sel=address, out=out, a=fromRegisterA,
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b=fromRegisterB,
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c=fromRegisterC,
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d=fromRegisterD,
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e=fromRegisterE,
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f=fromRegisterF,
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g=fromRegisterG,
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h=fromRegisterH);
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}
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// This file is part of www.nand2tetris.org
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||||
// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/03/a/RAM8.hdl
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/**
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* Memory of 8 registers, each 16 bit-wide. Out holds the value
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* stored at the memory location specified by address. If load==1, then
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* the in value is loaded into the memory location specified by address
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* (the loaded value will be emitted to out from the next time step onward).
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*/
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CHIP RAM8 {
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IN in[16], load, address[3];
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OUT out[16];
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PARTS:
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// Put your code here:
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DMux8Way(in=load, sel=address, a=toRegisterA,
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b=toRegisterB,
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c=toRegisterC,
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d=toRegisterD,
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e=toRegisterE,
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f=toRegisterF,
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g=toRegisterG,
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h=toRegisterH);
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Register(in=in, load=toRegisterA, out=fromRegisterA);
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Register(in=in, load=toRegisterB, out=fromRegisterB);
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Register(in=in, load=toRegisterC, out=fromRegisterC);
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Register(in=in, load=toRegisterD, out=fromRegisterD);
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Register(in=in, load=toRegisterE, out=fromRegisterE);
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Register(in=in, load=toRegisterF, out=fromRegisterF);
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Register(in=in, load=toRegisterG, out=fromRegisterG);
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Register(in=in, load=toRegisterH, out=fromRegisterH);
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Mux8Way16(sel=address, out=out, a=fromRegisterA,
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b=fromRegisterB,
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c=fromRegisterC,
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d=fromRegisterD,
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e=fromRegisterE,
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f=fromRegisterF,
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g=fromRegisterG,
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h=fromRegisterH);
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}
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@@ -1,34 +1,34 @@
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// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/03/a/Register.hdl
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/**
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* 16-bit register:
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* If load[t] == 1 then out[t+1] = in[t]
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* else out does not change
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*/
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CHIP Register {
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IN in[16], load;
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OUT out[16];
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PARTS:
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// Put your code here:
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Bit(in=in[0], load=load, out=out[0]);
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Bit(in=in[1], load=load, out=out[1]);
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Bit(in=in[2], load=load, out=out[2]);
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Bit(in=in[3], load=load, out=out[3]);
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Bit(in=in[4], load=load, out=out[4]);
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Bit(in=in[5], load=load, out=out[5]);
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Bit(in=in[6], load=load, out=out[6]);
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Bit(in=in[7], load=load, out=out[7]);
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Bit(in=in[8], load=load, out=out[8]);
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Bit(in=in[9], load=load, out=out[9]);
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Bit(in=in[10], load=load, out=out[10]);
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Bit(in=in[11], load=load, out=out[11]);
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Bit(in=in[12], load=load, out=out[12]);
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Bit(in=in[13], load=load, out=out[13]);
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Bit(in=in[14], load=load, out=out[14]);
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Bit(in=in[15], load=load, out=out[15]);
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}
|
||||
// This file is part of www.nand2tetris.org
|
||||
// and the book "The Elements of Computing Systems"
|
||||
// by Nisan and Schocken, MIT Press.
|
||||
// File name: projects/03/a/Register.hdl
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|
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/**
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||||
* 16-bit register:
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* If load[t] == 1 then out[t+1] = in[t]
|
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* else out does not change
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*/
|
||||
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CHIP Register {
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IN in[16], load;
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OUT out[16];
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PARTS:
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// Put your code here:
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Bit(in=in[0], load=load, out=out[0]);
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Bit(in=in[1], load=load, out=out[1]);
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Bit(in=in[2], load=load, out=out[2]);
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Bit(in=in[3], load=load, out=out[3]);
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Bit(in=in[4], load=load, out=out[4]);
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Bit(in=in[5], load=load, out=out[5]);
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Bit(in=in[6], load=load, out=out[6]);
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Bit(in=in[7], load=load, out=out[7]);
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Bit(in=in[8], load=load, out=out[8]);
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||||
Bit(in=in[9], load=load, out=out[9]);
|
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Bit(in=in[10], load=load, out=out[10]);
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Bit(in=in[11], load=load, out=out[11]);
|
||||
Bit(in=in[12], load=load, out=out[12]);
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||||
Bit(in=in[13], load=load, out=out[13]);
|
||||
Bit(in=in[14], load=load, out=out[14]);
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||||
Bit(in=in[15], load=load, out=out[15]);
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||||
}
|
||||
|
||||
@@ -1,33 +1,33 @@
|
||||
// This file is part of www.nand2tetris.org
|
||||
// and the book "The Elements of Computing Systems"
|
||||
// by Nisan and Schocken, MIT Press.
|
||||
// File name: projects/03/b/RAM16K.hdl
|
||||
|
||||
/**
|
||||
* Memory of 16K registers, each 16 bit-wide. Out holds the value
|
||||
* stored at the memory location specified by address. If load==1, then
|
||||
* the in value is loaded into the memory location specified by address
|
||||
* (the loaded value will be emitted to out from the next time step onward).
|
||||
*/
|
||||
|
||||
CHIP RAM16K {
|
||||
IN in[16], load, address[14];
|
||||
OUT out[16];
|
||||
|
||||
PARTS:
|
||||
// Put your code here:
|
||||
DMux4Way(in=load, sel=address[12..13], a=toRAM4KA,
|
||||
b=toRAM4KB,
|
||||
c=toRAM4KC,
|
||||
d=toRAM4KD);
|
||||
|
||||
RAM4K(in=in, load=toRAM4KA, address=address[0..11], out=fromRAM4KA);
|
||||
RAM4K(in=in, load=toRAM4KB, address=address[0..11], out=fromRAM4KB);
|
||||
RAM4K(in=in, load=toRAM4KC, address=address[0..11], out=fromRAM4KC);
|
||||
RAM4K(in=in, load=toRAM4KD, address=address[0..11], out=fromRAM4KD);
|
||||
|
||||
Mux4Way16(sel=address[12..13], out=out, a=fromRAM4KA,
|
||||
b=fromRAM4KB,
|
||||
c=fromRAM4KC,
|
||||
d=fromRAM4KD);
|
||||
}
|
||||
// This file is part of www.nand2tetris.org
|
||||
// and the book "The Elements of Computing Systems"
|
||||
// by Nisan and Schocken, MIT Press.
|
||||
// File name: projects/03/b/RAM16K.hdl
|
||||
|
||||
/**
|
||||
* Memory of 16K registers, each 16 bit-wide. Out holds the value
|
||||
* stored at the memory location specified by address. If load==1, then
|
||||
* the in value is loaded into the memory location specified by address
|
||||
* (the loaded value will be emitted to out from the next time step onward).
|
||||
*/
|
||||
|
||||
CHIP RAM16K {
|
||||
IN in[16], load, address[14];
|
||||
OUT out[16];
|
||||
|
||||
PARTS:
|
||||
// Put your code here:
|
||||
DMux4Way(in=load, sel=address[12..13], a=toRAM4KA,
|
||||
b=toRAM4KB,
|
||||
c=toRAM4KC,
|
||||
d=toRAM4KD);
|
||||
|
||||
RAM4K(in=in, load=toRAM4KA, address=address[0..11], out=fromRAM4KA);
|
||||
RAM4K(in=in, load=toRAM4KB, address=address[0..11], out=fromRAM4KB);
|
||||
RAM4K(in=in, load=toRAM4KC, address=address[0..11], out=fromRAM4KC);
|
||||
RAM4K(in=in, load=toRAM4KD, address=address[0..11], out=fromRAM4KD);
|
||||
|
||||
Mux4Way16(sel=address[12..13], out=out, a=fromRAM4KA,
|
||||
b=fromRAM4KB,
|
||||
c=fromRAM4KC,
|
||||
d=fromRAM4KD);
|
||||
}
|
||||
|
||||
@@ -1,45 +1,45 @@
|
||||
// This file is part of www.nand2tetris.org
|
||||
// and the book "The Elements of Computing Systems"
|
||||
// by Nisan and Schocken, MIT Press.
|
||||
// File name: projects/03/b/RAM4K.hdl
|
||||
|
||||
/**
|
||||
* Memory of 4K registers, each 16 bit-wide. Out holds the value
|
||||
* stored at the memory location specified by address. If load==1, then
|
||||
* the in value is loaded into the memory location specified by address
|
||||
* (the loaded value will be emitted to out from the next time step onward).
|
||||
*/
|
||||
|
||||
CHIP RAM4K {
|
||||
IN in[16], load, address[12];
|
||||
OUT out[16];
|
||||
|
||||
PARTS:
|
||||
// Put your code here:
|
||||
DMux8Way(in=load, sel=address[9..11], a=toRAM512A,
|
||||
b=toRAM512B,
|
||||
c=toRAM512C,
|
||||
d=toRAM512D,
|
||||
e=toRAM512E,
|
||||
f=toRAM512F,
|
||||
g=toRAM512G,
|
||||
h=toRAM512H);
|
||||
|
||||
RAM512(in=in, load=toRAM512A, address=address[0..8], out=fromRAM512A);
|
||||
RAM512(in=in, load=toRAM512B, address=address[0..8], out=fromRAM512B);
|
||||
RAM512(in=in, load=toRAM512C, address=address[0..8], out=fromRAM512C);
|
||||
RAM512(in=in, load=toRAM512D, address=address[0..8], out=fromRAM512D);
|
||||
RAM512(in=in, load=toRAM512E, address=address[0..8], out=fromRAM512E);
|
||||
RAM512(in=in, load=toRAM512F, address=address[0..8], out=fromRAM512F);
|
||||
RAM512(in=in, load=toRAM512G, address=address[0..8], out=fromRAM512G);
|
||||
RAM512(in=in, load=toRAM512H, address=address[0..8], out=fromRAM512H);
|
||||
|
||||
Mux8Way16(sel=address[9..11], out=out, a=fromRAM512A,
|
||||
b=fromRAM512B,
|
||||
c=fromRAM512C,
|
||||
d=fromRAM512D,
|
||||
e=fromRAM512E,
|
||||
f=fromRAM512F,
|
||||
g=fromRAM512G,
|
||||
h=fromRAM512H);
|
||||
}
|
||||
// This file is part of www.nand2tetris.org
|
||||
// and the book "The Elements of Computing Systems"
|
||||
// by Nisan and Schocken, MIT Press.
|
||||
// File name: projects/03/b/RAM4K.hdl
|
||||
|
||||
/**
|
||||
* Memory of 4K registers, each 16 bit-wide. Out holds the value
|
||||
* stored at the memory location specified by address. If load==1, then
|
||||
* the in value is loaded into the memory location specified by address
|
||||
* (the loaded value will be emitted to out from the next time step onward).
|
||||
*/
|
||||
|
||||
CHIP RAM4K {
|
||||
IN in[16], load, address[12];
|
||||
OUT out[16];
|
||||
|
||||
PARTS:
|
||||
// Put your code here:
|
||||
DMux8Way(in=load, sel=address[9..11], a=toRAM512A,
|
||||
b=toRAM512B,
|
||||
c=toRAM512C,
|
||||
d=toRAM512D,
|
||||
e=toRAM512E,
|
||||
f=toRAM512F,
|
||||
g=toRAM512G,
|
||||
h=toRAM512H);
|
||||
|
||||
RAM512(in=in, load=toRAM512A, address=address[0..8], out=fromRAM512A);
|
||||
RAM512(in=in, load=toRAM512B, address=address[0..8], out=fromRAM512B);
|
||||
RAM512(in=in, load=toRAM512C, address=address[0..8], out=fromRAM512C);
|
||||
RAM512(in=in, load=toRAM512D, address=address[0..8], out=fromRAM512D);
|
||||
RAM512(in=in, load=toRAM512E, address=address[0..8], out=fromRAM512E);
|
||||
RAM512(in=in, load=toRAM512F, address=address[0..8], out=fromRAM512F);
|
||||
RAM512(in=in, load=toRAM512G, address=address[0..8], out=fromRAM512G);
|
||||
RAM512(in=in, load=toRAM512H, address=address[0..8], out=fromRAM512H);
|
||||
|
||||
Mux8Way16(sel=address[9..11], out=out, a=fromRAM512A,
|
||||
b=fromRAM512B,
|
||||
c=fromRAM512C,
|
||||
d=fromRAM512D,
|
||||
e=fromRAM512E,
|
||||
f=fromRAM512F,
|
||||
g=fromRAM512G,
|
||||
h=fromRAM512H);
|
||||
}
|
||||
|
||||
@@ -1,45 +1,45 @@
|
||||
// This file is part of the materials accompanying the book
|
||||
// "The Elements of Computing Systems" by Nisan and Schocken,
|
||||
// MIT Press. Book site: www.idc.ac.il/tecs
|
||||
// File name: projects/03/b/RAM512.hdl
|
||||
|
||||
/**
|
||||
* Memory of 512 registers, each 16 bit-wide. Out holds the value
|
||||
* stored at the memory location specified by address. If load==1, then
|
||||
* the in value is loaded into the memory location specified by address
|
||||
* (the loaded value will be emitted to out from the next time step onward).
|
||||
*/
|
||||
|
||||
CHIP RAM512 {
|
||||
IN in[16], load, address[9];
|
||||
OUT out[16];
|
||||
|
||||
PARTS:
|
||||
// Put your code here:
|
||||
DMux8Way(in=load, sel=address[6..8], a=toRAM64A,
|
||||
b=toRAM64B,
|
||||
c=toRAM64C,
|
||||
d=toRAM64D,
|
||||
e=toRAM64E,
|
||||
f=toRAM64F,
|
||||
g=toRAM64G,
|
||||
h=toRAM64H);
|
||||
|
||||
RAM64(in=in, load=toRAM64A, address=address[0..5], out=fromRAM64A);
|
||||
RAM64(in=in, load=toRAM64B, address=address[0..5], out=fromRAM64B);
|
||||
RAM64(in=in, load=toRAM64C, address=address[0..5], out=fromRAM64C);
|
||||
RAM64(in=in, load=toRAM64D, address=address[0..5], out=fromRAM64D);
|
||||
RAM64(in=in, load=toRAM64E, address=address[0..5], out=fromRAM64E);
|
||||
RAM64(in=in, load=toRAM64F, address=address[0..5], out=fromRAM64F);
|
||||
RAM64(in=in, load=toRAM64G, address=address[0..5], out=fromRAM64G);
|
||||
RAM64(in=in, load=toRAM64H, address=address[0..5], out=fromRAM64H);
|
||||
|
||||
Mux8Way16(sel=address[6..8], out=out, a=fromRAM64A,
|
||||
b=fromRAM64B,
|
||||
c=fromRAM64C,
|
||||
d=fromRAM64D,
|
||||
e=fromRAM64E,
|
||||
f=fromRAM64F,
|
||||
g=fromRAM64G,
|
||||
h=fromRAM64H);
|
||||
}
|
||||
// This file is part of the materials accompanying the book
|
||||
// "The Elements of Computing Systems" by Nisan and Schocken,
|
||||
// MIT Press. Book site: www.idc.ac.il/tecs
|
||||
// File name: projects/03/b/RAM512.hdl
|
||||
|
||||
/**
|
||||
* Memory of 512 registers, each 16 bit-wide. Out holds the value
|
||||
* stored at the memory location specified by address. If load==1, then
|
||||
* the in value is loaded into the memory location specified by address
|
||||
* (the loaded value will be emitted to out from the next time step onward).
|
||||
*/
|
||||
|
||||
CHIP RAM512 {
|
||||
IN in[16], load, address[9];
|
||||
OUT out[16];
|
||||
|
||||
PARTS:
|
||||
// Put your code here:
|
||||
DMux8Way(in=load, sel=address[6..8], a=toRAM64A,
|
||||
b=toRAM64B,
|
||||
c=toRAM64C,
|
||||
d=toRAM64D,
|
||||
e=toRAM64E,
|
||||
f=toRAM64F,
|
||||
g=toRAM64G,
|
||||
h=toRAM64H);
|
||||
|
||||
RAM64(in=in, load=toRAM64A, address=address[0..5], out=fromRAM64A);
|
||||
RAM64(in=in, load=toRAM64B, address=address[0..5], out=fromRAM64B);
|
||||
RAM64(in=in, load=toRAM64C, address=address[0..5], out=fromRAM64C);
|
||||
RAM64(in=in, load=toRAM64D, address=address[0..5], out=fromRAM64D);
|
||||
RAM64(in=in, load=toRAM64E, address=address[0..5], out=fromRAM64E);
|
||||
RAM64(in=in, load=toRAM64F, address=address[0..5], out=fromRAM64F);
|
||||
RAM64(in=in, load=toRAM64G, address=address[0..5], out=fromRAM64G);
|
||||
RAM64(in=in, load=toRAM64H, address=address[0..5], out=fromRAM64H);
|
||||
|
||||
Mux8Way16(sel=address[6..8], out=out, a=fromRAM64A,
|
||||
b=fromRAM64B,
|
||||
c=fromRAM64C,
|
||||
d=fromRAM64D,
|
||||
e=fromRAM64E,
|
||||
f=fromRAM64F,
|
||||
g=fromRAM64G,
|
||||
h=fromRAM64H);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user