51 lines
1.6 KiB
Markdown
51 lines
1.6 KiB
Markdown
# 03 Sequential Logic
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Build sequential chips `Bit` , `Register` and `PC`, that make use of the data flip flop (DFF) to store the state. `DFF` is considered primitive, so it's not necessary to implement it. The memory chips `RAM512` and `RAM3840` are based on the primitive `RAM256`, which uses block ram structures integrated in iCE40HX1K. `BitShift9R` and `BitShift8L` are new chips not explained in the original nand2tetris course. They serve to connect HACK to different IO-Devices, which are connected using a serial protocol, where data is transmitted bitwise.
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## blinky
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The folder `08_blinky` contains a project to test the counter `PC` in real hardware. Blinky uses counters `PC` to scale down the frequency of 100MHz provided by the clock oscillator on iCE40HX1K-EVB and finally drives the LED1/2.
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***
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### Project
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* Implement the chips `Bit`, `Register`, `PC`, `RAM512`, `RAM3840`, `BitShift9R` and `BitShift8L` using `DFF` as primitive building block.
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* Implement the chips `RAM512` and `RAM3840` using `RAM256` as primitive building block.
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* for every chip we provide a test bench in the dedicated folder.
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```shell
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$ cd <test folder>
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$ apio clean
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$ apio sim
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```
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* Run blinky in simulation
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```
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$ cd 06_blinky
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$ apio clean
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$ apio sim
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```
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* Zoom in to check the prescaler:
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* Zoom out to check the counter:
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* Upload the project to iCE40HX1K-EVB end test in real hardware:
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```
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$ cd 06_blinky
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$ apio clean
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$ apio upload
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```
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* Look at LED1/2 and see if they blink. |