135 lines
4.4 KiB
Markdown
135 lines
4.4 KiB
Markdown
# 01 Boolean Logic
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The hardware part of the project nand2tetris-fpga is implemented in verilog, a hardware description language similar to HDL used in the original nand2tetris course. There is no need to learn much verilog, as you can easily translate all your HDL-files into verilog following the given example for `Xor`.
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**Note:**
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The following modules are considered primitive and thus there is no need to implement them.
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| module | description |
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| ---------- | --------------------------------------------------------------------- |
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| `Nand.v` | Nand-gate. Basic building block for combinatorial logic |
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| `DFF.v` | Data Flip Flop. Basic building block for sequential logic |
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| `RAM256.v` | uses Block Ram (BRAM) of iCE40 |
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| `ROM.v` | uses Block Ram (BRAM) of iCE40 preloaded with HACK-code at startup |
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| `InOut.v` | Tristate buffer, used to connect to the bidirectional databus of SRAM |
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***
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## Example Xor
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### Xor.hdl
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Yout implementation of Xor in HDL (nand2tetris) should look something like:
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```
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// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/01/Xor.hdl
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/**
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* Xor (exclusive or) gate:
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* If a<>b out=1 else out=0.
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*/
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CHIP Xor {
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IN a, b;
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OUT out;
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PARTS:
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Not(in=a, out=nota);
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Not(in=b, out=notb);
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And(a=a, b=notb, out=w1);
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And(a=nota, b=b, out=w2);
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Or(a=w1, b=w2, out=out);
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}
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```
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### Xor.v
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`Xor.hdl` can easily be translated into `Xor.v` (verilog):
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```
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/**
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* Xor (exclusive or) gate:
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* If a<>b out=1 else out=0.
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*/
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module Xor(
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input a,
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input b,
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output out
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);
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wire nota; //new wire must be declared (as wire)
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wire notb;
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Not NOT1(.in(a), .out(nota)); //Every chip has an instance name (NOT1)
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Not NOT2(.in(b), .out(notb)); //this chip is named NOT2
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wire w1;
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wire w2;
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And AND1(.a(a),.b(notb),.out(w1));
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And AND2(.a(nota),.b(b),.out(w2));
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Or OR(.a(w1),.b(w2),.out(out));
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}
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```
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### Simulation
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For every chip wie provide a test folder e.g. `05_Xor`, in which you find a so called testbench (`Xor_tb.v`). To run the test bench cd into the test directory and run apio:
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```
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$ cd 05_Xor
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$ apio clean (used to remove older implementation from cache)
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$ apio sim
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```
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**Attention:** All used chips used in the verilog code must be already implemented and included in the `Include.v` file.
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The test bench will produce a graphical represantation `Xor.gtkw` of all signal lines, which can be viewed with gtkwave.
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You can see four sections:
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* `IN`: the input signals (generated by the test bench)
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* `OUT`: the output signals (generated by YOUR chip implementation)
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* `CMP`: the output signals (generated by the test bench)
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* `Test`: the fail signal. Goes high, when the test fails.
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Your chip passes the test, when `out=out_cmp` and `fail=0` over the whole test time.
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### iCE40HX1K.pcf
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To upload the chip `Xor` onto your fpga board iCE40HX1K-EVB you need two additional files: `top.v` and `iCE40HX1K.pcf` (physical constraints file). The pyhiscal constraints file assigns every io-signal wire of the top level module `top.v` to physical pins of the fpga chip iCE40HX1K. Pin numbering can be checked by consulting the schematic [iCE40HX1K-EVB](../doc/iCE40HX1K-EVB_Rev_B.pdf) in `doc/iCE40HX1K-EVB_Rev_B.pdf`.
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```
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# physical constrain file
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# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB
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# compare to the schematic of the board and the datasheet of fpga
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set_io BUT1 41 # BUT1
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set_io BUT2 42 # BUT2
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set_io LED1 40 # LED1
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set_io LED2 51 # LED2
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```
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* Now you can build and upload the chip `Xor` to iCE40-HX1K-EVB with:
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```
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$ apio clean
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$ apio build
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$ apio upload
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```
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* Press buttons BUT1 and BUT2 and see the result of your `Xor` chip on LED1.
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**Attention:** Due to pull up resistors at the buttons, the signals appear inverted:
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| pin | function |
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| ------ | ------------------------------------------------- |
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| LED1/2 | 0 led is off, 1 led is on |
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| BUT1/2 | 0 button is pressed down, 1 button is released up |
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Chips with note more than two in- and output signals can be uploaded and tested in real hardware: `Nand`, `Not`, `Buffer`, `And`, `Or`, `Xor` and `DMux`. |