169 lines
5.7 KiB
Markdown
169 lines
5.7 KiB
Markdown
## 04 SRAM
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The evaluation board iCE40HX1K-EVB includes an 512kbyte static ram chip K6R4016V1D. The SRAM chip connects to iCE40HX1K with 37 wires;
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- SRAM_ADDR 18 bit
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- SRAM_DATA 16 bit (bidiretional inout)
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- SRAM_CSX (chip select not)
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- SRAM_OEX (output enable not)
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- SRAM_WEX (write enable not)
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To read and write to the SRAM chip we will add two special function register to HACK:
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1. SRAM_A is a 16 bit register mapped at memory location 4104. SRAM_ADDR controls the 16 lower bits of the 18 bit address bus. The two most significant bits are allways 0, so we can only access 64k x 16 bit words of SRAM chip.
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2. SRAM_D is a special function register mapped at memory location 4105. SRAM_D controls the bidirectional data bus and the control wires CSX, OEX and WEX.
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**Note:** the 16 bit data bus is bidirectional and has therefore to be connected over a tristate buffer. This is done with `InOut.v` which is considered primitive and must not be implemented.
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### Chip specification SRAM_A
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SRAM_A is a simple `Register` that stores the lower 16 bit of the 18 bit address of the SRAM chip.
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### Chip specification SRAM_D
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| IN/OUT | wire | function |
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| ------ | --------------- | -------------------------- |
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| IN | clk | system clock (25MHz) |
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| IN | load | initiate a write operation |
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| IN | in[15:0] | data to write to SRAM |
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| OUT | out[15:0] | data read from SRAM |
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| INOUT | SRAM_DATA[15:0] | bidirectional data bus |
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| OUT | SRAM_CSX | chip select not |
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| OUT | SRAM_OEX | output enable not |
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| OUT | SRAM_WEX | write enable not |
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When load[t]=1 transmission of word in[15:0] is initiated. The word is send to SRAM over the bidirectional wires SRAM_DATA (direction out) and a write pulse will be triggered for one cycle at t+1:
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* SRAM_OEX=1
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* SRAM_WEX=0
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When load=0 SRAM_DATA will be used as input and the data of the SRAM chip will be presented at out[15:0]
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- SRAM_OEX=0
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- SRAM_WEX=1
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SRAM_CSX can be set to low all the time.
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### Proposed Implementation ADDR_A
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Use a `Register` to store the lower 16 bit of SRAM_ADDR (The two most significant bits are hardwired to 0).
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### Proposed Implementation ADDR_D
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Use a `DFF` to delay the load signal. Use a `Register` to store the data in[15:0] to be stored. Use a tristate buffer `InOut.v` to control the direction of the bidirectional SRAM_DATA data bus.
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### Memory map
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The special function register `SRAM_A` and `SRAM_D` are mapped to memory map of HACK according to:
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| address | I/O device | R/W | function |
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| ------- | ---------- | --- | ------------------------------ |
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| 4101 | SRAM_A | R | address of SRAM |
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| 4102 | SRAM_D | R | read data from SRAM |
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| 4102 | SRAM_D | W | initiate a write cylce to SRAM |
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### buffer.asm
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To test HACK with SRAM we need a little machine language programm `buffer.asm`, which reads the first four bytes of an ASCII file previosuly stored to the SPI flash memory chip W25Q16BV of iCE40HX1K-EVB, starting at address 0x040000 (256k) and stores the four bytes to SRAM. Finally we read the four bytes from SRAM and write them to UART.
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### SRAM in real hardware
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The board iCE40HX1K-EVB comes with a static ram chip K6R4016V1D. The chip is already connected to iCE40HX1K according `iCE40HX1K-EVB.pcf` (Compare with schematic [iCE40HX1K_EVB](../../doc/iCE40HX1K-EVB_Rev_B.pdf).
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```
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set_io SRAM_ADDR[0] 79 # SA0
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set_io SRAM_ADDR[1] 80 # SA1
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set_io SRAM_ADDR[2] 81 # SA2
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set_io SRAM_ADDR[3] 82 # SA3
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set_io SRAM_ADDR[4] 83 # SA4
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set_io SRAM_ADDR[5] 85 # SA5
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set_io SRAM_ADDR[6] 86 # SA6
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set_io SRAM_ADDR[7] 87 # SA7
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set_io SRAM_ADDR[8] 89 # SA8
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set_io SRAM_ADDR[9] 90 # SA9
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set_io SRAM_ADDR[10] 91 # SA10
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set_io SRAM_ADDR[11] 93 # SA11
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set_io SRAM_ADDR[12] 94 # SA12
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set_io SRAM_ADDR[13] 95 # SA13
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set_io SRAM_ADDR[14] 96 # SA14
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set_io SRAM_ADDR[15] 97 # SA15
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set_io SRAM_ADDR[16] 99 # SA16
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set_io SRAM_ADDR[17] 100 # SA17
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set_io SRAM_CSX 78 # SRAM_#CS
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set_io SRAM_OEX 74 # SRAM_#OE
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set_io SRAM_WEX 73 # SRAM_#WE
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set_io SRAM_DATA[0] 62 # SD0
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set_io SRAM_DATA[1] 63 # SD1
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set_io SRAM_DATA[2] 64 # SD2
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set_io SRAM_DATA[3] 65 # SD3
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set_io SRAM_DATA[4] 66 # SD4
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set_io SRAM_DATA[5] 68 # SD5
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set_io SRAM_DATA[6] 69 # SD6
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set_io SRAM_DATA[7] 71 # SD7
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set_io SRAM_DATA[8] 72 # SD8
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set_io SRAM_DATA[9] 60 # SD9
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set_io SRAM_DATA[10] 59 # SD10
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set_io SRAM_DATA[11] 57 # SD11
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set_io SRAM_DATA[12] 56 # SD12
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set_io SRAM_DATA[13] 54 # SD13
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set_io SRAM_DATA[14] 53 # SD14
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set_io SRAM_DATA[15] 52 # SD15
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```
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***
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### Project
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* Implement `SRAM_D.v` and simulate with testbench:
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```
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$ cd 04_SRAM_D
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$ apio clean
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$ apio sim
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```
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* Compare output of your chip `OUT` with `CMP`.
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![](sram_tb.png)
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* Edit `HACK.v` and add a `Register` for SRAM_A memory mapped to 4101.
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* Edit `HACK.v` and add a special function register `SRAM_D` to memory address 4102.
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* Implement `buffer.asm` and test with the testbench:
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```
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$ cd 04_SRAM_D
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$ make
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$ cd ../00_HACK
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$ apio clean
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$ apio sim
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```
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* Check the SRAM wires of the simulation and look for the storing of "SPI!" (which was preloaded in SPI chip at memory address 0x040000 of the testbench).
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![](buffer1.png)
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* Check the output at UART_TX in the long run. You should see the string "SPI!" output to UART_TX:
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![](buffer.png)
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* preload the SPI memory chip with some text file at address 0x040000.
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* build and upload HACK with `buffer.asm` in ROM.BIN to iCE40HX1K-EVB.
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- press reset button on iCE40HX1K-EVB and see if wou can receive the preloaded text file on your Computer.
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```
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$ echo SPI! > spi.txt
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$ iceprogduino -o 256k -w spi.txt
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$ cd 04_SRAM_D
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$ make
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$ cd ../00_HACK
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$ apio clean
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$ apio upload
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$ tio /dev/ttyACM0
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```
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