43 lines
1.1 KiB
Verilog
43 lines
1.1 KiB
Verilog
/**
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* SRAM controller:
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* If load[t] == 1 then out[t+1] = in[t]
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* OEX[t+1] = 1
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* WEX[t+1] = 0
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* DATA[t+1] = in[t] (DATA is configured as output)
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* At any other time:
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* out = DATA (DATA is configured as input)
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* CSX =0;
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*/
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`default_nettype none
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module SRAM_D(
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input clk,
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input load,
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input [15:0] in,
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output [15:0] out,
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inout [15:0] DATA, // SRAM data 16 Bit
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output CSX, // SRAM chip_enable_not
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output reg OEX, // SRAM output_enable_not
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output reg WEX // SRAM write_enable_not
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);
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// Put your code here:
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reg [15:0] to_sram;
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always @(posedge clk) begin
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if (load) begin
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OEX <= 1;
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WEX <= 0;
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to_sram <= in;
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end else begin
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OEX <= 0;
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WEX <= 1;
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end
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end
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//DFF DFF(clk, load, LOAD);
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//Register Register(clk, in, load, to_sram);
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// assign OEX = (LOAD) ? 1 : 0;
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// assign WEX = (LOAD) ? 0 : 1;
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assign CSX = 0;
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InOut InOut(DATA, to_sram, out, OEX);
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endmodule
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