build hack with UART TX / RX support

06_IO_Devices/01_UartTX/hello.asm

@@ -2,3 +2,31 @@
 // this little assembler programm outputs "Hi" on UART_TX
 // 
 // Put your code here:
+//check tx status
+(START)
+@UART_TX
+D=M
+@SENDH
+D;JEQ
+@START
+0;JMP
+(SENDH)
+@72
+D=A
+@UART_TX
+M=D
+(WAIT)
+@UART_TX 
+D=M
+@SENDI
+D;JEQ
+@WAIT
+0;JMP
+(SENDI)
+@105
+D=A
+@UART_TX
+M=D
+(END)
+@END
+0;JMP

06_IO_Devices/GO.v

@@ -14,5 +14,13 @@ module GO(
 );
 	
 	// Put your code here:
-
+	reg active=0;
+	always @(posedge clk) begin
+			if (load) begin
+				active = 1;
+			end
+		end
+	
+	assign instruction = (active) ? sram_data : ROM_data;
+	assign SRAM_ADDR = (active) ? pc : sram_addr;
 endmodule

06_IO_Devices/HACK.v

@@ -35,5 +35,102 @@ module HACK(
 );
 
 	// Put your code here:
+    wire loadRAM;
+    wire loadIO0;
+    wire loadIO1;
+    wire loadIO2;
+    wire loadIO3;
+    wire loadIO4;
+    wire loadIO5;
+    wire loadIO6;
+    wire loadIO7;
+    wire loadIO8;
+    wire loadIO9;
+    wire loadIOA;
+    wire loadIOB;
+    wire loadIOC;
+    wire loadIOD;
+    wire loadIOE;
+    wire loadIOF;
+    wire [15:0] inRAM;
+    wire [15:0] inIO0;
+    wire [15:0] inIO1;
+    wire [15:0] inIO2;
+    wire [15:0] inIO3;
+    wire [15:0] inIO4=0;
+    wire [15:0] inIO5=0;
+    wire [15:0] inIO6=0;
+    wire [15:0] inIO7=0;
+    wire [15:0] inIO8=0;
+    wire [15:0] inIO9=0;
+    wire [15:0] inIOA=0;
+    wire [15:0] inIOB;
+    wire [15:0] inIOC;
+    wire [15:0] inIOD;
+    wire [15:0] inIOE;
+    wire [15:0] inIOF;
 
+    wire writeM;
+    wire [15:0] inM;
+    wire [15:0] instruction;
+    wire [15:0] outM;
+    wire [15:0] addressM;
+    wire [15:0] pc;
+
+    wire clk, reset;
+    wire [15:0] outDEBUG0;
+    wire [15:0] outDEBUG1;
+    wire [15:0] outDEBUG2;
+    wire loadDEBUG0;
+    wire loadDEBUG1;
+    wire loadDEBUG2;
+    // Put your code here:
+    assign LED[1:0] = inIO0[1:0];
+    assign outDEBUG0 = inIOB;
+    assign outDEBUG1 = inIOC;
+    assign outDEBUG2 = inIOD;
+    assign loadDEBUG0 = loadIOB;
+    assign loadDEBUG1 = loadIOC;
+    assign loadDEBUG2 = loadIOD;
+    Clock25_Reset20 CLKR(CLK, clk, reset);
+    CPU CPU(clk, inM, instruction, reset, outM, writeM, addressM, pc);
+
+    Memory Memory(addressM, writeM, inM, loadRAM,
+        loadIO0, loadIO1, loadIO2, loadIO3, loadIO4, loadIO5, loadIO6, loadIO7,
+        loadIO8, loadIO9, loadIOA, loadIOB, loadIOC, loadIOD, loadIOE, loadIOF,
+        inRAM, inIO0, inIO1, inIO2, inIO3, inIO4, inIO5, inIO6, inIO7,
+        inIO8, inIO9, inIOA, inIOB, inIOC, inIOD, inIOE, inIOF);
+
+    ROM ROM(pc, instruction);
+    RAM3840 RAM(clk, addressM[11:0], outM, loadRAM, inRAM);
+
+    Register LED12(clk, outM, loadIO0, inIO0);
+    Register BUT12(clk, {14'b0, BUT[1:0]}, 1'b1, inIO1);
+
+    UartTX UartTX(clk, loadIO2, outM, UART_TX, inIO2);
+    UartRX UartRX(clk, loadIO3, UART_RX, inIO3);
+
+    //SPI SPI(clk, loadIO4, outM, inIO4, SPI_CSX, SPI_SDO, SPI_SDI, SPI_SCK);
+    //GO GO(clk, loadIO5, pc, sram_addr, SRAM_ADDR, sram_data, ROM_data, instruction);
+
+    Register DEBUG0(clk, outM, loadIOB, inIOB);
+    Register DEBUG1(clk, outM, loadIOC, inIOC);
+    Register DEBUG2(clk, outM, loadIOD, inIOD);
+    Register DEBUG3(clk, outM, loadIOE, inIOE);
+    Register DEBUG4(clk, outM, loadIOF, inIOF);
+
+assign SPI_SDO=0;
+assign SPI_SCK=0;
+assign SPI_CSX=0;
+assign SRAM_ADDR=0;
+assign SRAM_DATA=0;
+assign SRAM_WEX=0;
+assign SRAM_OEX=0;
+assign SRAM_CSX=0;
+assign LCD_DCX=0;
+assign LCD_SDO=0;
+assign LCD_SCK=0;
+assign LCD_CSX=0;
+assign RTP_SDO=0;
+assign RTP_SCK=0;
 endmodule

06_IO_Devices/SPI.v

@@ -9,16 +9,120 @@
 `default_nettype none
 
 module SPI(
-	input clk,
-	input load,
-	input [15:0] in,
-	output [15:0] out,
-	output CSX,
-	output SDO,
-	input SDI,
-	output SCK
+    input clk,
+    input load,
+    input [15:0] in,
+    output reg [15:0] out,
+    output reg CSX,
+    output reg SDO,
+    input SDI,
+    output reg SCK
 );
 
-	// Put your code here:	
+    // Put your code here:
+    // 1100 0000 0101 1011
+    // 1000 0000 0101 1011
+    reg temp;
+    reg active=0;
+    reg [7:0] totx;
+    reg [7:0] torx;
+    reg [11:0] is216;
 
+    always @(posedge clk) begin
+        CSX <= 0;
+        SDO <= 0;
+        SCK <= 0;
+        out <= (out)? out : 0;
+        if (load == 1) begin
+            out[14:8] <= 0;
+            out[7:0] <= in[7:0];
+            if (in[8]==1) begin
+                out[15] <= 0;
+                CSX <= 1;
+            end
+            else if (in[8]==0) begin
+                out[15] <= 1;
+                CSX <= 0;
+                active <= 1;
+                is216 <= 1;
+                totx[7:0] <= in[7:0];
+                SDO <= in[7];
+                //out <= (out<<1);
+                //out[0] <= SDI;
+                //torx[7] <= SDI;
+            end
+        end
+        else if (active==1) begin
+            SCK <= ~SCK;
+            if (is216 == 16) begin
+                active <= 0;
+                CSX <= CSX;
+                out <= {8'b0, torx[7:0]};
+            end
+            else begin
+                CSX <= 0;
+                is216 <= is216 + 1;
+                //SDO <= totx[7-(is216/2)];
+                torx[7-(is216/2)] <= SDI;
+                    case (is216+1)
+                        2  : SDO <= totx[7];
+                        3  : SDO <= totx[6];
+                        4  : SDO <= totx[6];
+                        5  : SDO <= totx[5];
+                        6  : SDO <= totx[5];
+                        7  : SDO <= totx[4];
+                        8  : SDO <= totx[4];
+                        9  : SDO <= totx[3];
+                        10 : SDO <= totx[3];
+                        11 : SDO <= totx[2];
+                        12 : SDO <= totx[2];
+                        13 : SDO <= totx[1];
+                        14 : SDO <= totx[1];
+                        15 : SDO <= totx[0];
+                        16 : SDO <= totx[0];
+                    endcase
+                
+                    // case (is216)
+                    //     3  : torx[6] <= SDI;
+                    //     5  : torx[5] <= SDI;
+                    //     7  : torx[4] <= SDI;
+                    //     9  : torx[3] <= SDI;
+                    //     11 : torx[2] <= SDI;
+                    //     13 : torx[1] <= SDI;
+                    //     15 : torx[0] <= SDI;
+                    // endcase
+                case (is216)
+                    2  : out <= (out<<1);
+                    4  : out <= (out<<1);
+                    6  : out <= (out<<1);
+                    8  : out <= (out<<1);
+                    10 : out <= (out<<1);
+                    12 : out <= (out<<1);
+                    14 : out <= (out<<1);
+                endcase
+                case (is216)
+                    2  : out[0] <= torx[7];
+                    4  : out[0] <= torx[6];
+                    6  : out[0] <= torx[5];
+                    8  : out[0] <= torx[4];
+                    10 : out[0] <= torx[3];
+                    12 : out[0] <= torx[2];
+                    14 : out[0] <= torx[1];
+                endcase
+                case (is216)
+                    2  : out[15:8] <= {8'b10000000};
+                    4  : out[15:8] <= {8'b10000000};
+                    6  : out[15:8] <= {8'b10000000};
+                    8  : out[15:8] <= {8'b10000000};
+                    10 : out[15:8] <= {8'b10000000};
+                    12 : out[15:8] <= {8'b10000000};
+                    14 : out[15:8] <= {8'b10000000};
+                endcase
+            end
+        end else begin
+            CSX <= CSX;
+            out <= out? out : 16'b0;
+        end
+    end
 endmodule
+

06_IO_Devices/SRAM_D.v

@@ -10,16 +10,33 @@
  */
 `default_nettype none
 module SRAM_D(
-	input clk,
-	input load,
-	input [15:0] in,
-	output [15:0] out,
-	inout [15:0] DATA,	// SRAM data 16 Bit
-	output CSX, 		// SRAM chip_enable_not
-	output OEX,		// SRAM output_enable_not
-	output WEX			// SRAM write_enable_not
+    input clk,
+    input load,
+    input [15:0] in,
+    output [15:0] out,
+    inout [15:0] DATA,  // SRAM data 16 Bit
+    output CSX,         // SRAM chip_enable_not
+    output reg OEX,     // SRAM output_enable_not
+    output reg WEX      // SRAM write_enable_not
 );
-	
-	// Put your code here:
+
+    // Put your code here:
+    reg [15:0] to_sram;
+    always @(posedge clk) begin
+        if (load) begin
+            OEX <= 1;
+            WEX <= 0;
+            to_sram <= in;
+        end else begin
+            OEX <= 0;
+            WEX <= 1;
+        end
+    end
+    //DFF DFF(clk, load, LOAD);
+    //Register Register(clk, in, load, to_sram);
+    // assign OEX = (LOAD) ? 1 : 0;
+    // assign WEX = (LOAD) ? 0 : 1;
+    assign CSX = 0;
+    InOut InOut(DATA, to_sram, out, OEX);
 
 endmodule

06_IO_Devices/UartRX.v

@@ -7,14 +7,45 @@
  * of byte completes, chip ouputs the received byte to out[7:0]] with out[15]=0.
  */
 `default_nettype none
-
 module UartRX(
-	input clk,
-	input clear,
-	input RX,
-	output [15:0] out
+    input clk,
+    input clear,
+    input RX,
+    output reg [15:0] out
 );
-	
-	// Put your code here:
 
+    // Put your code here:
+    wire clkdRX;
+    reg active=0;
+    reg [7:0] uart;
+    reg [3:0] nthbit;
+    reg [11:0] is216;
+    always @(posedge clk) begin
+        out <= clear ? 16'h8000 : out;
+
+        if ((active==0) && (RX == 0)) begin
+            active <= 1;
+            is216 <= 1;
+            uart <= 0;
+            nthbit <= 0;
+        end
+        else if (active==1) begin
+            is216 <= (is216 == 216) ? 0 : is216 + 1;
+            nthbit <= (is216 == 108) ? nthbit + 1 : nthbit;
+            case (nthbit)
+                1 : uart[0] <= RX;
+                2 : uart[1] <= RX;
+                3 : uart[2] <= RX;
+                4 : uart[3] <= RX;
+                5 : uart[4] <= RX;
+                6 : uart[5] <= RX;
+                7 : uart[6] <= RX;
+                8 : uart[7] <= RX;
+            endcase
+            if (nthbit == 10 && is216 == 216) begin
+                active <= 0;
+                out <= {8'b0, uart};
+            end
+        end
+    end
 endmodule

06_IO_Devices/UartTX.v

@@ -9,13 +9,46 @@
  */
 `default_nettype none
 module UartTX(
-	input clk,
-	input load,
-	input [15:0] in,
-	output TX,
-	output [15:0] out
+    input clk,
+    input load,
+    input [15:0] in,
+    output TX,
+    output reg [15:0] out
 );
 
-	// Put your code here:
+    reg uart=1;
+    reg active=0;
+    reg [7:0] to_send;
+    reg [3:0] nthbit=0;
+    reg [11:0] is216;
+    always @(posedge clk) begin
+        out <= (load || active) ? 16'h8000 : 16'h0000;
+
+        if ((active==0) && (load == 1)) begin
+            active <= 1;
+            is216  <= 1;
+            nthbit <= 0;
+            uart   <= 0;
+            to_send <= in[7:0];
+        end
+        else if (active==1) begin
+            is216 <= (is216 == 216) ? 0 : is216 + 1;
+            nthbit <= (is216 == 216) ? nthbit + 1 : nthbit;
+            case (nthbit)
+                0 : uart <= 0;
+                1 : uart <= to_send[0];
+                2 : uart <= to_send[1];
+                3 : uart <= to_send[2];
+                4 : uart <= to_send[3];
+                5 : uart <= to_send[4];
+                6 : uart <= to_send[5];
+                7 : uart <= to_send[6];
+                8 : uart <= to_send[7];
+                9 : uart <= 1;
+                10 : begin active <= 0; out <= 16'h0000; end
+            endcase
+        end
+    end
+    assign TX = uart;
 
 endmodule