nand2/05_Computer_Architecture/Clock25_Reset20.v

28 lines
761 B
Verilog

/**
* Uses CLK of 100MHz to generate:
* internal clock signal clk with 25MHz and
* a reset signal of approx. 20us length
*/
`default_nettype none
module Clock25_Reset20(
input CLK, // external clock 100 MHz
output reg clk, // internal clock 25 Mhz
output reg reset // reset signal approx. 20us
);
// Put your code here:
reg boot=1;
reg [3:0] ccount=0;
reg [12:0] rcount=0;
always @(posedge CLK) begin
if (boot == 1) begin
boot <= (rcount == 4095) ? 0 : 1;
rcount <= (rcount == 4095) ? 0 : rcount + 1;
reset <= (rcount >= 2048) ? 0 : 1;
end
ccount <= (ccount == 3) ? 0 : ccount + 1;
clk <= (ccount >= 2) ? 1 : 0;
end
endmodule