31 lines
380 B
Verilog
31 lines
380 B
Verilog
`timescale 10ns/1ns
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`default_nettype none
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module HACK_tb();
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// IN,OUT
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reg CLK = 1;
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reg [1:0] BUT = 0;
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wire [1:0] LED;
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// Part
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HACK HACK(
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.CLK(CLK),
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.BUT(BUT),
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.LED(LED)
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);
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// Simulate
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always #500 BUT <= BUT+1;
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// Test
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always #0.5 CLK = ~CLK;
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initial begin
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$dumpfile("HACK_tb.vcd");
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$dumpvars(0, HACK_tb);
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#4000
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$finish;
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end
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endmodule
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