33 lines
677 B
Verilog
33 lines
677 B
Verilog
/**
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* 9 bit Shiftregister (shifts to right)
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* if (load == 1) out[t+1] = in[t]
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* else if (shift == 1) out[t+1] = out[t]>>1 | (inMSB<<8)
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* (shift one position to right and insert inMSB as most significant bit)
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*/
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`default_nettype none
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module BitShift9R(
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input clk,
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input [8:0] in,
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input inMSB,
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input load,
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input shift,
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output [8:0] out
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);
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// Put your code here:
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reg [8:0] reg9;
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always @(posedge clk) begin
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if (load == 1) begin
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reg9[7:0] = in[7:0];
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end
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else if (shift == 1 ) begin
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reg9[7:0] = reg9[8:1];
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reg9[8] = inMSB;
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end
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end
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assign out = reg9;
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endmodule
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