nand2/03_Sequential_Logic/BitShift9R.v

/**
* 9 bit Shiftregister (shifts to right)
* if      (load == 1)  out[t+1] = in[t]
* else if (shift == 1) out[t+1] = out[t]>>1 | (inMSB<<8)
* (shift one position to right and insert inMSB as most significant bit)
*/

`default_nettype none
module BitShift9R(
    input clk,
    input [8:0] in,
    input inMSB,
    input load,
    input shift,
    output [8:0] out
);

    // Put your code here:
    reg [8:0] reg9;

    always @(posedge clk) begin
        if (load == 1) begin
            reg9[7:0] = in[7:0];
        end
        else if (shift == 1 ) begin
            reg9[7:0] = reg9[8:1];
            reg9[8] = inMSB;
        end
    end

    assign out = reg9;
endmodule