22 lines
433 B
Verilog
22 lines
433 B
Verilog
/**
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* 1-bit register:
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* If load[t] == 1 then out[t+1] = in[t]
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* else out does not change (out[t+1] = out[t])
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*/
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`default_nettype none
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module Bit(
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input clk,
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input in,
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input load,
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output out
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);
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// Put your code here:
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wire muxout;
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// Mux(a=dffout, b=in, sel=load, out=muxout);
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// DFF(in=muxout, out=out, out=dffout);
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Mux MUX(out, in, load, muxout);
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DFF DFF(clk, muxout, out);
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endmodule
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