nand2/03_Sequential_Logic/Bit.v

/**
 * 1-bit register:
 * If load[t] == 1 then out[t+1] = in[t]
 *    else out does not change (out[t+1] = out[t])
 */

`default_nettype none
module Bit(
    input clk,
    input in,
    input load,
    output out
);

    // Put your code here:
    wire muxout;
    // Mux(a=dffout, b=in, sel=load, out=muxout);
    // DFF(in=muxout, out=out, out=dffout);
    Mux MUX(out, in, load, muxout);
    DFF DFF(clk, muxout, out);
endmodule