25 lines
289 B
Verilog
25 lines
289 B
Verilog
`default_nettype none
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module blinky_tb();
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// IN,OUT
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reg CLK=1;
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wire[1:0] LED;
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// Part
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blinky blinky(
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.CLK(CLK),
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.LED(LED)
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);
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// Simulate
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always #1 CLK=~CLK;
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initial begin
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$dumpfile("blinky_tb.vcd");
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$dumpvars(0, blinky_tb);
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#100000
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$finish;
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end
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endmodule
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