nand2/03_Sequential_Logic/08_blinky/blinky_tb.v

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2023-01-11 10:13:09 +00:00
`default_nettype none
module blinky_tb();
// IN,OUT
reg CLK=1;
wire[1:0] LED;
// Part
blinky blinky(
.CLK(CLK),
.LED(LED)
);
// Simulate
always #1 CLK=~CLK;
initial begin
$dumpfile("blinky_tb.vcd");
$dumpvars(0, blinky_tb);
#100000
$finish;
end
endmodule