13 lines
181 B
Verilog
13 lines
181 B
Verilog
`default_nettype none
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module top(
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input BUT1,
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input BUT2,
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output LED1,
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output LED2
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);
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Buffer BUFFER1(.in(BUT1),.out(LED1));
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Buffer BUFFER2(.in(BUT2),.out(LED2));
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endmodule
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