bootloader test dump

03_Sequential_Logic/Register.v

@@ -30,4 +30,8 @@ module Register(
     Bit BITN(clk, in[13], load, out[13]);
     Bit BITO(clk, in[14], load, out[14]);
     Bit BITP(clk, in[15], load, out[15]);
+	// reg [15:0] out = 0;
+	// always @(posedge clk)
+	// 	out <= load?in:out;
+	// initial out = 0;
 endmodule