From e2fa3ee864183494c5b72c6eda4ef4c77dd3b273 Mon Sep 17 00:00:00 2001 From: Konarak Date: Sat, 23 Nov 2024 16:56:29 +0530 Subject: [PATCH] bootloader test dump --- 01_Boolean_Logic/Mux8Way16.v | 15 +- 03_Sequential_Logic/Register.v | 4 + 04_Machine_Language/Makefile | 2 +- 04_Machine_Language/leds.asm | 4 +- 05_Computer_Architecture/CPU.v | 5 - 05_Computer_Architecture/Clock25_Reset20.v | 2 +- 06_IO_Devices/03_SPI/cat.asm | 226 ++++++++++----------- 06_IO_Devices/04_SRAM/buffer.asm | 182 +++++++++++++++++ 06_IO_Devices/05_GO/boot.asm | 167 +++++++++++++++ 06_IO_Devices/HACK.v | 70 ++++--- 06_IO_Devices/SRAM_D.v | 44 ++-- 11 files changed, 538 insertions(+), 183 deletions(-) diff --git a/01_Boolean_Logic/Mux8Way16.v b/01_Boolean_Logic/Mux8Way16.v index 2f64ff3..4620965 100644 --- a/01_Boolean_Logic/Mux8Way16.v +++ b/01_Boolean_Logic/Mux8Way16.v @@ -14,7 +14,7 @@ module Mux8Way16( input [15:0] f, input [15:0] g, input [15:0] h, - input [2:0] sel, + input [2:0] sel, output [15:0] out ); @@ -35,4 +35,17 @@ module Mux8Way16( Mux16 MUX16F(outef[15:0], outgh[15:0], sel[1], outefgh[15:0]); Mux16 MUX16(outabcd[15:0], outefgh[15:0], sel[2], out[15:0]); + // always @(*) begin + // case (sel) + // 0 : out = a; + // 1 : out = b; + // 2 : out = c; + // 3 : out = d; + // 4 : out = e; + // 5 : out = f; + // 6 : out = g; + // 7 : out = h; + // endcase + // end + endmodule diff --git a/03_Sequential_Logic/Register.v b/03_Sequential_Logic/Register.v index 47308f1..fa70967 100644 --- a/03_Sequential_Logic/Register.v +++ b/03_Sequential_Logic/Register.v @@ -30,4 +30,8 @@ module Register( Bit BITN(clk, in[13], load, out[13]); Bit BITO(clk, in[14], load, out[14]); Bit BITP(clk, in[15], load, out[15]); + // reg [15:0] out = 0; + // always @(posedge clk) + // out <= load?in:out; + // initial out = 0; endmodule diff --git a/04_Machine_Language/Makefile b/04_Machine_Language/Makefile index 1d018e2..f5bc713 100644 --- a/04_Machine_Language/Makefile +++ b/04_Machine_Language/Makefile @@ -1,4 +1,4 @@ -PYTHON = /bin/python3.11 +PYTHON = /usr/bin/python3.11 leds: $(PYTHON) ../tools/Assembler/assembler.pyc leds.asm diff --git a/04_Machine_Language/leds.asm b/04_Machine_Language/leds.asm index 2766dc2..dcf0f3a 100644 --- a/04_Machine_Language/leds.asm +++ b/04_Machine_Language/leds.asm @@ -5,8 +5,8 @@ // Put your code here: @BUT -D=M +D=!M @LED -M=!D +M=D @0 0;JMP diff --git a/05_Computer_Architecture/CPU.v b/05_Computer_Architecture/CPU.v index eafbd75..93653fd 100644 --- a/05_Computer_Architecture/CPU.v +++ b/05_Computer_Architecture/CPU.v @@ -54,21 +54,16 @@ module CPU( wire [15:0] fromAorM; wire [15:0] fromALU; - reg [15:0] tempM; - reg [15:0] tempPC; - assign is_C = instruction[15] & instruction[14] & instruction[13]; assign is_A = ~is_C; - assign loadD = is_C & instruction[4]; assign loadA = (is_C & instruction[5]) || is_A; assign fromAorM = instruction[12] ? inM : fromA; assign toA = is_A ? instruction : outM; - // jump if j1 bit set and ng bit set // jump if j2 bit set and zr bit set // jump if j3 bit set and zr, ng bit not set diff --git a/05_Computer_Architecture/Clock25_Reset20.v b/05_Computer_Architecture/Clock25_Reset20.v index 16f1378..62a2cea 100644 --- a/05_Computer_Architecture/Clock25_Reset20.v +++ b/05_Computer_Architecture/Clock25_Reset20.v @@ -13,7 +13,7 @@ module Clock25_Reset20( // Put your code here: reg boot=1; reg [3:0] ccount=0; - reg [12:0] rcount=0; + reg [11:0] rcount=0; always @(posedge CLK) begin if (boot == 1) begin diff --git a/06_IO_Devices/03_SPI/cat.asm b/06_IO_Devices/03_SPI/cat.asm index b9fa1c7..3af5838 100644 --- a/06_IO_Devices/03_SPI/cat.asm +++ b/06_IO_Devices/03_SPI/cat.asm @@ -5,131 +5,92 @@ // // Put your code here: -@171 -D=A -@SPI -M=D -@21 -D=A -@COUNT -M=D -(DECR) -@COUNT -DM=M-1 -@DECR -D;JGT -@3 -D=A -@SPI -M=D -(WAIT10) -@SPI -D=M -@WAIT10 -D;JLT -@4 -D=A -@SPI -M=D -(WAIT11) -@SPI -D=M -@WAIT11 -D;JLT -@SPI -M=0 -(WAIT12) -@SPI -D=M -@WAIT12 -D;JLT -@SPI -M=0 -(WAIT13) -@SPI -D=M -@WAIT13 -D;JLT -//(WAIT14) -//@SPI -//D=M -//@WAIT14 -//D;JLT -//@SPI -//D=M -//@128 -//M=D +// D=M -> 1111110000010000 +// M=D -> 1110001100001000 +// M=0 -> 1110101010001000 -@4 -D=A -@SPI -M=D -(WAIT21) -@SPI -D=M -@WAIT21 -D;JLT -@SPI -M=0 -(WAIT22) -@SPI -D=M -@WAIT22 -D;JLT -@SPI -M=1 -(WAIT23) -@SPI -D=M -@WAIT23 -D;JLT -@SPI -D=M -@129 -M=D -@4 -D=A -@SPI -M=D -(WAIT31) -@SPI -D=M -@WAIT31 -D;JLT -@SPI -M=0 -(WAIT32) -@SPI -D=M -@WAIT32 -D;JLT -@2 -D=A -@SPI -M=D -(WAIT33) -@SPI -D=M -@WAIT33 -D;JLT -@SPI -D=M -@130 -M=D - start +// read data starting at address +// 0x03 0x04 0x00 0x00 + @3 + D=A + @128 + M=D + @4 + D=A + @129 + M=D + @130 + M=0 + @131 + M=0 + +// wake up from deep power down and wait 3us +// 0xAB + @171 + D=A + @SPI + M=D + @4 + D=A + @COUNT + M=D + (DECR1) + @COUNT + DM=M-1 + @DECR1 + D;JGT + @511 + D=A + @SPI + M=D + @21 + D=A + @COUNT + M=D + (DECR2) + @COUNT + DM=M-1 + @DECR2 + D;JGT + +//command stack base address @128 D=A - @CHARBOOT + @CHARREAD M=D - @BOOT + @READCOUNT + M=0 + @WAITREAD 0;JEQ -(POLL) - @BUT - D=!M - @LED +(WAITREAD) + @SPI + D=M + @WAITREAD + D;JLT + @READ + 0;JMP + +(READ) + // read + @CHARREAD + A=M + D=M + @SPI M=D - @POLL + @CHARREAD + M=M+1 + @132 + D=A + @CHARREAD + D=D-M + @WAITREAD + D;JGT + @ENDREAD + 0;JMP + +(ENDREAD) + @WAITBOOT 0;JMP (WAITBOOT) @@ -141,16 +102,26 @@ M=D 0;JMP (BOOT) - @CHARBOOT - A=M + @SPI + M=0 + @4 + D=A + @COUNT + M=D + (FROMSPI) + @COUNT + DM=M-1 + @FROMSPI + D;JGT + @SPI D=M @UART_TX M=D - @CHARBOOT + @READCOUNT M=M+1 - @131 + @4 D=A - @CHARBOOT + @READCOUNT D=D-M @ENDBOOT D;JEQ @@ -160,3 +131,12 @@ M=D (ENDBOOT) @POLL 0;JMP + +// LED<->BUT loop +(POLL) + @BUT + D=!M + @LED + M=D + @POLL + 0;JMP diff --git a/06_IO_Devices/04_SRAM/buffer.asm b/06_IO_Devices/04_SRAM/buffer.asm index 5fbdf07..7f52e2f 100644 --- a/06_IO_Devices/04_SRAM/buffer.asm +++ b/06_IO_Devices/04_SRAM/buffer.asm @@ -5,3 +5,185 @@ // the string to UART_TX // // Put your code here: +// cat.asm +// +// load spi flash rom starting at address 0x040000 and write the +// data to UART_TX +// +// Put your code here: + +// D=M -> 1111110000010000 +// M=D -> 1110001100001000 +// M=0 -> 1110101010001000 + +// read data starting at address +// 0x03 0x04 0x00 0x00 + @3 + D=A + @128 + M=D + @4 + D=A + @129 + M=D + @130 + M=0 + @131 + M=0 + +// wake up from deep power down and wait 3us +// 0xAB + @171 + D=A + @SPI + M=D + @4 + D=A + @COUNT + M=D + (DECR1) + @COUNT + DM=M-1 + @DECR1 + D;JGT + @511 + D=A + @SPI + M=D + @21 + D=A + @COUNT + M=D + (DECR2) + @COUNT + DM=M-1 + @DECR2 + D;JGT + +//command stack base address + @128 + D=A + @CHARREAD + M=D + @WRITECOUNT + M=0 + @SENDCOUNT + M=0 + @WAITREAD + 0;JEQ + +(WAITREAD) + @SPI + D=M + @WAITREAD + D;JLT + @READ + 0;JMP + +(READ) + // read + @CHARREAD + A=M + D=M + @SPI + M=D + @CHARREAD + M=M+1 + @132 + D=A + @CHARREAD + D=D-M + @WAITREAD + D;JGT + @ENDREAD + 0;JMP + +(ENDREAD) + @WAITWRITE + 0;JMP + +(WAITWRITE) + @SPI + D=M + @WAITWRITE + D;JLT + @WRITE + 0;JMP + +(WRITE) + @SPI + M=0 + @4 + D=A + @COUNT + M=D + (FROMSPI) + @COUNT + DM=M-1 + @FROMSPI + D;JGT + @WRITECOUNT + D=M + @SRAM_A + M=D + @SPI + D=M + @SRAM_D + M=D + @WRITECOUNT + M=M+1 + @8 + D=A + @WRITECOUNT + D=D-M + @ENDWRITE + D;JEQ + @WAITWRITE + 0;JMP + +(ENDWRITE) + @WAITBOOT + 0;JMP + + +(WAITBOOT) + @UART_TX + D=M + @BOOT + D;JEQ + @WAITBOOT + 0;JMP + +(BOOT) + @SENDCOUNT + D=M + @SRAM_A + M=D + @SRAM_D + D=M + @UART_TX + M=D + @SENDCOUNT + M=M+1 + @8 + D=A + @SENDCOUNT + D=D-M + @ENDBOOT + D;JEQ + @WAITBOOT + 0;JMP + +(ENDBOOT) + @POLL + 0;JMP + + +// LED<->BUT loop +(POLL) + @BUT + D=!M + @LED + M=D + @POLL + 0;JMP diff --git a/06_IO_Devices/05_GO/boot.asm b/06_IO_Devices/05_GO/boot.asm index 5fc5705..2f39a75 100644 --- a/06_IO_Devices/05_GO/boot.asm +++ b/06_IO_Devices/05_GO/boot.asm @@ -3,3 +3,170 @@ //***************************************************************************** // // Put your code here: + +// read data starting at address +// 0x03 0x01 0x00 0x00 + @3 + D=A + @100 + M=D + @1 + D=A + @101 + M=D + @102 + M=0 + @103 + M=0 + +// wake up from deep power down and wait 3us +// 0xAB + @171 + D=A + @SPI + M=D + @4 + D=A + @COUNT + M=D + (DECR1) + @COUNT + DM=M-1 + @DECR1 + D;JGT + @511 + D=A + @SPI + M=D + @21 + D=A + @COUNT + M=D + (DECR2) + @COUNT + DM=M-1 + @DECR2 + D;JGT + +//command stack base address + @100 + D=A + @READCOMMAND + M=D + @DIRECTION + M=0 + @WORDCOUNT + M=0 + @WAITREAD + 0;JEQ + +(WAITREAD) + @SPI + D=M + @WAITREAD + D;JLT + @READ + 0;JMP + +(READ) + // read + @READCOMMAND + A=M + D=M + @SPI + M=D + @READCOMMAND + M=M+1 + @104 + D=A + @READCOMMAND + D=D-M + @WAITREAD + D;JGT + @ENDREAD + 0;JMP + +(ENDREAD) + @WAITWRITE + 0;JMP + +(WAITWRITE) + @SPI + D=M + @WAITWRITE + D;JLT + @WRITE + 0;JMP + +(WRITE) + @SPI + M=0 + @4 + D=A + @COUNT + M=D + (FROMSPI) + @COUNT + DM=M-1 + @FROMSPI + D;JGT + @DIRECTION + D=M + @WESTWORD + D;JEQ + @EASTWORD + D;JGT + +(WESTWORD) + @SPI + D=M + @R13 + M=D + DM=D+M + DM=D+M + DM=D+M + DM=D+M + DM=D+M + DM=D+M + DM=D+M + DM=D+M + @DIRECTION + M=1 + @WAITWRITE + 0;JMP + +(EASTWORD) + @WORDCOUNT + D=M + @SRAM_A + M=D + @SPI + D=M + @R14 + M=D + @R13 + D=M + @R14 + D=D+M + @SRAM_D + M=D + @DIRECTION + M=0 + @WORDCOUNT + M=M+1 + @6 + D=A + @WORDCOUNT + D=D-M + @ENDWRITE + D;JEQ + @WAITWRITE + 0;JMP + +(ENDWRITE) + @185 + D=A + @SPI + M=D + @GO + M=1 diff --git a/06_IO_Devices/HACK.v b/06_IO_Devices/HACK.v index 947419d..83c474d 100644 --- a/06_IO_Devices/HACK.v +++ b/06_IO_Devices/HACK.v @@ -61,11 +61,11 @@ module HACK( wire [15:0] inIO5; wire [15:0] inIO6; wire [15:0] inIO7; - wire [15:0] inIO8=0; - wire [15:0] inIO9=0; + wire [15:0] inIO8; + wire [15:0] inIO9; wire [15:0] inIOA=0; - wire [15:0] inIOB=0; - wire [15:0] inIOC=0; + wire [15:0] inIOB; + wire [15:0] inIOC; wire [15:0] inIOD=0; wire [15:0] inIOE=0; wire [15:0] inIOF=0; @@ -77,29 +77,32 @@ module HACK( wire [15:0] addressM; wire [15:0] pc; - wire clk, reset; + wire clk, reset, RESET; wire [15:0] ROM_DATA; wire [15:0] fromLCD; - //wire [15:0] outDEBUG0; - //wire [15:0] outDEBUG1; + wire [15:0] outDEBUG0; + wire [15:0] outDEBUG1; //wire [15:0] outDEBUG2; - //wire loadDEBUG0; - //wire loadDEBUG1; + wire loadDEBUG0; + wire loadDEBUG1; //wire loadDEBUG2; // Put your code here: - //assign SRAM_ADDR[17:16]=2'b0; + wire [15:0] fromGO; + assign SRAM_ADDR[17:16]=2'b0; + assign SRAM_ADDR[15:0]=fromGO; assign LED[1:0] = inIO0[1:0]; assign inIO8 = fromLCD; assign inIO9 = fromLCD; - //assign outDEBUG0 = inIOB; - //assign outDEBUG1 = inIOC; + assign outDEBUG0 = inIOB; + assign outDEBUG1 = inIOC; //assign outDEBUG2 = inIOD; //assign loadDEBUG0 = loadIOB; //assign loadDEBUG1 = loadIOC; //assign loadDEBUG2 = loadIOD; Clock25_Reset20 CLKR(CLK, clk, reset); - CPU CPU(clk, inM, instruction, reset, outM, writeM, addressM, pc); + Or OR(reset, loadIO7, RESET); + CPU CPU(clk, inM, instruction, RESET, outM, writeM, addressM, pc); Memory Memory(addressM, writeM, inM, loadRAM, loadIO0, loadIO1, loadIO2, loadIO3, loadIO4, loadIO5, loadIO6, loadIO7, @@ -107,7 +110,7 @@ module HACK( inRAM, inIO0, inIO1, inIO2, inIO3, inIO4, inIO5, inIO6, inIO7, inIO8, inIO9, inIOA, inIOB, inIOC, inIOD, inIOE, inIOF); - ROM ROM(pc, instruction); + ROM ROM(pc, ROM_DATA); RAM3840 RAM(clk, addressM[11:0], outM, loadRAM, inRAM); Register LED12(clk, outM, loadIO0, inIO0); @@ -117,13 +120,24 @@ module HACK( UartRX UartRX(clk, loadIO3, UART_RX, inIO3); SPI SPI(clk, loadIO4, outM, inIO4, SPI_CSX, SPI_SDO, SPI_SDI, SPI_SCK); - //GO GO(clk, loadIO5, pc, inIO6, SRAM_ADDR[15:0], inIO7, ROM_DATA, instruction); - //Register SRAM_A(clk, outM, loadIO0, inIO6); - //SRAM_D SRAM_D(clk, loadIO7, outM, inIO7, SRAM_DATA, SRAM_CSX, SRAM_OEX, SRAM_WEX); - //LCD LCD(clk, loadIO8, loadIO9, outM, fromLCD, LCD_DCX, LCD_CSX, LCD_SDO, LCD_SCK); - //Register DEBUG0(clk, outM, loadIOB, inIOB); - //Register DEBUG1(clk, outM, loadIOC, inIOC); + // if loadIO7=1 then instruction = SRAM_DATA/inIO6 otherwise output ROM_DATA + //GO GO(clk, loadIO7, pc, inIO5, SRAM_ADDR[15:0], inIO6, ROM_DATA, instruction); + reg load_sram=0; + always @(posedge clk) begin + if (loadIO7) begin + load_sram <= 1; + end + end + + Mux16 SWITCHA(inIO5, pc, load_sram, fromGO); + Mux16 SWITCHD(ROM_DATA, inIO6, load_sram, instruction); + Register SRAM_A(clk, outM, loadIO5, inIO5); + SRAM_D SRAM_D(clk, loadIO6, outM, inIO6, SRAM_DATA, SRAM_CSX, SRAM_OEX, SRAM_WEX); + LCD LCD(clk, loadIO8, loadIO9, outM, fromLCD, LCD_DCX, LCD_CSX, LCD_SDO, LCD_SCK); + + Register DEBUG0(clk, outM, loadIOB, inIOB); + Register DEBUG1(clk, outM, loadIOC, inIOC); //Register DEBUG2(clk, outM, loadIOD, inIOD); //Register DEBUG3(clk, outM, loadIOE, inIOE); //Register DEBUG4(clk, outM, loadIOF, inIOF); @@ -132,14 +146,14 @@ module HACK( //assign SPI_SCK=0; //assign SPI_CSX=0; -assign SRAM_DATA=0; -assign SRAM_WEX=0; -assign SRAM_OEX=0; -assign SRAM_CSX=0; -assign LCD_DCX=0; -assign LCD_SDO=0; -assign LCD_SCK=0; -assign LCD_CSX=0; +//assign SRAM_DATA=0; +//assign SRAM_WEX=0; +//assign SRAM_OEX=0; +//assign SRAM_CSX=0; +//assign LCD_DCX=0; +//assign LCD_SDO=0; +//assign LCD_SCK=0; +//assign LCD_CSX=0; assign RTP_SDO=0; assign RTP_SCK=0; endmodule diff --git a/06_IO_Devices/SRAM_D.v b/06_IO_Devices/SRAM_D.v index 686e11a..eac7db0 100644 --- a/06_IO_Devices/SRAM_D.v +++ b/06_IO_Devices/SRAM_D.v @@ -15,33 +15,33 @@ module SRAM_D( input [15:0] in, output [15:0] out, inout [15:0] DATA, // SRAM data 16 Bit - output CSX, // SRAM chip_enable_not - output OEX, // SRAM output_enable_not - output WEX // SRAM write_enable_not + output reg CSX=0, // SRAM chip_enable_not + output reg OEX, // SRAM output_enable_not + output reg WEX // SRAM write_enable_not ); // Put your code here: - wire LOAD; - wire [15:0] to_sram; - // always @(posedge clk) begin - // if (load) begin - // OEX <= 1; - // WEX <= 0; - // //to_sram <= in; - // end else begin - // OEX <= 0; - // WEX <= 1; - // end - // end - assign CSX = 0; - assign OEX = (LOAD) ? 1 : 0; - assign WEX = (LOAD) ? 0 : 1; - - DFF DFF(clk, load, LOAD); - Register Register(clk, in, load, to_sram); + reg [15:0] to_sram; + always @(posedge clk) begin + if (load) begin + OEX <= 1; + WEX <= 0; + to_sram <= in; + end else begin + OEX <= 0; + WEX <= 1; + end + end + // wire LOAD; + // wire [15:0] to_sram; + // assign CSX = 0; + // assign OEX = (LOAD) ? 1 : 0; + // assign WEX = (LOAD) ? 0 : 1; + // DFF DFF(clk, load, LOAD); + // Register Register(clk, in, load, to_sram); + InOut InOut(DATA, to_sram, out, OEX); //if (dir == 0) IN: PIN are set to High-Z, dataR = external PIN //if (dir == 1) OUTPUT: dataW is output to external PIN, dataR = dataW - InOut InOut(DATA, to_sram, out, OEX); endmodule