added v2.0
This commit is contained in:
Michael Schröder
BIN
06_IO_Devices/00_HACK/HACK.dia
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BIN
06_IO_Devices/00_HACK/HACK.dia
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Binary file not shown.
BIN
06_IO_Devices/00_HACK/HACK.png
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BIN
06_IO_Devices/00_HACK/HACK.png
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After Width: | Height: | Size: 100 KiB |
72
06_IO_Devices/00_HACK/HACK_tb.gtkw
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72
06_IO_Devices/00_HACK/HACK_tb.gtkw
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Thu Dec 29 16:29:18 2022
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[*]
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[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/00_HACK/HACK_tb.vcd"
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[dumpfile_mtime] "Thu Dec 29 16:28:24 2022"
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[dumpfile_size] 83632917
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[savefile] "/home/micha/gitlab/nand2tetris-fpga/06_IO_Devices/00_HACK/HACK_tb.gtkw"
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[timestart] 281880000
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[size] 1920 963
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[pos] -1 -1
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*-24.000000 40600000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] HACK_tb.
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[sst_width] 281
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[signals_width] 180
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[sst_expanded] 1
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[sst_vpaned_height] 259
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@200
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-GPIO
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@28
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HACK_tb.BUT[1:0]
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HACK_tb.LED[1:0]
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@200
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-UART
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@28
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HACK_tb.UART_TX
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HACK_tb.UART_RX
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@200
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-SPI
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@28
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HACK_tb.SPI_CSX
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HACK_tb.SPI_SDI
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HACK_tb.SPI_SDO
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HACK_tb.SPI_SCK
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@200
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-SRAM
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@22
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HACK_tb.SRAM_ADDR[17:0]
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@28
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HACK_tb.SRAM_CSX
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HACK_tb.SRAM_OEX
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HACK_tb.SRAM_WEX
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@22
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HACK_tb.SRAM_DATA[15:0]
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@200
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-GO
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@28
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HACK_tb.HACK.loadGO
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@200
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-DEBUG
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@28
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HACK_tb.HACK.loadDEBUG0
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@820
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HACK_tb.HACK.outDEBUG0[15:0]
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@28
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HACK_tb.HACK.loadDEBUG1
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@24
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HACK_tb.HACK.outDEBUG1[15:0]
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@28
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HACK_tb.HACK.loadDEBUG2
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@24
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HACK_tb.HACK.outDEBUG2[15:0]
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@28
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HACK_tb.HACK.loadDEBUG3
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@24
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HACK_tb.HACK.outDEBUG3[15:0]
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@28
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HACK_tb.HACK.loadDEBUG4
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@24
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HACK_tb.HACK.outDEBUG4[15:0]
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[pattern_trace] 1
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[pattern_trace] 0
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121
06_IO_Devices/00_HACK/HACK_tb.v
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121
06_IO_Devices/00_HACK/HACK_tb.v
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`timescale 10ns/1ns
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`default_nettype none
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module HACK_tb();
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// IN,OUT
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reg CLK = 1;
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reg [1:0] BUT = 3;
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wire [1:0] LED;
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wire UART_TX;
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wire UART_RX;
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wire SPI_SDO;
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wire SPI_SDI;
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wire SPI_SCK;
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wire SPI_CSX;
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wire [17:0] SRAM_ADDR;
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wire [15:0] SRAM_DATA;
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wire SRAM_WEX;
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wire SRAM_OEX;
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wire SRAM_CSX;
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wire LCD_DCX;
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wire LCD_SDO;
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wire LCD_SCK;
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wire LCD_CSX;
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reg RTP_SDI;
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wire RTP_SDO;
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wire RTP_SCK;
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// Part
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HACK HACK(
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.CLK(CLK), // external clock 100 MHz
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.BUT(BUT), // user button ("pushed down" == 0) ("up" == 1)
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.LED(LED), // leds (0 off, 1 on)
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.UART_RX(UART_RX), // UART receive
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.UART_TX(UART_TX), // UART transmit
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.SPI_SDO(SPI_SDO), // SPI serial data out
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.SPI_SDI(SPI_SDI), // SPI serial data in
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.SPI_SCK(SPI_SCK), // SPI serial clock
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.SPI_CSX(SPI_CSX), // SPI chip select not
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.SRAM_ADDR(SRAM_ADDR), // SRAM address 18 Bit = 256K
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.SRAM_DATA(SRAM_DATA), // SRAM data 16 Bit
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.SRAM_WEX(SRAM_WEX), // SRAM write_enable_not
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.SRAM_OEX(SRAM_OEX), // SRAM output_enable_not
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.SRAM_CSX(SRAM_CSX), // SRAM chip_select_not
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.LCD_DCX(LCD_DCX), // LCD data/command not
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.LCD_SDO(LCD_SDO), // LCD serial data out
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.LCD_SCK(LCD_SCK), // LCD serial clock
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.LCD_CSX(LCD_CSX), // LCD chip select not
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.RTP_SDI(RTP_SDI), // RTP serial data in
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.RTP_SDO(RTP_SDO), // RTP serial data out in
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.RTP_SCK(RTP_SCK) // RTP serial clock
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);
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// Simulate
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always #0.5 CLK = ~CLK;
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integer n=0;
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always @(posedge CLK) n=n+1;
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// Compare
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reg [9:0] uart=10'b1111111111;
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reg [15:0] baudrate = 0;
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always @(posedge CLK)
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baudrate <= ((baudrate==866)?0:baudrate+1);
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always @(posedge CLK) begin
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uart <= (n==5000)?((82<<2)+1):(n==15000)?((88<<2)+1):((baudrate==866)?{1'b1,uart[9:1]}:uart);
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end
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wire shift = (baudrate==866);
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assign UART_RX = uart[0];
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//Simulate SPI
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reg spi_sleep=1;
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reg [31:0] spi_cmd=0;
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reg [95:0] spi=0;
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assign SPI_SDI = (SPI_CSX | spi_sleep) ? 1'bz:spi[95];
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always @(posedge (SPI_SCK))
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spi <= {spi[95:0],1'b0};
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always @(posedge (SPI_SCK))
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spi_cmd <= {spi_cmd[30:0],SPI_SDO};
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always @(negedge (SPI_CSX))
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spi_cmd <= 0;
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always @(spi_cmd) begin
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if (spi_cmd==32'h000000AB) spi_sleep <= 0;
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if (spi_cmd==32'h000000B9) spi_sleep <= 1;
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if (spi_cmd==32'h03040000) spi <= "SPI! 123";
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if (spi_cmd==32'h03010000) spi <= 96'h1001_FC10_1000_E308_0000_EA87;
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end
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//Simulate SRAM
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reg [16:0] sram[0:7];
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always @(posedge CLK)
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if (~SRAM_WEX&&SRAM_OEX&&~SRAM_CSX) sram[SRAM_ADDR] <= SRAM_DATA;
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assign SRAM_DATA = (~SRAM_CSX&&~SRAM_OEX)?sram[SRAM_ADDR]:16'bzzzzzzzzzzzzzzzz;
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//Simulate LCD
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reg [7:0] lcd_c;
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reg [15:0] lcd_d;
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always @(posedge LCD_SCK) begin
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lcd_c <= (~LCD_DCX)?{lcd_c[6:0],LCD_SDO}:lcd_c;
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lcd_d <= (LCD_DCX)?{lcd_d[6:0],LCD_SDO}:lcd_d;
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end
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always @(negedge LCD_CSX) begin
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lcd_c <= 0;
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lcd_d <= 0;
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end
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//simulate BUT
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always @(posedge CLK) begin
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if (n==10000) BUT<=0;
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if (n==20000) BUT<=1;
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if (n==30000) BUT<=2;
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end
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initial begin
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$dumpfile("HACK_tb.vcd");
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$dumpvars(0, HACK_tb);
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$display("------------------------");
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$display("Testbench: Hack");
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#40000
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$finish;
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end
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endmodule
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49
06_IO_Devices/00_HACK/Include.v
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49
06_IO_Devices/00_HACK/Include.v
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`include "../../01_Boolean_Logic/Nand.v"
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`include "../../01_Boolean_Logic/Not.v"
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`include "../../01_Boolean_Logic/Buffer.v"
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`include "../../01_Boolean_Logic/And.v"
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`include "../../01_Boolean_Logic/Or.v"
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`include "../../01_Boolean_Logic/Xor.v"
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`include "../../01_Boolean_Logic/Mux.v"
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`include "../../01_Boolean_Logic/DMux.v"
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`include "../../01_Boolean_Logic/Not16.v"
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`include "../../01_Boolean_Logic/Buffer16.v"
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`include "../../01_Boolean_Logic/And16.v"
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`include "../../01_Boolean_Logic/Or16.v"
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`include "../../01_Boolean_Logic/Mux16.v"
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`include "../../01_Boolean_Logic/Or8Way.v"
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`include "../../01_Boolean_Logic/Mux4Way16.v"
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`include "../../01_Boolean_Logic/Mux8Way16.v"
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`include "../../01_Boolean_Logic/DMux4Way.v"
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`include "../../01_Boolean_Logic/DMux8Way.v"
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`include "../../02_Boolean_Arithmetic/HalfAdder.v"
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`include "../../02_Boolean_Arithmetic/FullAdder.v"
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`include "../../02_Boolean_Arithmetic/Add16.v"
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`include "../../02_Boolean_Arithmetic/Inc16.v"
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`include "../../02_Boolean_Arithmetic/ALU.v"
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`include "../../03_Sequential_Logic/DFF.v"
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`include "../../03_Sequential_Logic/Bit.v"
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`include "../../03_Sequential_Logic/Register.v"
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`include "../../03_Sequential_Logic/PC.v"
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`include "../../03_Sequential_Logic/RAM256.v"
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`include "../../03_Sequential_Logic/RAM512.v"
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`include "../../03_Sequential_Logic/RAM3840.v"
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`include "../../03_Sequential_Logic/BitShift9R.v"
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`include "../../03_Sequential_Logic/BitShift8L.v"
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`include "../../05_Computer_Architecture/CPU.v"
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`include "../../05_Computer_Architecture/Memory.v"
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`include "../../05_Computer_Architecture/ROM.v"
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`include "../../05_Computer_Architecture/Clock25_Reset20.v"
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`include "../../06_IO_Devices/HACK.v"
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`include "../../06_IO_Devices/UartTX.v"
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`include "../../06_IO_Devices/UartRX.v"
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`include "../../06_IO_Devices/SPI.v"
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`include "../../06_IO_Devices/InOut.v"
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`include "../../06_IO_Devices/SRAM_D.v"
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`include "../../06_IO_Devices/GO.v"
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`include "../../06_IO_Devices/LCD.v"
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`include "../../06_IO_Devices/RTP.v"
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3
06_IO_Devices/00_HACK/apio.ini
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3
06_IO_Devices/00_HACK/apio.ini
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[env]
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board = iCE40-HX1K-EVB
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68
06_IO_Devices/00_HACK/iCE40HX1K-EVB.pcf
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68
06_IO_Devices/00_HACK/iCE40HX1K-EVB.pcf
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# physical constrain file
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# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40HX1K-EVB
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# compare to the schematic of the board and the datasheet of fpga
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set_io CLK 15 # SYSCLOCK 100 MHz
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set_io BUT[0] 41 # BUT1
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set_io BUT[1] 42 # BUT2
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set_io LED[0] 40 # LED1
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set_io LED[1] 51 # LED2
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set_io UART_RX 36 # PIO2_8/RxD connected to pin 3 of UEXT (PGM)
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set_io UART_TX 37 # PIO2_9/TxD connected to pin 4 of UEXT (PGM)
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set_io SPI_SDO 45 # iCE40-SDO
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set_io SPI_SDI 46 # iCE40-SDI
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set_io SPI_SCK 48 # iCE40-SCK
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set_io SPI_CSX 49 # iCE40-SS_B
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set_io SRAM_ADDR[0] 79 # SA0
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set_io SRAM_ADDR[1] 80 # SA1
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set_io SRAM_ADDR[2] 81 # SA2
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set_io SRAM_ADDR[3] 82 # SA3
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set_io SRAM_ADDR[4] 83 # SA4
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set_io SRAM_ADDR[5] 85 # SA5
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set_io SRAM_ADDR[6] 86 # SA6
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set_io SRAM_ADDR[7] 87 # SA7
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set_io SRAM_ADDR[8] 89 # SA8
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set_io SRAM_ADDR[9] 90 # SA9
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set_io SRAM_ADDR[10] 91 # SA10
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set_io SRAM_ADDR[11] 93 # SA11
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set_io SRAM_ADDR[12] 94 # SA12
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set_io SRAM_ADDR[13] 95 # SA13
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set_io SRAM_ADDR[14] 96 # SA14
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set_io SRAM_ADDR[15] 97 # SA15
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set_io SRAM_ADDR[16] 99 # SA16
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set_io SRAM_ADDR[17] 100 # SA17
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set_io SRAM_CSX 78 # SRAM_#CS
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set_io SRAM_OEX 74 # SRAM_#OE
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set_io SRAM_WEX 73 # SRAM_#WE
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set_io SRAM_DATA[0] 62 # SD0
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set_io SRAM_DATA[1] 63 # SD1
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set_io SRAM_DATA[2] 64 # SD2
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set_io SRAM_DATA[3] 65 # SD3
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set_io SRAM_DATA[4] 66 # SD4
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set_io SRAM_DATA[5] 68 # SD5
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set_io SRAM_DATA[6] 69 # SD6
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set_io SRAM_DATA[7] 71 # SD7
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set_io SRAM_DATA[8] 72 # SD8
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set_io SRAM_DATA[9] 60 # SD9
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set_io SRAM_DATA[10] 59 # SD10
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set_io SRAM_DATA[11] 57 # SD11
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set_io SRAM_DATA[12] 56 # SD12
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set_io SRAM_DATA[13] 54 # SD13
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set_io SRAM_DATA[14] 53 # SD14
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set_io SRAM_DATA[15] 52 # SD15
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set_io LCD_DCX 1 # PIO3_1A connected to pin 5 of GPIO1
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set_io LCD_SDO 2 # PIO3_1B connected to pin 7 of GPIO1
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set_io LCD_SCK 3 # PIO3_2A connected to pin 9 of GPIO1
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set_io LCD_CSX 4 # PIO3_2B connected to pin 11 of GPIO1
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set_io RTP_SDI 7 # PIO3_3A connected to pin 13 of GPIO1
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set_io RTP_SDO 8 # PIO3_3B connected to pin 15 of GPIO1
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set_io RTP_SCK 9 # PIO3_5A connected to pin 17 of GPIO1
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