added v2.0

05_Computer_Architecture/04_HACK/HACK_tb.gtkw

@@ -0,0 +1,42 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Mon Dec 12 16:41:42 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/05_Computer_Architecture/04_HACK/HACK_tb.vcd"
+[dumpfile_mtime] "Mon Dec 12 16:41:24 2022"
+[dumpfile_size] 5432004
+[savefile] "/home/micha/gitlab/nand2tetris/05_Computer_Architecture/04_HACK/HACK_tb.gtkw"
+[timestart] 0
+[size] 1673 487
+[pos] 118 133
+*-23.000000 50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] HACK_tb.
+[sst_width] 281
+[signals_width] 180
+[sst_expanded] 1
+[sst_vpaned_height] 98
+@200
+-IN
+@28
+HACK_tb.CLK
+HACK_tb.BUT[1:0]
+@200
+-OUT
+@28
+HACK_tb.LED[1:0]
+@200
+-DEBUG
+@28
+HACK_tb.HACK.loadDEBUG0
+@24
+HACK_tb.HACK.outDEBUG0[15:0]
+@28
+HACK_tb.HACK.loadDEBUG1
+@24
+HACK_tb.HACK.outDEBUG1[15:0]
+@28
+HACK_tb.HACK.loadDEBUG2
+@24
+HACK_tb.HACK.outDEBUG2[15:0]
+[pattern_trace] 1
+[pattern_trace] 0

05_Computer_Architecture/04_HACK/HACK_tb.v

@@ -0,0 +1,30 @@
+`timescale 10ns/1ns
+`default_nettype none
+module HACK_tb();
+
+	// IN,OUT
+	reg CLK = 1;
+	reg [1:0] BUT = 0;
+	wire [1:0] LED;
+
+	// Part
+	HACK HACK(
+    	.CLK(CLK),
+    	.BUT(BUT),
+    	.LED(LED)
+	);
+
+	// Simulate
+	always #500 BUT <= BUT+1;
+
+	// Test
+	always #0.5 CLK = ~CLK;
+	initial begin
+  		$dumpfile("HACK_tb.vcd");
+  		$dumpvars(0, HACK_tb);
+
+		#4000
+		$finish;
+	end
+
+endmodule

05_Computer_Architecture/04_HACK/Hack_tb.gtkw

@@ -0,0 +1,68 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Mon Nov 28 10:58:53 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/05_Computer_Architecture/03_HACK/Hack_tb.vcd"
+[dumpfile_mtime] "Mon Nov 28 10:58:25 2022"
+[dumpfile_size] 3140780
+[savefile] "/home/micha/gitlab/nand2tetris/05_Computer_Architecture/03_HACK/Hack_tb.gtkw"
+[timestart] 0
+[size] 1920 963
+[pos] -1 -1
+*-8.420643 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] Hack_tb.
+[treeopen] Hack_tb.HACK.
+[sst_width] 281
+[signals_width] 200
+[sst_expanded] 1
+[sst_vpaned_height] 261
+@28
+Hack_tb.HACK.clk
+@200
+-IN
+@28
+Hack_tb.RST
+Hack_tb.BUT
+@200
+-CPU
+@22
+Hack_tb.HACK.pc[15:0]
+Hack_tb.HACK.instruction[15:0]
+Hack_tb.HACK.CPU.regA[15:0]
+Hack_tb.HACK.CPU.regD[15:0]
+@200
+-MEM
+@22
+Hack_tb.HACK.MEMORY.address[15:0]
+@28
+Hack_tb.HACK.MEMORY.load
+@22
+Hack_tb.HACK.MEMORY.out[15:0]
+@200
+-OUT
+@28
+Hack_tb.LED[1:0]
+@200
+-DEBUG
+@28
+Hack_tb.HACK.loadDEBUG0
+@24
+Hack_tb.HACK.outDEBUG0[15:0]
+@28
+Hack_tb.HACK.loadDEBUG1
+@24
+Hack_tb.HACK.outDEBUG1[15:0]
+@28
+Hack_tb.HACK.loadDEBUG2
+@25
+Hack_tb.HACK.outDEBUG2[15:0]
+@28
+Hack_tb.HACK.loadDEBUG3
+@22
+Hack_tb.HACK.outDEBUG3[15:0]
+@28
+Hack_tb.HACK.loadDEBUG4
+@22
+Hack_tb.HACK.outDEBUG4[15:0]
+[pattern_trace] 1
+[pattern_trace] 0

05_Computer_Architecture/04_HACK/Include.v

@@ -0,0 +1,40 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+`include "../../01_Boolean_Logic/Mux4Way16.v"
+`include "../../01_Boolean_Logic/Mux8Way16.v"
+`include "../../01_Boolean_Logic/DMux4Way.v"
+`include "../../01_Boolean_Logic/DMux8Way.v"
+
+`include "../../02_Boolean_Arithmetic/HalfAdder.v"
+`include "../../02_Boolean_Arithmetic/FullAdder.v"
+`include "../../02_Boolean_Arithmetic/Add16.v"
+`include "../../02_Boolean_Arithmetic/Inc16.v"
+`include "../../02_Boolean_Arithmetic/ALU.v"
+
+`include "../../03_Sequential_Logic/DFF.v"
+`include "../../03_Sequential_Logic/Bit.v"
+`include "../../03_Sequential_Logic/Register.v"
+`include "../../03_Sequential_Logic/PC.v"
+`include "../../03_Sequential_Logic/RAM256.v"
+`include "../../03_Sequential_Logic/RAM512.v"
+`include "../../03_Sequential_Logic/RAM3840.v"
+`include "../../03_Sequential_Logic/BitShift9R.v"
+`include "../../03_Sequential_Logic/BitShift8L.v"
+
+`include "../../05_Computer_Architecture/CPU.v"
+`include "../../05_Computer_Architecture/Memory.v"
+`include "../../05_Computer_Architecture/ROM.v"
+`include "../../05_Computer_Architecture/Clock25_Reset20.v"
+`include "../../05_Computer_Architecture/HACK.v"

05_Computer_Architecture/04_HACK/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

05_Computer_Architecture/04_HACK/iCE40HX1K.pcf

@@ -0,0 +1,11 @@
+# physical constrain file
+# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB
+# compare to the schematic of the board and the datasheet of fpga
+
+set_io CLK 15
+set_io BUT[0] 41
+set_io BUT[1] 42
+
+set_io LED[0] 40
+set_io LED[1] 51
+