added v2.0

05_Computer_Architecture/03_Clock25_Reset20/Clock25_Reset20_tb.gtkw

@@ -0,0 +1,23 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 29 21:52:20 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/05_Computer_Architecture/03_Clock_Reset/Clock25_Reset20_tb.vcd"
+[dumpfile_mtime] "Thu Dec 29 21:51:50 2022"
+[dumpfile_size] 2320447
+[savefile] "/home/micha/gitlab/nand2tetris-fpga/05_Computer_Architecture/03_Clock_Reset/Clock25_Reset20_tb.gtkw"
+[timestart] 0
+[size] 1636 438
+[pos] -1 -1
+*-17.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 80
+[sst_expanded] 1
+[sst_vpaned_height] 76
+@28
+Clock25_Reset20_tb.CLK
+Clock25_Reset20_tb.clk
+@29
+Clock25_Reset20_tb.reset
+[pattern_trace] 1
+[pattern_trace] 0

05_Computer_Architecture/03_Clock25_Reset20/Clock25_Reset20_tb.v

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+`timescale 10ns/1ns
+`default_nettype none
+module Clock25_Reset20_tb();
+
+	// IN,OUT
+	reg CLK=1;
+	wire clk;
+	wire reset;
+	
+	// Part
+	Clock25_Reset20 CLOCK25_RESET20(
+		.CLK(CLK),
+		.clk(clk),
+		.reset(reset)
+	);
+
+	// Simulation
+	always #0.5 CLK=~CLK;
+	
+	// Test  
+  	initial begin
+  		$dumpfile("Clock25_Reset20_tb.vcd");
+  		$dumpvars(0, Clock25_Reset20_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Clock25_Reset10");
+
+		#4000	
+		$finish;
+	end
+
+endmodule

05_Computer_Architecture/03_Clock25_Reset20/Include.v

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+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+`include "../../01_Boolean_Logic/Mux4Way16.v"
+`include "../../01_Boolean_Logic/Mux8Way16.v"
+`include "../../01_Boolean_Logic/DMux4Way.v"
+`include "../../01_Boolean_Logic/DMux8Way.v"
+
+`include "../../02_Boolean_Arithmetic/HalfAdder.v"
+`include "../../02_Boolean_Arithmetic/FullAdder.v"
+`include "../../02_Boolean_Arithmetic/Add16.v"
+`include "../../02_Boolean_Arithmetic/Inc16.v"
+`include "../../02_Boolean_Arithmetic/ALU.v"
+
+`include "../../03_Sequential_Logic/DFF.v"
+`include "../../03_Sequential_Logic/Bit.v"
+`include "../../03_Sequential_Logic/Register.v"
+`include "../../03_Sequential_Logic/PC.v"
+`include "../../03_Sequential_Logic/BitShift9R.v"
+`include "../../03_Sequential_Logic/BitShift8L.v"
+
+`include "../../05_Computer_Architecture/Clock25_Reset20.v"

05_Computer_Architecture/03_Clock25_Reset20/apio.ini

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+[env]
+board = iCE40-HX1K-EVB
+