added v2.0

05_Computer_Architecture/01_CPU/CPU_tb.gtkw

@@ -0,0 +1,48 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Fri Dec 23 09:59:16 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/05_Computer_Architecture/01_CPU/CPU_tb.vcd"
+[dumpfile_mtime] "Fri Dec 23 09:58:03 2022"
+[dumpfile_size] 3204741
+[savefile] "/home/micha/gitlab/nand2tetris/05_Computer_Architecture/01_CPU/CPU_tb.gtkw"
+[timestart] 0
+[size] 1866 600
+[pos] -1 -1
+*-3.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] CPU_tb.
+[sst_width] 281
+[signals_width] 210
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@28
+CPU_tb.clk
+@200
+-IN
+@22
+CPU_tb.inM[15:0]
+CPU_tb.instruction[15:0]
+@28
+CPU_tb.reset
+@200
+-OUT
+@22
+CPU_tb.addressM[15:0]
+CPU_tb.outM[15:0]
+CPU_tb.pc[15:0]
+@28
+CPU_tb.writeM
+@200
+-CMP
+@22
+CPU_tb.addressM_cmp[15:0]
+CPU_tb.out_cmp[15:0]
+CPU_tb.pc_cmp[15:0]
+@28
+CPU_tb.writeM_cmp
+@200
+-Test
+@28
+CPU_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

05_Computer_Architecture/01_CPU/CPU_tb.v

@@ -0,0 +1,86 @@
+`default_nettype none
+module CPU_tb();
+
+	// IN,OUT
+	reg clk=1;
+    reg [15:0] inM=0;
+   	reg [15:0] instruction=0;
+	reg reset=1;
+    wire [15:0] outM;
+    wire writeM;
+    wire [15:0] addressM;
+    wire [15:0] pc;
+	
+	// Part
+	CPU CPU(
+		.clk(clk),
+		.inM(inM),
+		.instruction(instruction),
+		.reset(reset),
+		.outM(outM),
+		.writeM(writeM),
+		.addressM(addressM),
+		.pc(pc)
+	);
+
+	// Simulation
+	always #1 clk=~clk;
+	always @(posedge clk) begin
+		inM <= $random;
+		reset <= (n<=10) || ((n>20) && (n<40));
+		instruction <= $random;	
+	end
+
+	// Compare	
+	reg [15:0] addressM_cmp=0;
+	reg [15:0] regD=0;
+	reg [15:0] pc_cmp=0;
+	reg zx,nx,zy,ny,f,no;
+	wire [15:0] out_cmp;
+	wire [15:0] x,y;
+	wire zr,ng;
+	assign x = instruction[10]?(instruction[11]?~0:~regD):(instruction[11]?0:regD);
+	assign y = instruction[8]?(instruction[9]?~0:~(instruction[12]?inM:addressM_cmp)):(instruction[9]?0:(instruction[12]?inM:addressM_cmp));
+	assign out_cmp = instruction[6]?(instruction[7]?~(x+y):~(x&y)):(instruction[7]?(x+y):(x&y));
+	wire comp;
+	wire jmp;
+	assign comp = instruction[15] && instruction[14] && instruction[13];
+	assign zr = (out_cmp==0);
+	assign ng = out_cmp[15];
+	assign jmp = comp && ((ng&&instruction[2])||(zr&&instruction[1])||(~(ng|zr)&&instruction[0]));
+	always @(posedge clk) begin
+		addressM_cmp <= comp?(instruction[5]?out_cmp:addressM_cmp) : instruction;
+		regD <= comp?(instruction[4]?out_cmp:regD) : regD;
+		pc_cmp <= reset?0 : (jmp?addressM_cmp:pc_cmp+1);
+	end
+	wire writeM_cmp;
+	assign writeM_cmp = comp?instruction[3]:0;
+	
+	reg fail = 0;
+	reg [15:0] n = 0;
+	task check;
+		#1
+		if ((pc != pc_cmp) || (addressM != addressM_cmp) || (outM != out_cmp) || (writeM != writeM_cmp)) 
+			begin
+				$display("FAIL: clk=%1b, inM=%16b, instruction=%16b, reset=%1b, outM=%16b, writeM=%1b, addressM=%16b, pc=%16b",clk,inM,instruction,reset,outM,writeM,addressM,pc);
+				fail=1;
+			end
+	endtask
+	
+	// Test  
+  	initial begin
+  		$dumpfile("CPU_tb.vcd");
+  		$dumpvars(0, CPU_tb);
+		
+		$display("------------------------");
+		$display("Testbench: CPU");
+
+		for (n=0; n<1000;n=n+1) 
+			check();
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

05_Computer_Architecture/01_CPU/Include.v

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+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+`include "../../01_Boolean_Logic/Mux4Way16.v"
+`include "../../01_Boolean_Logic/Mux8Way16.v"
+`include "../../01_Boolean_Logic/DMux4Way.v"
+`include "../../01_Boolean_Logic/DMux8Way.v"
+
+`include "../../02_Boolean_Arithmetic/HalfAdder.v"
+`include "../../02_Boolean_Arithmetic/FullAdder.v"
+`include "../../02_Boolean_Arithmetic/Add16.v"
+`include "../../02_Boolean_Arithmetic/Inc16.v"
+`include "../../02_Boolean_Arithmetic/ALU.v"
+
+`include "../../03_Sequential_Logic/DFF.v"
+`include "../../03_Sequential_Logic/Bit.v"
+`include "../../03_Sequential_Logic/Register.v"
+`include "../../03_Sequential_Logic/PC.v"
+`include "../../03_Sequential_Logic/BitShift9R.v"
+`include "../../03_Sequential_Logic/BitShift8L.v"
+
+`include "../../05_Computer_Architecture/CPU.v"

05_Computer_Architecture/01_CPU/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+