added v2.0

03_Sequential_Logic/08_blinky/Include.v

@@ -0,0 +1,24 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+
+`include "../../02_Boolean_Arithmetic/HalfAdder.v"
+`include "../../02_Boolean_Arithmetic/FullAdder.v"
+`include "../../02_Boolean_Arithmetic/Add16.v"
+`include "../../02_Boolean_Arithmetic/Inc16.v"
+
+`include "../../03_Sequential_Logic/DFF.v"
+`include "../../03_Sequential_Logic/Bit.v"
+`include "../../03_Sequential_Logic/Register.v"
+`include "../../03_Sequential_Logic/PC.v"

03_Sequential_Logic/08_blinky/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+

03_Sequential_Logic/08_blinky/blinky.v

@@ -0,0 +1,19 @@
+// Test to run on fpga with 100 MHz
+
+`default_nettype none
+module blinky(
+	input CLK,
+	output [1:0] LED
+);
+
+	wire [15:0] prescaler;
+	wire clk;
+	PC PRESCALER(.clk(CLK),.load(1'b0),.in(16'b0),.reset(1'b0),.inc(1'b1),.out(prescaler));
+	Buffer 	CLOCK(.in(prescaler[12]),.out(clk));
+
+	wire [15:0] counter;
+	PC COUNTER(.clk(clk),.load(1'b0),.in(16'b0),.reset(1'b0),.inc(1'b1),.out(counter));
+	Buffer BUF1(.in(counter[15]),.out(LED[1]));
+	Buffer BUF2(.in(counter[14]),.out(LED[0]));
+
+endmodule

03_Sequential_Logic/08_blinky/blinky_tb.gtkw

@@ -0,0 +1,26 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Fri Dec 30 09:21:12 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/06_Blinky/blinky_tb.vcd"
+[dumpfile_mtime] "Fri Dec 30 09:19:51 2022"
+[dumpfile_size] 30570990
+[savefile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/06_Blinky/blinky_tb.gtkw"
+[timestart] 0
+[size] 1746 387
+[pos] 46 72
+*-2.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] blinky_tb.
+[sst_width] 281
+[signals_width] 180
+[sst_expanded] 1
+[sst_vpaned_height] 58
+@28
+blinky_tb.CLK
+@22
+blinky_tb.blinky.prescaler[15:0]
+blinky_tb.blinky.counter[15:0]
+@29
+blinky_tb.LED[1:0]
+[pattern_trace] 1
+[pattern_trace] 0

03_Sequential_Logic/08_blinky/blinky_tb.v

@@ -0,0 +1,24 @@
+`default_nettype none
+module blinky_tb();
+
+	// IN,OUT
+	reg CLK=1;
+	wire[1:0] LED;
+
+	// Part
+	blinky blinky(
+		.CLK(CLK),
+		.LED(LED)
+	);
+	
+	// Simulate
+	always #1 CLK=~CLK;
+
+  	initial begin
+  		$dumpfile("blinky_tb.vcd");
+  		$dumpvars(0, blinky_tb);
+		#100000
+		$finish;
+	end
+
+endmodule

03_Sequential_Logic/08_blinky/iCE40HX1K.pcf

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+# physical constrain file
+# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB
+# compare to the schematic of the board and the datasheet of fpga
+
+set_io CLK 15	# CLK (100 Mhz)
+
+set_io BUT[0] 41	# BUT1
+set_io BUT[1] 42	# BUT2
+
+set_io LED[0] 40	# LED1
+set_io LED[1] 51	# LED2
+